19-0433; Rev 0; 9/95

Full-Featured µP Supervisory Circuit with

±1.5% Reset Accuracy
_______________General Description ____________________________Features

MAX807L/M/N
The MAX807 microprocessor (µP) supervisory circuit ♦ Precision 4.675V (MAX807L) or 4.425V
reduces the complexity and number of components (MAX807M), or 4.575V (MAX807N) Voltage
needed to monitor power-supply and battery-control func-
Monitoring
tions in µP systems. A 70µA supply current makes the
MAX807 ideal for use in portable equipment, while a 2ns ♦ 200ms Power OK / Reset Time Delay
chip-enable propagation delay and 250mA output current ♦ RESET and RESET Outputs
capability (20mA in battery-backup mode) make it suit-
able for larger, higher-performance equipment. ♦ Independent Watchdog Timer
The MAX807 comes in 16-pin DIP and SO packages, and ♦ 1µA Standby Current
provides the following functions:
♦ Power Switching:
1) µP reset. The active-low RESET output is asserted dur-
250mA in VCC Mode
ing power-up, power-down, and brownout conditions,
20mA in Battery-Backup Mode
and is guaranteed to be in the correct state for VCC
down to 1V. ♦ On-Board Gating of Chip-Enable Signals:
2) Active-high RESET output. 2ns CE Gate Propagation Delay
3) Manual-reset input. ♦ MaxCap™ and SuperCap™ Compatible
4) Two-stage power-fail warning. A separate low-line ♦ Voltage Monitor for Power-Fail
comparator compares VCC to a threshold 52mV above
the reset threshold. This low-line comparator is more ♦ Backup-Battery Monitor
accurate than those in previous µP supervisors. ♦ Guaranteed RESET Valid to VCC = 1V
5) Backup-battery switchover for CMOS RAM, real-time ♦ ±1.5% Low-line Threshold Accuracy 52mV above
clocks, µPs, or other low-power logic.
Reset Threshold
6) Write protection of CMOS RAM or EEPROM.
7) 2.275V threshold detector—provides for power-fail
warning and low-battery detection, or monitors a
power supply other than +5V.
8) BATT OK status flag indicates that the backup-battery __________________Pin Configuration
voltage is above 2.275V.
9) Watchdog-fault output—asserted if the watchdog input
has not been toggled within a preset timeout period.
TOP VIEW
________________________Applications PFI 1 16 OUT
Computers PFO 2 15 BATT OK
Controllers VCC 3 14 BATT
Intelligent Instruments WDI 4 MAX807 13 BATT ON
Critical µP Power Monitoring GND 5 12 CE IN

Portable/Battery-Powered Equipment MR 6 11 CE OUT

LOW LINE 7 10 WDO
RESET 8 9 RESET

DIP/SO

Ordering Information and Typical Operating Circuit appear at end of data sheet.
SuperCap is a trademark of Baknor Industries. MaxCap is a trademark of The Carborundum Corp.

________________________________________________________________ Maxim Integrated Products 1

Call toll free 1-800-998-8800 for free samples or literature.

 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
ABSOLUTE MAXIMUM RATINGS
MAX807L/M/N

Input Voltages (with respect to GND) Continuous Power Dissipation (TA = +70°C)
VCC ..........................................................................-0.3V to 6V Plastic DIP (derate 10.53mW/°C above +70°C) ...........842mW
VBATT .......................................................................-0.3V to 6V Wide SO (derate 9.52mW/°C above +70°C).................762mW
All Other Inputs......................................-0.3V to (VOUT + 0.3V) CERDIP (derate 10.00mW/°C above +70°C) ................800mW
Input Current Operating Temperature Ranges
VCC Peak ...........................................................................1.0A MAX807_C_E .......................................................0°C to +70°C
VCC Continuous .............................................................500mA MAX807_E_E ....................................................-40°C to +85°C
IBATT Peak......................................................................250mA MAX807_MJE .................................................-55°C to +125°C
IBATT Continuous .............................................................50mA Storage Temperature Range .............................-65°C to +160°C
GND .................................................................................50mA Lead Temperature (soldering, 10sec) .............................+300°C
All Other Inputs ................................................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V CC = 4.60V to 5.5V for the MAX807L, VCC = 4.50V to 5.5V for the MAX807N, VCC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0V, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range
0 5.5 V
VBATT, VCC (Note 1)
IOUT = 25mA VCC - 0.02
IOUT = 250mA,
VCC - 0.35 VCC - 0.22
VOUT in Normal Operating VCC = 4.5V MAX807C/E
V
Mode IOUT = 250mA,
VCC - 0.45
MAX807M
VCC = 3V, VBATT = 2.8V, IOUT = 100mA VCC - 0.25 VCC - 0.12
VCC = 4.5V, MAX807C/E 1.0 1.4
VCC to OUT On-Resistance IOUT = 250mA MAX807M 1.8 Ω
VCC = 3V, IOUT = 100mA 1.2 2.5
VBATT = 4.5V, IOUT = 20mA, VCC = 0V VBATT - 0.17
VOUT in Battery-Backup Mode VBATT = 2.8V, IOUT = 10mA, VCC = 0V VBATT - 0.25 VBATT - 0.12 V
VBATT = 2.0V, IOUT = 5mA, VCC = 0V VBATT - 0.20 VBATT - 0.08
VBATT = 4.5V, IOUT = 20mA 8.5
BATT to OUT On-Resistance VBATT = 2.8V, IOUT = 10mA 12 25 Ω
VBATT = 2.0V, IOUT = 5mA 16 40
Supply Current in Normal
70 110 µA
Operating Mode (excludes IOUT)
Supply Current in Battery- TA = +25°C 0.4 1
Backup Mode (excludes IOUT) VCC = 0V, VBATT = 2.8V MAX807C/E 5 µA
(Note 2) MAX807M 50

TA = +25°C -0.1 0.1

BATT Standby Current (Note 3) VBATT + 0.2V ≤ VCC µA
TA = TMIN to
-1.0 1.0
TMAX
Power up VBATT + 0.05
Battery-Switchover Threshold VBATT = 2.8V V
Power down VBATT
Battery-Switchover Hysteresis 50 mV
BATT ON Output, Low Voltage VRST (max), ISINK = 3.2mA 0.1 0.4 V
BATT ON Output, High Voltage VCC = 0V, ISOURCE = 0.1mA, VBATT = 2.8V 2 2.7 V

2 _______________________________________________________________________________________
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
ELECTRICAL CHARACTERISTICS (continued)

MAX807L/M/N
(V CC = 4.60V to 5.5V for the MAX807L, VCC = 4.50V to 5.5V for the MAX807N, VCC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0V, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BATT ON Output Sink current 70
mA
Short-Circuit Current Source current, VCC = 0V, VBATT = 2.8V 5
RESET, LOW LINE, AND WATCHDOG TIMER
MAX807L 4.600 4.675 4.750
Reset Threshold VRST VCC rising and falling MAX807N 4.500 4.575 4.650 V
MAX807M 4.350 4.425 4.500
Reset Threshold Hysteresis 13 mV
LOW LINE to RESET
VLR VCC falling 30 52 70 mV
Threshold Voltage
MAX807L 4.73 4.81
LOW LINE Threshold,
VLL MAX807N 4.63 4.71 V
VCC Rising
MAX807M 4.48 4.56
VCC to RESET Delay VCC falling at 1mV/µs 26 µs
VCC to LOW LINE Delay VCC falling at 1mV/µs 24 µs
RESET Active Timeout Period tRP VCC rising 140 200 280 ms
Watchdog Timeout Period tWD 1.12 1.6 2.24 sec
Minimum Watchdog Input
VIL = 0.8V, VIH = 0.75 x VCC 100 ns
Pulse Width
VCC = 1V,
0.3
ISINK = 50µA, MAX807_C
VBATT = 0V, VCC falling VCC = 1.2V,
RESET Output Voltage 0.3 V
MAX807_E/M
ISINK = 3.2mA, VCC = 4.25V 0.1 0.4
ISOURCE = 0.1mA VCC - 1.5 VCC - 0.1
RESET Output Output sink current, VCC = 4.25V 60
ISC mA
Short-Circuit Current Output source current 1.6
ISINK = 3.2mA 0.4
RESET Output Voltage V
ISOURCE = 5mA VCC - 1.5
RESET Output Output sink current 60
ISC mA
Short-Circuit Current Output source current, VCC = 4.25V 15
ISINK = 3.2mA, VCC = 4.25V 0.4
LOW LINE Output Voltage V
ISOURCE = 5mA VCC - 1.5
LOW LINE Output Output sink current, VCC = 4.25V 28
ISC mA
Short-Circuit Current Output source current 20
ISINK = 3.2mA 0.4
WDO Output Voltage V
ISOURCE = 5mA VCC - 1.5
WDO Output Output sink current 35
ISC mA
Short-Circuit Current Output source current 20
WDI Threshold Voltage VIH 0.75 x VCC
V
(Note 4) VIL 0.8
VIH Reset deasserted, WDI = 0V -50 -10
WDI Input Current µA
Reset deasserted, WDI = VCC 16 50

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 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
ELECTRICAL CHARACTERISTICS (continued)
MAX807L/M/N

(V CC = 4.60V to 5.5V for the MAX807L, VCC = 4.50V to 5.5V for the MAX807N, VCC = 4.35V to 5.5V for the MAX807M,
VBATT = 2.8V, VPFI = 0V, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VPFI falling 2.20 2.265 2.33
PFI Input Threshold VPFT V
VPFI rising 2.22 2.285 2.35
PFI Hysteresis 20 mV
PFI Leakage Current ±0.005 ±40 nA
PFI to PFO Delay (Note 5) VOD = 30mV, VPFI falling 14 µs
CHIP-ENABLE GATING
CE IN Leakage Current Disabled mode, MR = 0V ±0.00002 ±1 µA
CE IN to CE OUT Resistance
Enabled mode, VCC = VRST (max) 75 150 Ω
(Note 6)
CE OUT Short-Circuit Current VCC = 5V, disabled mode,
17 mA
(RESET active) CE OUT = 0V, MR = 0V
CE IN to CE OUT VCC = 5V, CLOAD = 50pF,
2 8 ns
Propagation Delay (Note 7) 50Ω source impedance driver
VCC = 5V,
3.5
CE OUT Output Voltage High IOUT = 2mA
Disabled mode, MR = 0V V
(RESET active) VCC = 0V,
VBATT - 0.1 VBATT
IOUT = 10µA
RESET to CE OUT Delay VCC falling 28 µs
MANUAL RESET INPUT
MR Minimum Pulse Input 1 µs
MR-to-RESET Propagation
170 ns
Delay
VIH 2.4
MR Threshold V
VIL 0.8
MR Pull-Up Current MR = 0V 50 100 200 µA
BATT OK COMPARATOR
BATT OK Threshold VBOK 2.200 2.265 2.350 V
BATT OK Hysteresis 20 mV
LOGIC OUTPUTS
Output Voltage VOL ISINK = 3.2mA 0.4
V
(PFO, BATT OK) VOH ISOURCE = 5mA VCC - 1.5
Output sink current 35
Output Short-Circuit Current ISC mA
Output source current 20

Note 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V.
Note 2: The supply current drawn by the MAX807 from the battery (excluding IOUT) typically goes to 15µA when (VBATT - 0.1V)
< VCC < VBATT. In most applications, this is a brief period as VCC falls through this region (see Typical Operating Characteristics).
Note 3: “+”= battery discharging current, “-”= battery charging current.
Note 4: WDI is internally connected to a voltage divider between VCC and GND. If unconnected, WDI is driven to 1.8V (typical),
disabling the watchdog function.
Note 5: Overdrive (VOD) is measured from center of hysteresis band.
Note 6: The chip-enable resistance is tested with V CE IN = VCC/2, and I CE IN = 1mA.
Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.

4 _______________________________________________________________________________________
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
__________________________________________Typical Operating Characteristics

MAX807L/M/N
(VCC = 5V, VBATT = 2.8V, PFI = 0V, no load, TA = +25°C, unless otherwise noted.)

VCC SUPPLY CURRENT vs. TEMPERATURE BATTERY SUPPLY CURRENT vs. CHIP-ENABLE PROPAGATION DELAY
(NORMAL OPERATING MODE) TEMPERATURE (BATTERY-BACKUP MODE) vs. TEMPERATURE
80 3.0 6

MAX807-02
MAX807-01

MAX807-03
78
BATTERY SUPPLY CURRENT (µA)

2.5 5
VCC SUPPLY CURRENT (µA)

PROPAGATION DELAY (ns)

76
74 2.0 4
72
70 1.5 3
68
1.0 2
66
64 0.5 1
62
60 0 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

BATT-to-OUT ON-RESISTANCE VCC-to-OUT ON-RESISTANCE PFI THRESHOLD

vs. TEMPERATURE vs. TEMPERATURE vs. TEMPERATURE (VPFI FALLING)
30 1.6 2.340
MAX807-05
MAX807-04

MAX807-06
VCC = 0V IOUT = 250mA
1.5
BATT-to-OUT ON-RESISTANCE (Ω)

IOUT = 10mA 2.320

VCC-to-OUT ON-RESISTANCE (Ω)

25 1.4
PFI THRESHOLD (V)

2.300
1.3
20 VBATT = 2.0V
1.2 2.280

1.1 2.260
15
VBATT = 2.8V 1.0
2.240
10 0.9
VBATT = 4.5V 2.220
0.8

5 0.7 2.200
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

RESET THRESHOLD RESET TIMEOUT PERIOD LOW LINE -to-RESET THRESHOLD

vs. TEMPERATURE vs. TEMPERATURE (VCC RISING) vs. TEMPERATURE (VCC FALLING)
4.70 280 80
MAX807-09
MAX807-08
MAX807-07

LOW LINE-to-RESET THRESHOLD (mV)

260 70
RESET TIMEOUT PERIOD (ms)

4.65
MAX807L
60
RESET THRESHOLD (V)

240
4.60
50
220
4.55 MAX807N 40
200
30
4.50
180
20
4.45 160 10
MAX807M
4.40 140 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

_______________________________________________________________________________________ 5
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
____________________________Typical Operating Characteristics (continued)
MAX807L/M/N

(VCC = 5V, VBATT = 2.8V, PFI = 0V, no load, TA = +25°C, unless otherwise noted.)

LOW LINE THRESHOLD LOW LINE COMPARATOR PROPAGATION RESET COMPARATOR PROPAGATION
vs. TEMPERATURE (VCC RISING) DELAY vs. TEMPERATURE (VCC FALLING) DELAY vs. TEMPERATURE (VCC FALLING)
4.80 40 40
MAX807-10

MAX807-11

MAX807-12
LOW LINE COMPARATOR PROP. DELAY (µs)

RESET COMPARATOR PROP. DELAY (µs)

4.75 “L” VERSION 35 VCC FALLING AT 1mV/µs 35 VCC FALLING AT 1mV/µs
LOW LINE THRESHOLD (V)

4.70 30 30

4.65 “N” VERSION 25 25

4.60 20 20

4.55 15 15

4.50 “M” VERSION 10 10

4.45 5 5
4.40 0 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)

BATTERY CURRENT CHIP-ENABLE PROPAGATION DELAY BATT-to-OUT vs.

vs. INPUT SUPPLY VOLTAGE vs. CE OUT LOAD CAPACITANCE OUTPUT CURRENT
16 8 1000
MAX807-14
MAX807-13

MAX807-15
VCC = 0V
14
PROPAGATION DELAY (ns)
BATTERY CURRENT (µA)

12 6
BATT-to-OUT (mV)

10

8 4 100

4 2

2
50Ω DRIVER SLOPE = 12Ω
0 0 10
2.5 2.6 2.7 2.8 2.9 3.0 0 50 100 1 10 100
VCC (V) CLOAD (pF) IOUT (mA)

VCC-to-OUT vs. MAXIMUM TRANSIENT DURATION vs.

OUTPUT CURRENT RESET COMPARATOR OVERDRIVE
1000 1000
MAX807-16

MAX807-17
MAXIMUM TRANSIENT DURATION (µs)

RESET OCCURS
VCC-VOUT (mV)

100 100

SLOPE = 1.0Ω
10 10

1 1
1 10 100 1000 1 10 100 1000
IOUT (mA) RESET COMPARATOR OVERDRIVE (mV)

6 _______________________________________________________________________________________
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________Pin Description

MAX807L/M/N
PIN NAME FUNCTION

1 PFI Power-Fail Input. When PFI is less than VPFT (2.265V), PFO goes low. Connect to ground when unused.
Power-Fail Output. This CMOS-logic output goes low when PFI is less than VPFT (2.265V). Valid for
2 PFO
VCC ≥ 4V. PFO swings between VCC and GND.
3 VCC Input Supply Voltage, nominally +5V. Bypass with a 0.1µF capacitor to GND.
Watchdog Input. If WDI remains high or low longer than the the watchdog timeout period (1.6sec
4 WDI
typical), WDO goes low. Leave unconnected to disable the watchdog function.
5 GND Ground

Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low
and for 200ms after MR returns high. MR is an active-low input with an internal pull-up to VCC. It can be
6 MR
driven using TTL or CMOS logic, or shorted to ground with a switch. Connect to VCC, or leave uncon-
nected if not used.

Low-Line Comparator Output. This CMOS-logic output goes low when VCC falls to 52mV above the reset
7 LOW LINE threshold. Use this output to generate an NMI to initiate an orderly shutdown routine when VCC is falling.
LOW LINE swings between VCC and GND.

Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks
8 RESET
current. RESET swings between VCC and GND.
Active-Low Reset Output. RESET is triggered and stays low when VCC is below the reset threshold or
when MR is low. It remains low 200ms after VCC rises above the reset threshold or MR returns high.
9 RESET
RESET has a strong pull-down but a relatively weak pull-up, and can be wire-OR connected to logic
gates. Valid for VCC ≥ 1V. RESET swings between VCC and GND.
Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watch-
dog timeout period (tWD), and remains low until the next transition of WDI. WDO remains high if WDI is
10 WDO
unconnected. WDO is high during reset. WDO swings between VCC and GND. Connect WDO to MR to
generate resets during watchdog faults.
Chip-Enable Output. Output to the chip-enable gating circuit. CE OUT is pulled up to the higher of VCC
11 CE OUT
or VBATT, when the chip-enable gate is disabled.
12 CE IN Chip-Enable Input

Battery On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to
BATT and low when OUT is connected to VCC. Connect the base of a PNP transistor or gate of a PMOS
13 BATT ON
transistor to BATT ON for IOUT requirements exceeding 250mA. BATT ON swings between the higher of
VCC and VBATT, and GND.

Backup-Battery Input. When VCC falls below the reset threshold and VBATT, OUT switches from VCC to
BATT. VBATT may exceed VCC. The battery can be removed while the MAX807 is powered-up, provided
14 BATT
BATT is bypassed with a 0.1µF capacitor to GND. If no battery is used, connect BATT to ground, and
connect VCC and OUT together.
Battery OK Signal Output. High in normal operating mode when VBATT exceeds VBOK (2.265V). Valid for
15 BATT OK
VCC ≥ 4V.

Output Supply Voltage to CMOS RAM. When VCC exceeds the reset threshold or VCC > VBATT, OUT is
16 OUT connected to VCC. When VCC falls below the reset threshold and VBATT, OUT connects to BATT. Bypass
OUT with a 0.1µF capacitor to GND.

_______________________________________________________________________________________ 7
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
_______________Detailed Description RESET and RESET Outputs
MAX807L/M/N

The MAX807’s RESET output ensures that the µP pow-

The MAX807 microprocessor (µP) supervisory circuit
ers up in a known state, and prevents code execution
provides power-supply monitoring, backup-battery
errors during power-down and brownout conditions. It
switchover, and program execution watchdog functions
accomplishes this by resetting the µP, terminating pro-
in µP systems (Figure 1). Use of BiCMOS technology
gram execution when VCC dips below the reset thresh-
results in an improved 1.5% reset-threshold precision,
old or MR is pulled low. Each time RESET is asserted it
while keeping supply currents typically below 70µA.
stays low for the 200ms reset timeout period, which is
The MAX807 is intended for battery-powered applica-
set by an internal timer to ensure the µP has adequate
tions that require high reset-threshold precision, allow-
time to return to an initial state. Any time V CC goes
ing a wide power-supply operating range while
below the reset threshold before the reset timeout peri-
preventing the system from operating below its speci-
od is completed, the internal timer restarts. The watch-
fied voltage range.
dog timer can also initiate a reset if WDO is connected
to MR. See the Watchdog Input section.

VCC
OUT
BATT
BATTERY-BACKUP
COMPARATOR P

BATT ON

RESET N
COMPARATOR

LOW LINE
LOW-LINE BATT OK
COMPARATOR
PFO

WATCHDOG
TRANSITION WDI
BATTERY-OK DETECTOR
VCC
COMPARATOR

50kΩ
GND

POWER-FAIL MR
PFI COMPARATOR RESET
STATE
MACHINE RESET
OSCILLATOR WDO

2.275V
THE HIGHER
OF VCC OR VBATT

P
MAX807
P
CE IN CE OUT
N

Figure 1. Block Diagram

8 _______________________________________________________________________________________
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy

MAX807L/M/N
VRST VLL VRST + VLR VRST

VCC VCC

VLOW LINE VLOW LINE

VRESET tRP VRESET

VRESET tRP VRESET

VCE OUT VBATT VCE OUT VBATT

SHOWN FOR VCC = 0V to 5V, VBATT = 2.8V, CE IN = GND SHOWN FOR VCC = 5V to 0V, VBATT = 2.8V, CE IN = GND

Figure 2a. Timing Diagram, VCC Rising Figure 2b. Timing Diagram, VCC Falling

The RESET output is active low and implemented with a

strong pull-down/relatively weak pull-up structure. It is
guaranteed to be a logic low for 0V < VCC < VRST, pro- MANUAL RESET
vided VBATT is greater than 2V. Without a backup bat-
tery, RESET is guaranteed valid for VCC ≥ 1. It typically MR
sinks 3.2mA at 0.1V saturation voltage in its active state.
The RESET output is the inverse of the RESET output; it *
both sources and sinks current and cannot be wire-OR OTHER MAX807
connected. RESET
SOURCES *
Manual Reset Input
Many µP-based products require manual-reset capabil-
ity to allow an operator or test technician to initiate a * DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
reset. The Manual Reset (MR) input permits the genera-
tion of a reset in response to a logic low from a switch,
WDO, or external circuitry. Reset remains asserted Figure 3. Diode “OR” connections allow multiple reset sources
while MR is low, and for 200ms after MR returns high. to connect to MR.
MR has an internal 50µA to 200µA pull-up current, so it
Watchdog Timer
can be left open if it is not used. MR can be driven with Watchdog Input
TTL or CMOS-logic levels, or with open-drain/collector The watchdog circuit monitors the µP’s activity. If the
outputs. Connect a normally open momentary switch µP does not toggle the watchdog input (WDI) within
from MR to GND to create a manual-reset function; 1.6sec, WDO goes low. The internal 1.6sec timer is
external debounce circuitry is not required. If MR is dri- cleared and WDO returns high when reset is asserted
ven from long cables or if the device is used in a noisy or when a transition (low-to-high or high-to-low) occurs
environment, connect a 0.1µF capacitor from MR to at WDI while RESET is high. As long as reset is assert-
ground to provide additional noise immunity. As shown ed, the timer remains cleared and does not count. As
in Figure 3, diode-ORed connections can be used to soon as reset is released, the timer starts counting
allow manual resets from multiple sources. Figure 4 (Figure 5). Supply current is typically reduced by 10µA
shows the reset timing. when WDI is at a valid logic level.

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 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
Chip-Enable Signal Gating
MAX807L/M/N

1µs MIN
MR The MAX807 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
170ns the CMOS RAM in the event of a power failure. During
RESET normal operation, the CE gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
CE IN corrupting the CMOS RAM. The MAX807 uses a series
0V transmission gate from the Chip-Enable Input (CE IN) to
CE OUT
the Chip-Enable Output (CE OUT) (Figure 1).
28µs TYP The 8ns max chip-enable propagation from CE IN to CE
OUT enables the MAX807 to be used with most µPs.
Figure 4. Manual-Reset Timing Diagram
Watchdog Output Chip-Enable Input
WDO remains high if there is a transition or pulse at CE IN is high impedance (disabled mode) while RESET
WDI during the watchdog timeout period. WDO goes is asserted. During a power-down sequence when VCC
low if no transition occurs at WDI during the watchdog passes the reset threshold, the CE transmission gate
timeout period. The watchdog function is disabled and disables and CE IN becomes high impedance 28µs
WDO is a logic high when V CC is below the reset after reset is asserted (Figure 7). During a power-up
threshold or WDI is an open circuit. To generate a sys- sequence, CE IN remains high impedance (regardless
tem reset on every watchdog fault, simply diode-OR of CE IN activity) until reset is deasserted following the
connect WDO to MR (Figure 6). When a watchdog fault reset-timeout period.
occurs in this mode, WDO goes low, which pulls MR In the high-impedance mode, the leakage currents into
low, causing a reset pulse to be issued. As soon as this input are ±1µA max over temperature. In the low-
reset is asserted, the watchdog timer clears and WDO impedance mode, the impedance of CE IN appears as
returns high. With WDO connected to MR, a continuous a 75Ω resistor in series with the load at CE OUT.
high or low on WDI will cause 200ms reset pulses to be
The propagation delay through the CE transmission
issued every 1.6sec.
gate depends on both the source impedance of the
drive to CE IN and the capacitive loading on CE OUT

VRST
VCC
4.7k
VCC
MAX807
WDO
tRP RESET TO µP
RESET
MR

WDO
VCC

tWD WDO
∼50µs

WDI
RESET tRP tWD tRP

WDI
WDO CONNECTED TO µP INTERRUPT

Figure 5. Watchdog Timing Relationship Figure 6. Generating a Reset on Each Watchdog Fault

10 ______________________________________________________________________________________
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy

MAX807L/M/N
VRST MAX
VCC
RESET
THRESHOLD VCC

CE IN

MAX807
CE OUT CE IN CE OUT
28µs
26µs 26µs 50pF
50Ω DRIVER CLOAD
RESET

GND
RESET

Figure 7. Reset and Chip-Enable Timing Figure 8. CE Propagation Delay Test Circuit

(see the Chip-Enable Propagation Delay vs. CE OUT

Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 8). For minimum propagation 4.5V to 5.5V
REGULATOR VCC LOW LINE TO µP NMI
delay, minimize the capacitive load at CE OUT and use
a low output-impedance driver. CHOLD

Chip-Enable Output MAX807

In the enabled mode, the impedance of CE OUT is equiv-
alent to 75Ω in series with the source driving CE IN. In the
disabled mode, the 75Ω transmission gate is off and CE
CHOLD > ILOAD x tSHDN
OUT is actively pulled to the higher of VCC or VBATT. This VLR
source turns off when the transmission gate is enabled. GND

Low-Line Comparator
The low-line comparator monitors VCC with a threshold
voltage typically 52mV above the reset threshold, with
13mV of hysteresis. Use LOW LINE to provide a non-
Figure 9. Using LOW LINE to Provide a Power-Fail Warning to
maskable interrupt (NMI) to the µP when power begins
the µP
to fall, to initiate an orderly software shutdown routine.
In most battery-operated portable systems, reserve worst-case shutdown time, the worst-case load current,
energy in the battery provides ample time to complete and the minimum low-line to reset threshold (VLR(min)),
the shutdown routine once the low-line warning is calculate the amount of capacitance required to allow the
encountered, and before reset asserts. If the system shutdown routine to complete before reset is asserted:
must contend with a more rapid VCC fall time—such as
CHOLD = (ILOAD x tSHDN) / VLR (min)
when the main battery is disconnected, a DC-DC con-
verter shuts down, or a high-side switch is opened dur- where tSHDN is the time required for the system to com-
ing normal operation—use capacitance on the VCC line plete the shutdown routine, and includes the VCC to
to provide time to execute the shutdown routine (Figure low-line propagation delay; and where ILOAD is the cur-
9). First calculate the worst-case time required for the rent being drained from the capacitor, VLR is the low-
system to perform its shutdown routine. Then, with the line to reset threshold.

______________________________________________________________________________________ 11
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
MAX807L/M/N

VIN

VCC VCC
R1 R1

PFI
MAX807 PFO MAX807
PFI PFO
R2
R2

MR
GND GND

VIN
VCC VCC

PFO PFO
VIN VIN
VL VTRIP 0V VTRIP VH

1 1 VCC R1 + R2
VTRIP = R2 (VPFT + VPFH) ( R1 + R2 ) – R1 VTRIP = VPFT ( R2 )
WHERE VPFT = 2.265V
1 1 VCC VPFH = 20mV R1 + R2
VL = R2 (VPFT) ( +
R1 R2 ) –
R1 NOTE: VTRIP, VL ARE NEGATIVE
VH = (VPFT + VPFH)
R2( )
a) b)
Figure 10. Using the Power-Fail Comparator to Monitor an Additional Power Supply: a) VIN is Negative, b) VIN is Positive

Power-Fail Comparator
FROM
REGULATED µP POWER
PFI is the noninverting input to an uncommitted com-
SUPPLY VCC OUT POWER TO
parator. If PFI is less than VPFT (2.265V), PFO goes low.
0.1µF 0.1µF CMOS RAM The power-fail comparator is intended to monitor the
MAX807 preregulated input of the power supply, providing an
BATT early power-fail warning so software can conduct an
µP orderly shutdown. It can also be used to monitor sup-
2.8V
plies other than 5V. Set the power-fail threshold with a
resistor divider, as shown in Figure 10.
RESET RESET
LOW LINE NMI Power-Fail Input
WDI I/O LINE PFI is the input to the power-fail comparator. The typical
GND
a) comparator delay is 14µs from VIL to VOL (power failing),
and 32µs from VIH to VOH (power being restored). If
unused, connect this input to ground.
µP POWER
VCC OUT Power-Fail Output
POWER TO
0.1µF 0.1µF CMOS RAM The Power-Fail Output (PFO) goes low when PFI goes
VOLTAGE MAX807 below VPFT. It typically sinks 3.2mA with a saturation
REGULATOR BATT voltage of 0.1V. With PFI above VPFT, PFO is actively
µP pulled to VCC. Connecting PFI through a voltage divider
2.8V
to a preregulated supply allows PFO to generate an
NMI as the preregulated power begins to fall (Figure
RESET RESET 11b). If the preregulated supply is inaccessible, use
PFI PFO NMI LOW LINE to generate the NMI (Figure 11a). The LOW
WDI I/O LINE
GND
LINE threshold is typically 52mV above the reset
threshold (see Low-Line Comparator section).

b)
Figure 11. a) If the preregulated supply is inaccessible, LOW
LINE generates the NMI for the µP. b) Use PFO to generate the
µP NMI if the preregulated supply is accessible.

12 ______________________________________________________________________________________
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy

MAX807L/M/N
Table 1. Input and Output Status in Battery-Backup Mode
PIN NAME FUNCTION
1 PFI The power-fail comparator remains active in battery-backup mode for VCC ≥ 4V.
2 PFO The power-fail comparator remains active in battery-backup mode for VCC ≥ 4V. Below 4V, PFO is forced low.
3 VCC Battery switchover comparator monitors VCC for active switchover.
4 WDI WDI is ignored and goes high impedance.
5 GND Ground—0V reference for all signals.
6 MR MR is ignored.
7 LOW LINE Logic low.
8 RESET Logic high; the open-circuit output voltage is equal to VCC.
9 RESET Logic low.
10 WDO Logic high. The open-circuit output voltage is equal to VCC.
11 CE OUT Logic high. The open-circuit output voltage is equal to VBATT.
12 CE IN High impedance.
13 BATT ON Logic high. The open-circuit output voltage is equal to VBATT.
14 BATT Supply current is 1µA maximum for VBATT ≤ 2.8V.
15 BATT OK Logic high when VBATT exceeds 2.285V. Valid for VCC ≥ 4V. Below 4V, BATT OK is forced low.
16 OUT OUT is connected to BATT through two internal PMOS switches in series.

Backup-Battery Input
The BATT input is similar to VCC, except the PMOS
switch is much smaller. This input is designed to con-
MAX807 duct up to 20mA to OUT during battery backup. The
on-resistance of the PMOS switch is approximately
P
VCC 13Ω. Figure 12 shows the two series pass elements
between the BATT input and OUT that facilitates UL
approval. VBATT can exceed VCC during normal opera-
CONTROL OUT tion without causing a reset.
CIRCUITRY
Output Supply Voltage
0.1µF
The output supply (OUT) transfers power from VCC or
BATT to the µP, RAM, and other external circuitry. At
BATT the maximum source current of 250mA, VOUT will typi-
P P
cally be 260mV below VCC. Decouple this terminal with
a 0.1µF capacitor.
BATT ON Output
Figure 12. VCC and BATT-to-OUT Switch The battery on (BATT ON) output indicates the status of
the internal battery switchover comparator, which con-
Battery-Backup Mode trols the internal VCC and BATT switches. For VCC
Battery backup preserves the contents of RAM in the greater than V BATT (ignoring the small hysteresis
event of a brownout or power failure. With a backup effect), BATT ON typically sinks 3.2mA at 0.4V. In bat-
battery installed at BATT, the MAX807 automatically tery-backup mode, this output sources approximately
switches RAM to backup power when VCC falls. Two 5mA. Use BATT ON to indicate battery switchover sta-
conditions are required for switchover to battery-back- tus, or to supply gate or base drive for an external pass
up mode: 1) VCC must be below the reset threshold; 2) transistor for higher current applications (see Typical
VCC must be below VBATT. Table 1 lists the status of Operating Circuit).
inputs and outputs during battery-backup mode.

______________________________________________________________________________________ 13
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
BATT OK Output SuperCap (e.g., order of 0.47F) and a simple charging
MAX807L/M/N

The BATT OK comparator monitors the backup battery circuit as a backup source (Figure 13). Since VBATT can
voltage, comparing it with a 2.265V reference (VCC ≥ exceed VCC while VCC is above the reset threshold,
4V). BATT OK remains high as long as the backup bat- there are no special precautions when using these µP
tery voltage remains above 2.265V, signaling that the supervisors with a SuperCap.
backup battery has sufficient voltage to maintain the
memory of static RAM. When the battery voltage drops Alternative Chip-Enable Gating
below 2.265V, the BATT OK output drops low, signaling Using memory devices with CE and CE inputs allows
that the backup battery needs to be changed. the MAX807 CE loop to be bypassed. To do this, con-
nect CE IN to ground, pull up CE OUT to OUT, and
__________Applications Information connect CE OUT to the CE input of each memory
The MAX807 is not short-circuit protected. Shorting device (Figure 14). The CE input of each part then con-
OUT to ground, other than power-up transients such as nects directly to the chip-select logic, which does not
charging a decoupling capacitor, may destroy the have to be gated by the MAX807.
device. If long leads connect to the IC’s inputs, ensure Adding Hysteresis to the
that these lines are free from ringing and other condi- Power-Fail Comparator
tions that would forward bias the IC’s protection diodes. The power-fail comparator has a typical input hystere-
There are two distinct modes of operation: sis of 20mV. This is sufficient for most applications
1) Normal Operating Mode, with all circuitry powered where a power-supply line is being monitored through
up. Typical supply current from VCC is 70µA, while an external voltage divider (Figure 10).
only leakage currents flow from the battery. Figure 15 shows how to add hysteresis to the power-fail
2) Battery-Backup Mode, where VCC is below VBATT comparator. Select the ratio of R1 and R2 such that PFI
and VRST. The supply current from the battery is typ- sees 2.265V when VIN falls to the desired trip point
ically less than 1µA. (VTRIP). Resistor R3 adds hysteresis. It will typically be
an order of magnitude greater than R1 or R2. The cur-
Using SuperCaps™ or rent through R1 and R2 should be at least 1µA to
MaxCaps™ with the MAX807 ensure that the 25nA (max) PFI input current does not
BATT has the same operating voltage range as VCC, and shift the trip point. R3 should be larger than 10kΩ to
the battery-switchover threshold voltage is typically prevent it from loading down the PFO pin. Capacitor C1
VBATT when VCC is decreasing or VBATT + 0.06V when adds additional noise rejection.
V CC is increasing. This hysteresis allows use of a

Rp*
CE
+5V RAM 1
OUT CE

VCC CE IN CE OUT
1N4148 CE
RAM 2
CE

BATT OUT
MAX807 CE
0.47F RAM 3
CE
MAX807
GND CE
RAM 4
GND CE
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMS.
MINIMUM Rp VALUE IS 1kΩ ACTIVE-HIGH CE
LINES FROM LOGIC

Figure 13. SuperCap or MaxCap on BATT Figure 14. Alternate CE Gating

14 ______________________________________________________________________________________
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
Backup-Battery Replacement

MAX807L/M/N
The backup battery may be disconnected while VCC is
above the reset threshold, provided BATT is bypassed START
with a 0.1µF capacitor to ground. No precautions are
necessary to avoid spurious reset pulses.
SET
Negative-Going VCC Transients WDI
While issuing resets to the µP during power-up, power- LOW
down, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going VCC SUBROUTINE
transients (glitches). It is usually undesirable to reset OR PROGRAM LOOP,
the µP when VCC experiences only small glitches. SET WDI
HIGH
The Typical Operating Characteristics show Maximum
Transient Duration vs. Reset Comparator Overdrive, for
which reset pulses are not generated. The graph was
produced using negative-going VCC pulses, starting at RETURN
5V and ending below the reset threshold by the magni-
tude indicated (reset comparator overdrive). The graph
END
shows the maximum pulse width that a negative-going
V CC transient may typically have without causing a
reset pulse to be issued. As the amplitude of the tran- Figure 16. Watchdog Flow Diagram
sient increases (i.e., goes farther below the reset
threshold), the maximum allowable pulse width A 0.1µF bypass capacitor mounted close to the VCC
decreases. pin provides additional transient immunity.
Typically, a VCC transient that goes 40mV below the
Watchdog Software Considerations
reset threshold and lasts for 3µs or less will not cause a
To help the watchdog timer keep a closer watch on soft-
reset pulse to be issued.
ware execution, you can use the method of setting and
resetting the watchdog input at different points in the
VIN program, rather than “pulsing” the watchdog input high-
+5V low-high or low-high-low. This technique avoids a “stuck”
R1
loop where the watchdog timer continues to be reset
VCC within the loop, keeping the watchdog from timing out.
PFI Figure 16 shows an example flow diagram where the
C1*
I/O driving the watchdog input is set high at the begin-
ning of the program, set low at the beginning of every
R3
MAX807 subroutine or loop, then set high again when the pro-
R2
gram returns to the beginning. If the program should
PFO “hang” in any subroutine, the I/O is continually set low
GND and the watchdog timer is allowed to time out, causing
TO µP a reset or interrupt to be issued.
*OPTIONAL

+5V Maximum VCC Fall Time

The VCC fall time is limited by the propagation delay of
PFO
the battery switchover comparator and should not
0V exceed 0.03V/µs. A standard rule for filter capacitance
0V VL VTRIP VH
VIN
on most regulators is on the order of 100µF per amp of
R1 + R2 current. When the power supply is shut off or the main
VTRIP = 2.265
R2
battery is disconnected, the associated initial V CC fall
R2 || R3 VL - 2.265 + 5 - 2.265 = 2.265 rate is just the inverse or 1A / 100µF = 0.01V/µs. The
VH = 2.265 /
R1 + R2 || R3 R1 R3 R2 VCC fall rate decreases with time as VCC falls exponen-
tially, which more than satisfies the maximum fall-time
Figure 15. Adding Hysteresis to the Power-Fail Comparator requirement.

______________________________________________________________________________________ 15
 Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
__________Typical Operating Circuit ______________Ordering Information
MAX807L/M/N

PART† TEMP. RANGE PIN-PACKAGE

+5V MAX807_CPE 0°C to +70°C 16 Plastic DIP
MAX807_CWE 0°C to +70°C 16 Wide SO
0.1µF 0.1µF
MAX807_EPE -40°C to +85°C 16 Plastic DIP
REAL-
TIME MAX807_EWE -40°C to +85°C 16 Wide SO
VCC BATT OUT
CMOS CLOCK MAX807_MJE -55°C to +125°C 16 CERDIP
BATT ON
RAM
0.47F* † This part offers a choice of reset threshold voltage. From the
CE OUT table below, select the suffix corresponding to the desired
OTHER MR threshold and insert it into the blank to complete the part number.
SYSTEM
RESET ADDRESS
SOURCES CE IN
DECODE RESET THRESHOLD (V)
SUFFIX
PUSH- MAX807 A0–A15 MIN TYP MAX
BUTTON
SWITCH WDI I/O L 4.60 4.675 4.75
µP
LOW LINE NMI N 4.50 4.575 4.65
RESET RESET
M 4.35 4.425 4.50
RESET RESET
+12V BATT OK INTERRUPT
SUPPLY

PFO +12V SUPPLY FAILURE

PFI WDO WATCHDOG FAILURE

GND
*MaxCap™

___________________Chip Information
TRANSISTOR COUNT: 984

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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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