A

PROJECT REPORT

on

The Bank Of SAP

Submitted in partial fulfilment of the requirements for the degree of

BACHELOR OF TECHNOLOGY

Session: - Jan-June 2024

Under Guidance of Submitted by

Aaditya Maheshwari Akshat Audichya (20ETCCS005)
Kanishk Asawara (20ETCCS059)
HOD
8th Semester CSE
Computer science

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

TECHNO INDIA NJR INSTITUTE OF TECHNOLOGY, UDAIPUR-313001

MAY - 2024
CONTENTS
 A

PROJECT REPORT

on

The Bank of SAP

Submitted in partial fulfilment of the requirements for the degree of

BACHELOR OF TECHNOLOGY

Session: - Jan-June 2024

Under Guidance of Submitted by

Aaditya Maheshwari Akshat Audichya (20ETCCS005)
Kansihk Asawara (20ETCCS059)
HOD
8th Semester
Computer Science

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

TECHNO INDIA NJR INSTITUTE OF TECHNOLOGY, UDAIPUR-313001

MAY - 2024
 Department of Computer Science and Engineering
Techno India NJR Institute of Technology, Udaipur-313001

Certificate

This is to certify that project work titled The Bank of SAP by Akshat Audichya was
successfully carried out in the Department of Computer Science and Engineering,
TINJRIT and the report is approved for submission in the partial fulfillment of the
requirements for award of degree of Bachelor of Technology in Computer Science
and Engineering.

<Name of Guide> Aaditya Maheshwari

<Designation> HOD
<Department & Organization> Dept. of CSE TINJRIT, Udaipur
Date...................... Date......................
 Department of Computer Science and Engineering
Techno India NJR Institute of Technology, Udaipur-313001

Examiner Certificate

This is to certify that the following student Akshat Audichya of final year B.Tech.
(Computer Science and Engineering), was examined for the project work titled

The Bank of SAP during the academic year 2023 – 2024 at Techno India NJR
Institute of Technology, Udaipur

Remarks:

Date:

Signature Signature
(Internal Examiner) (External Examiner)
Name :- ……………………… Name :- ………………………
Designation:- ……………….. Designation:- ………………..
Department: - ………………. Department: - ……………….
Organization:- ……………… Organization:- ………………
 Preface

The microstrip patch antenna is one of the simplest radiating structures that can be built
using printed circuits. Single patch antennas and patch antenna arrays are widely used in
communication systems and airborne applications because of their light weight, precise
reproduction through photolithographic techniques, conformal properties, suitability to
integrate with active circuits, and low cost. Although the microstrip patch antenna is not the
best in terms of electrical properties, it is the preferred structure used for radiation in the vast
majority of low-cost applications because of its unique properties.

In Chapter 1, we give an overview of the VLSI physical design automation field. Topics
include the VLSI design cycle, physical design cycle, design styles and packaging styles.
The chapter concludes with a brief historical review of the field.

Chapter 2 discusses the fabrication process for VLSI devices. It is important to understand
the fabrication technology in order to correctly formulate the problems. In addition, it is
important for one to understand, what is doable and what is not! Chapter 2 presents
fundamentals of MOS and TTL transistors. It then describes simple NAND and NOR gates in
nMOS and CMOS.

Chapter 3 presents the status of fabrication process, as well as, process innovations on the
horizons and studies its impact on physical design. We also discuss several other factors
such as design rules, yield, delay, and fabrication costs involved in the VLSI process. Basic
material on data structures and algorithms involved in the physical design is presented in

Chapter 4. Several different data structures for layout

have been discussed. Graphs which are used to model several different problems

in VLSI design are defined and basic.

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

TECHNO INDIA NJR INSTITUTE OF TECHNOLOGY, UDAIPUR-313001
 ACKNOWLEDGMENT

We take this opportunity to record our sincere thanks to all who helped us to successfully
complete this work. Firstly, We are grateful to our supervisor Kutubuddin Bohra for his
invaluable guidance and constant encouragement, support and most importantly for giving
us the opportunity to carry out this work.

We would like to express our deepest sense of gratitude and humble regards to our

Head of Department Dr. Rimpy Bishnoi for giving invariable encouragement in our
endeavors and providing necessary facility for the same. Also a sincere thanks to all faculty
members of CSE, TINJRIT for their help in the project directly or indirectly.

Finally, We would like to thank my friends for their support and discussions that have proved
very valuable for us. We are indebted to our parents for providing constant support, love and
encouragement. We thank them for the sacrifices they made so that we could grow up in a
learning environment. They have always stood by us in everything we have done, providing
constant support, encouragement and love

Akshat Audichya (20ETCCS005)

Kanishk Asawara (20ETCCS005)

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

TECHNO INDIA NJR INSTITUTE OF TECHNOLOGY, UDAIPUR-313001
 CONTENTS

Abstract ………………………………………………………………. i

Contents ………………………………………………………………. ii – iii

List of Figures ……………………………………………………............ iv – v

List of Tables ……………………………………………………………. vi

List of Abbreviations Used………………………………………………. vii – viii

Chapter 1 INTRODUCTION…………………………………………... 1

1.1 Literature Survey ………….……………………………. 2

1.2 Contribution ……………………………………………. 3

1.3 Organization of Dissertation …………………………… 4

1.4 Tools Used ……………………………………………... 4

Chapter 2 HASH FUNCTIONS………………………………………. 5

2.1 Definition And Properties of Hash Functions…………... 5

2.2 Applications of Hash Functions………………………… 7

2.3 Attacks on Hash Functions……………………………… 13

2.4 Hash Computation Flow………………………………… 13

2.4.1 SHA1……………………………………………… 14

2.4.1.1 SHA1 Functions………………………………… 15

2.4.1.2 SHA1 Constants………………………………… 17

2.4.1.3 SHA1 Computation Flow……………….............. 17

2.5 Different Hash Implementations………………………... 20

 LIST OF FIGURES

Fig 2-1 Hashing Operation…………………………………………....... 6

Fig 2-2 Pre-image Resistance………………………………………….. 6

Fig 2-3 Second Pre-image Resistance………………………………….. 7

Fig 2-4 Collision Resistance…………………………………………… 7

Fig 2-5 Verifying Data Integrity……………………………………….. 9

Fig 2-6 Storing The Hash of a Password………………………………. 10

Fig 2-7 Authenticating Users………………………………………....... 11

Fig 2-8 Application of Digital Signature……………………………..... 13

Fig 2-9 Verification of a Digital Signature…………………………… 13

Fig 2-10 General Hash Computation Flow…………………………........ 15

Fig 2-11 Ch Function Architecture……………………………………… 16

Fig 2-12 Parity Function Architecture…………………………………... 16

Fig 2-13 Maj Function Architecture…………………………………….. 17

Fig 2-14 Message Padding………………………………………………. 18

Fig 2-15 SHA-1 Computation Flow…………………………………….. 21

Fig 2-16 General Block Diagram for a Hash Function Implementation... 23

Fig 3-1 FPGA Architecture…………………………………………….. 29

Fig 3-2 HDL Based FPGA design Flow……………………………….. 30

Fig 3-3 Schematic Based FPGA design Flow…………………………. 31

Fig 3-4 Levels of Abstraction………………………………………….. 32

 LIST OF TABLES

Table 2-1 SHA Summary…………………………………………... 15

Table 2-2 SHA- 1 Functions………………………………………... 17

Table 2-3 SHA- 1 Constants………………………………………... 18

Table 2-4 Initial Hash Value for SHA-1……………………………. 19

Table 2-5 Commercial Hash Function Cores………………………. 27

Table 3-1 Comparison of Resources Available in various FPGAs… 33

Table 4-1 Resource Utilization of Initial module for Virtex5……… 37

Table 4-2 Resource Utilization of Round module for Virtex5……... 41

Table 4-3 Resource Utilization of Last Block module for Virtex5… 43

Table 4-4 Resource Utilization of Final module for Virtex5………. 46

Table 4-5 Resource Utilization of Top module for Virtex5………... 49

Device Utilization Summary after Synthesis (Virtex5-

Table 4-6 51
XC5VLX220)……………………………………………..

Table 4-7 Timing Report after Synthesis (Virtex5-XC5VLX220)… 51

 List of Abbreviations/ Symbols

AHC Advanced Hash Calculator

ASCII American Standard Code for Information Interchange

ASIC Application Specific Integrated Circuit

DSA Digital Signature Algorithm

DSS Digital Signature Standard

FIPS Federal Information Processing Standard

FPGA Field Programmable Gate Array

FTP File Transfer Protocol

HDL Hardware Description Language

HMAC Hash Message Authentication Code

IOB Input / Output Block

IP Intellectual Property

JTAG Joint Test Action Group

LED Light Emitting Diode

LUT Look-Up Table

MAC Message Authentication Code

Mbps Mega-bits Per Second

MD5, MD4 Message Digest

MHz Mega Hertz

NCD Native Circuit Description