IE2104 Digital Electronics

Summary & Review

IE2104 Digital Electronics Summary & Review | Prepared by: Lai Fu Jun 1
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Content
7. Latches & Flip Flops
1. Number Systems
2. Digital Circuits 8. Synchronous State
3. Combinational Logic Machine Analysis &
Principles Design
4. Karnaugh Maps 9. Timing &
5. Programmable Logic Synchronisation
Devices
6. Combinational Logic 10. Counters & Shift
Modules Registers
11. Memory

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1. Number Systems

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Definitions

Decimal: 10
Binary: 2
Octal: 8
Hexadecimal: 16 (0-9, A-F)
MSB: Most significant bit (ie the leftmost bit)
LSB: Least significant bit (ie the rightmost bit)

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Changing Bases
𝑟 means radix/base

Lower base to higher base

N=𝑎𝑛−1 ×𝑟𝑛−1 +𝑎𝑛−2 ×𝑟𝑛−2 +⋯+𝑎1 ×𝑟1 +𝑎0 ×𝑟0
Eg. B5E16 = 11 × 162 + 5 × 161 + 14 × 160 = 291010

Higher base to lower base

Divide repeatedly by lower base and write remainders in reverse order
Eg. 1710 = 100012

Special: octal-to-binary (group in 3’s), hexadecimal-to-binary (group in 4’s)

Eg. 3628 = 011 110 0102, 0101 11102 = 5E16

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Signed Numbers
MSB: 0 ~ positive, 1 ~ negative
Sign & magnitude representation
MSB represents sign bit, other bits do not change
2 patterns represent 0 (0000 = +0 and 1000 = −0)

1’s complement representation

Invert every bit; Symmetrical
2 patterns represent 0 (0000 = +0 and 1111 = −0)

2’s complement representation

Invert every bit, then +1 to complement number; Handles sign bit as other bits Only 1 pattern represents
0 (0000)
N = (−1)𝑎𝑛−1 × 2𝑛−1 + 𝑎𝑛−2 × 2𝑛−2 + ⋯ + 𝑎1 × 21 + 𝑎0 × 20
Addition & Subtraction: Any carry beyond the MSB is ignored
Subtraction: (1) – (2) = (1) + Two’s Complement of (2)

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Overflow
For 𝑛-bit binary, the range is:

Unsigned 0 → +(2𝑛 − 1)

Sign & magnitude −(2𝑛−1 − 1) → +(2𝑛−1 − 1)

1’s complement −(2𝑛−1 − 1) → +(2𝑛−1 − 1)

2’s complement −2𝑛−1 → +(2𝑛−1 − 1)

If a result exceeds the range of the number system, overflow is said to occur.
Addition of two numbers of the same sign may result in an overflow.

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Codes
Binary-Coded Decimal (BCD) / 8421 Code Gray Code
Unsigned binary representations; 0000 through 1001; Same as regular binary 0 to 9

2421 Code
2-4-2-1 are the weights from the MSB to LSB
Self complementing (two numbers with a sum of 9 complements each other)

Excess-3
BCD + 3; Self-complementing (two numbers with a sum of 9 complements each other)
Advantage: only 1 bit flips at a time
ASCII code
Use ASCII table for references; 7-bit code 1 character takes up 1 byte in notepad

Miscellaneous
For digits after the decimal point, it will be: 𝛼 × 𝑟−1 + 𝛽 × 𝑟−2 …

Other possible code weights:

1) All decimal values can be represented
2) No repeated representations of the code for

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Different Bit Numbers Arithmetic
For +ve number, add 0’s to the front of the number, eg. 0110 (4 bit) ≡ 000110 (6 bit)
For −ve number, add 1’s to the front of the number, eg. 1010 (4 bit) ≡ 111010 (6 bit)

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2. Digital Circuits

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Binary Logic/Logic Gates

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CMOS Logic
Logic families
A collection of different IC chips that have similar input, output, and internal circuit characteristics
but perform different logic functions.
Eg. transistor transistor logic (TTL), diode logic, CMOS logic

CMOS (Complementary Metal Oxide Semiconductor) logic circuit

Uses complementary arrangements of NMOS & PMOS (if 1 is parallel the other will be series)
MOSFET: Metal Oxide Semiconductor Field-Effect Transistor

CMOS logic levels

Power supply = +5.0V (typically)
0.0 - 1.5 V ⇒ 0
1.5 - 3.5 V ⇒ undefined 3.5 - 5.0 V ⇒ 1

MOS-Switch equivalence
NMOS: 0 (open), 1 (close)
PMOS : 0 (close), 1 (open)

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CMOS Logic Circuits
Fan in
● The number of inputs that a gate can
have in a particular logic family.
● An 𝑛 input gate has 𝑛 series and 𝑛
parallel transistors
● Increasing the number of inputs will
increase the “on” resistance of the
series transistors (limits are typically 4
for NOR gates and 6 for NAND gates).

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CMOS Logic Circuits
CMOS AOI and OAI gates
Can perform two levels of logic with just one level of transistor delay

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CMOS Static Electrical Behaviour
Input / output voltages Typical Values
Typically VCC = 5.0 V ± 10% VCC – 0.1V
VOHmin : The minimum output voltage for the HIGH state 70% of VCC
VIHmin : The minimum input voltage recognized as HIGH 30% of VCC
VILmax : The maximum input voltage recognized as LOW ground + 0.1V
VOLmax : The maximum output voltage for the LOW state

DC noise margin
A measure of how much noise it takes to corrupt a worse case output voltage into a value that may be
recognized properly by an input.
Low state DC noise margin (NML) = VILmax − VOLmax
High state DC noise margin (NMH) = VOHmin − VIHmin
* Note: VOHmin > VIHmin and VOLmax < VILmax to allow for noise to not interfere with logic operations

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CMOS Static Electrical Behaviour
Input / output current
IILmax: The maximum current that flows into the input in LOW state
IIHmax: The maximum current that flows into the input in HIGH state
IOLmax: The maximum current that the output can sink in the LOW state
IOHmax: The maximum current that the output can source in the HIGH state

* Note: Current is positive when flowing into the gate, negative when flowing out

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CMOS Static Electrical Behaviour
Fanout
The number of inputs that the gate can drive without exceeding its worst case loading specifications
(logic level still correct).
* Note: Left is always output (don’t follow sink & source)
High State: fanout = IOHmax / IIHmax; Low State: fanout = IOLmax / IILmax
Fanout = min(fanout-high, fanout-low)
If fanout is exceeded:
• In the LOW state, the output voltage (VOL) may increase beyond VOLmax.
• In the HIGH state, the output voltage (VOH) may fall below VOHmin.
• Propagation delay to the output may increase beyond specifications.
• Output rise and fall times increase beyond their specifications.
• The operating temperature of the device may increase, thereby reducing the reliability.

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CMOS Static Electrical Behaviour
Unused inputs
Unused CMOS inputs should never be left unconnected (or floating, or open) *TTL also
Since CMOS inputs have high impedance, it takes only a small amount of circuit noise to temporarily
make a floating input look HIGH, creating some nasty intermittent circuit failures.

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CMOS Dynamic Electrical Behaviour
Speed and power consumption depends on dynamic electrical behavior

Transition time
The amount of time that the output of a logic circuit takes to change from one state to another.

Propagation delay
The propagation delay, 𝑡𝑝 of a signal path is the amount of time that it takes for a change in the input signal to produce a
change in the output signal.

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CMOS Dynamic Electrical Behaviour
Wired Logic

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CMOS Logic Families
Part number in the form “74FAMnn” (74 is the number for commercial purposes, FAM is an alphabetic
family mnemonic, nn is a numeric function designator; 54 is for military purposes)
Power dissipation, P = CPD × VCC × f where
f = transition frequency of the output signal, CPD = power dissipation capacitance

Bipolar logic families

Bipolar Junction Transistors (BJT) as the basic building blocks of logic circuits.
The simplest bipolar logic elements use diodes and resistors to perform logic operations.
Emitter Coupled Logic (ECL) families use transistors as current switches to achieve very high speed.
Bipolar logic families > TTL
The original Transistor Transistor Logic (TTL) families used transistors both to perform logic functions and
to boost their output drive capability.
Advantage of TTL over CMOS: Not sensitive to electrostatic discharge

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3. Combinational
Logic Principles

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Switching/Boolean Algebra
Positive logic convention → value 0 (LOW), value 1 (HIGH)
Negative logic convention → value 0 (HIGH), value 1 (LOW)

Axioms of switching algebra AND (·) ; OR (+)

(A1) X=0 if X≠1 (A1’) X=1 if X≠0
(A2) If X=0 then X’=1 (A2’) If X=1 then X’=0
(A3) 1+1=1 (A3’) 0·0=0
(A4) 0+0=0 (A4’) 1·1=1
(A5) 1+0=0+1=1 (A5’) 0·1=1·0=0

Switching-algebra theorems / Boolean algebra postulates

(T1) X+0=X (T1’) X·1=X (Identities)
(T2) X+1=1 (T2’) X·0=0 (Null elements)
(T3) X+X=X (T3’) X·X=X (Idempotency)
(T4) (X’)’ = X (Involution)
(T5) X+X’=1 (T5’) X·X’=0 (Complements)
(T6) X+Y=Y+X (T6’) X·Y=Y·X (Commutativity)
(T7) (X+Y)+Z=X+(Y+Z) (T7’) (X·Y)·Z=X·(Y·Z) (Associativity) (Distributivity)
(T8) X·Y+X·Z=X·(Y+Z) (T8’) (X+Y)·(X+Z)=X+Y·Z (Covering)
(T9) X+X·Y=X (T9’) X·(X+Y)=X (Combining)
(T10) X · Y + X · Y’ = X (T10’) (X+Y)·(X+Y’)=X (Consensus)
(T11) X·Y+X’·Z+Y·Z=X·Y+X’·Z (T11’) (X+Y)·(X’+Z)·(Y+Z)=(X+Y)·(X’+Z)

Prove by perfect induction → show that it is true for all possible cases

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Switching/Boolean Algebra
DeMorgan’s theorem “Break the bar & change the sign”
(T12) (X + Y)’ = X’ · Y’ (T12’) (X · Y)’ = X’ + Y

XOR & XNOR

a⊕b=a’b+ab’
(a⊕b)’=a’b+ab’

Operator precedence
Parentheses > NOT > AND > OR

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Boolean Functions
A literal is a variable in a product or sum term
A normal term is a product or sum term in which no variable appears more than once. Eg. w · x · y
Example of non-normal term: w · x · x · y
If function f has 𝑛 variables, each minterm/maxterm must have 𝑛 literals

Minterm / standard product

A product in which each variable appears only once
in either normal or complement form but NOT
BOTH. [sum of products (SOP) of 1’s]
Canonical sum
f1(x,y,z)=m1 +m4 +m6
= Σm(1, 4, 6)
f2(x,y,z)=m2 +m4 +m6 +m7
= Σm(2, 4, 6, 7)

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Boolean Functions
Maxterm / standard sum
A sum in which each variable appears only once in either normal or complement form but NOT
BOTH. [product of sums (POS) of 0’s]
Canonical product
f1(x, y, z) = (f1’)’
= (Σm(0, 2, 3, 5, 7))’
= (x’y’z’ + x’yz’ + x’yz + xy’z + xyz)
= (x + y + z) · (x + y’ + z) · (x + y’ + z’) · (x’ + y + z’) · (x’ + y’ +z’)
=M0 ·M2 ·M3 ·M5 ·M7
= ∏M(0, 2, 3, 5, 7)
f2(x,y,z) = M0 ·M1 ·M3 ·M5
= ∏M(0, 1, 3, 5)
= Σm(2, 4, 6, 7)

* Note: For minterm, m1 = x’y’z [no prime at value];

For maxterm, M1 = x + y + z’ [prime at value]

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Boolean Functions
Conversion to minterms / maxterms
Add terms without changing functionality
Minterm
f(a, b, c) = bc’
= bc’(a + a’) (x + x’ = 1)
= abc’ + a’bc’ (Distribution Law)
= Σm(2, 6)
Maxterm
f(a, b, c) = a’ + bc
= (a’ + b)(a’ + c’) (Distribution Law)
= (a’ + b + cc’)(a’ + c’ + bb’) (xx’ = 0)
= (a’ + b + c)(a’ + b + c’)(a’ + c’ + b)(a’ + c’ + b’) (Distribution Law)
= (a’ + b + c)(a’ + b + c’)(a’ + b’ + c’) (Ignore duplicate factor)
= ∏M(4, 5, 7)

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Boolean Functions
Function and circuit manipulation
Functions can be simplified to their minimum literals
For circuits, it is faster to use NAND and NOR gates (due to CMOS logic) → add inverters

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4. Karnaugh Maps

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 2 Variable K-map

For a two variable function, there are 4 minterms, i.e.,

K-maps can be constructed from Truth Tables
4 squares. Each square has a value 0 or 1.

m0= a’b’(00)
m1 = a’b (01)
m2 = ab’ (10)
m3 = ab (11)

For example, take the function f = a’b + ab’

=> f is true when ab = 01 or 10 NOTE: Each square of the K-map corresponds to
=> f = ⅀m(1,2) 1 row of the truth table

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 3 Variable K-map

Since a 3-variable logic function has 8 minterms Logic Minimization for 3-variable K-map
and a truth table with 8 rows, it has 8 squares

f = m1 + m3 + m4 + m6
= a’b’c + a’bc + ab’c + abc’
= a’c(b’+b) + ac’(b’+b)
= a’c + ac’
The binary sequence of abc follows Gray code
This ensures that adjacent squares have only 1
variable value changed

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 3 Variable K-map for 4 Variable K-map
Logic Simplification
A 4-variable K-map has 16 squares
for ac, notice that a=1
& c=1 & b changes NOTE: The order is in Gray code
from 0 to 1 However, the minterms are NOT in sequence

for a’b’, notice that a=0 & b=0 & c changes from 0 to 1
f = a’b’ + ac

In this case, notice how

only a=1 & both b & c
change from 0 to 1
f=a

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 Terminologies
K-map Covering - A function is said to be covered if all logic -1 squares are grouped. Rules to cover K-map

Implicants - Each group gives a product term and is called an implicant of the 1. Cover all logic 1 squares with min
function. Each implicant is a product term of the function. number of groups

2. Group only even number of

Prime Implicants - A prime implicant is an implicant which cannot be combined with adjacent squares
other implicants. It is the group that covers the maximum number of adjacent
squares. 3. Make groups as large as possible

Essential Prime Implicant - An essential prime implicant is a prime implicant that

covers a minterm which is not covered by other prime implicants.

Minimized Logic Functions - A minimized logic function is a logic function consisting

of ALL essential prime implicants plus other prime implicants that may be needed to
cover any remaining minterms which are not covered by the essential prime
implicants.

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K-Map for Product of Sums 4 Variable K-map
Covering logic-1 squares in K-map gives us logic
functions in sum-of-products form. A 4-variable K-map has 16 squares

We can also cover logic-0 squares, which will give us NOTE: The order is in Gray code
logic functions in product-of-sums form.
However, the minterms are NOT in sequence

f = (a+b’)(b’+c’) f’ = a’b +bc

f = (a+b’)(b’+c’)
We can use both of these methods to obtain the
function in a product-of-sums form

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 K-Map for XOR & XNOR DON’T CARE Conditions
In logic function, sometimes we do not have the
(m1, m7, m2, m4)
XOR specification for all the combinations
=a⨁b⨁c
We do not care about the logic value of the function for
This is an odd function since f=1 if 1 or 3 these undefined combinations
variables are logic 1
We call these combinations DON’T-CARE conditions.
They are usually denoted by ‘x’, or ‘X’ or ‘d’

(m0, m3, m6, m5)

XNOR = (a ⨁ b ⨁ c)’ f(a,b,c)
=⅀m(1,2,5)+ d(4,6)

This is an even function since f=1 if 0 or Note: Don’t care about the
2 variables are logic 1 DON’T-CAREs first

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5. Programmable
Logic Devices

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Programmable Logic Devices (PLDs)
● PLDs consist of AND & OR elements. Both PAL and PLA have 2n programmable
● The interconnections are programmable connections in the AND plane.
● Sum of Products (SOP) of logic functions can
PAL has fixed number of product terms for each
be implemented
OR gate output during the manufacturing and
Three common PLDs:
cannot be changed by the user.
❑ Programmable Array Logic (PAL)
❑ Programmable Logic Array (PLA) PLA has programmable number of product items
❑ Programmable Read Only Memory for each OR gate output
(PROM)
PAL PLA
The basic differences are whether the AND & OR
arrays are FIXED or PROGRAMMABLE

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6. Combinational
Logic Modules

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 Binary Decoder Binary Encoder
Binary Decoder has n inputs and 2^n outputs, and is also They perform the reverse function of a decoder and hence have
2^n inputs and n outputs (2^n-to-n)
called n-to-2^n decoder
They can be built from OR gates.
Inputs have all the 2^n combinations
4-to-2 Encoder means 4 inputs, 2 outputs
Only 1 of the 2^n outputs is activated for each of the
corresponding input combinations

3-to-8 decoder means 3 inputs, 8 outputs

Priority Encoder - Binary encoders have a problem when more

than one input is activated. This device solves that problem by
assigning priority to the inputs

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 Multiplexers (MUX) Demultiplexers (DMUX)
It has many input lines but one output line. It is used to select It reverses the operation of a MUX
the input to go to the output.
It has 1 data input line, n select signals and 2^n data output lines
If 2^n inputs, n select signals are needed 1-to-4 DMUX

We can use Decoders as DMUX

A MUX can also be used as a Function Generator

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Parity Circuits
Parity – even or odd quality of the number of 1’s in a binary code [odd/even parity]
Parity checking application: single error detection
.
Add a parity bit to the original binary code
If the original code has even parity → parity bit =
‘1’; odd parity → parity bit = ‘0’
Hence, the final code will always have odd parity
(error if even)

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Comparator

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Binary Adders
Half adder . Carry-Look-Ahead adder .
• Inputs: a, b From half adder, we define:
• Outputs: s (sum), c (carry) •s=a⊕b, c=ab • Carry propagate, Pi = Ai ⊕ Bi
• Carry generate, Gi = AiBi
Full adder . Fromfulladder:Si =Pi ⊕Ci , Ci+1 =Gi +PiCi
• Inputs: a, b, ci (carry input) Hence, eg. C2 = G1 + P1C1
• Outputs: s (sum), co (carry output) = G1 + P1(G0 + P0C0)
• Can be built from 2 half adders = G1 + P1G0 + P1P0C0
•s=a⊕b⊕c, co =ab+bci +aci =ab+ci(a⊕b)

𝑛-bit ripple adder .

• Addition of 2 𝑛-bit numbers
• Built from 𝑛 full adders
• Ripple adder is simple but slow carries have to propagate through the chain
• To increase speed, we have to reduce the delay on the carry chain

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7. Latches & Flip
Flops

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 Sequential Circuits Clocks
Combinational circuits Specifications
• period (tper)
Output(s) depend only on present value of inputs and not on past
values. • frequency (1 / tper)

Sequential circuits • duty cycle (tH / tper)

Outputs depend on both present and past input values. Device can be triggered by the rising or falling edge of the clock signal

To remember the present state, the sequential circuit must have

some form of ‘memory’

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 Latches
A memory element whose excitation input signals control the state of Feedback circuits with external inputs
the device. Any change to output can only be initiated by the input.
Allow the designer to control the stored value in memory
Simple latches
• Output logic is well defined for inputs 01, 10
Feedback loop: 1 NOT gate
• Input of 11 does not change the initial state of memory
Due to propagation delay, output voltage oscillates
• Input of 00 and changed to 11 will make the output oscillate (we need to
Astable (non stable 0 or 1, signal keeps changing) discard this possibility)

Bi-stable elements

When powered on, outputs of each inverter will go through a period

of instability.

One output settle to a high level & the other to a low level
→No way to predict the output status

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Basic Binary Cells (SR Latches)
Latches have a pair of complementary outputs; an asynchronous
sequential circuit

• SET condition Stores a ‘1’ at Q • REST condition Q state unchanged

• RESET condition Stores a ‘0’ at Q • NOT ALLOWED condition when Q = Q’; unstable

Cross-coupled NOR gate cell Cross-coupled NAND gate cell

Active-high input: 0V (not pushed) means ‘0’ Active-low input: 0V (not pushed) means ‘1’

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Timing Representation of SR Latch

tPLH: delay time between an input change and a corresponding low-to-high

output transition

tPHL: delay time between an input change and a corresponding high-to-low

output transition

* Note: Use a shaded box to represent output unknown values

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Flip-Flop
Has a control signal called a clock which controls the state of the device. Any change to output can only be initiated by the clock.

Characteristic Table: A truth-table for specifying the operational characteristic of the clocked flip-flop

Characteristic equation: Specifies the value of the next state as a function of the present state and the inputs.

Excitation table: Provides the desired inputs to produce a specific output transition.

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 Flip-Flop

The Input Forming Logic (IFL) is a combinational logic

block.

• Decodes the flip-flop inputs, including the clock pulse

and the present state of the basic cell.

• Produces the required asserting output signals, SET or

RESET, in synchrony with the clock, while not asserting
SET and RESET at the same time.

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Flip-Flop
Asynchronous Preset & Clear

• These asynchronous inputs are standard for most integrated circuit, normally added in
order to make the device more flexible. [preset = 0 means set, clear = 0 means reset]
• Completely overrides J and K inputs. •
These inputs are NOT synchronized by the clock signal. When asserted, they affect the
output immediately.
Triggering Schemes of Flip-Flops

• Level triggering: Normally implemented with the use of a simple gating scheme to gate the clock. Can cause the flip-flop to be unstable under
certain input conditions.
• Edge triggering: Normally implemented with a pulse transition detector. Ensures that the output of the flip-flop changes only with a clock edge.
Predominant mode of triggering used in synchronous sequential systems. (only triggered once per clock cycle)
• Pulse triggering: Normally implemented with the use of the master-slave system. Under normal circumstances, this system does cause the output
to change with a clock edge. Can give rise to problems known as “ones catching” and “zeros catching”.

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Flip-Flop Master/Slave JK Flip-Flop

• The whole flip-flop triggers only when a whole clock pulse has occurred (pulse- triggered
device). It guarantees stability against oscillatory state changes due to multiple operations
(race conditions).

• Slave latches onto output logic of master

• When Q = 0, K = 0/1 will have no effect (ie only rest (0, 0) and set (1, 0))

• When Q’ = 0, J = 0/1 will have no effect (ie only rest (0, 0) and reset (0, 1))

• “ones catching” and “zeros catching” -> false triggering due to noise

On the rising-edge of the clock pulse:

1. Master basic cell is loaded in accordance to the input condition of the 1st SET/RESET decoder.
2. Slave basic cell is inhibited due to the inversion clock pulse.
3. The new state (new data) is blocked by the intermediate NAND gates.

On the falling-edge of the clock pulse:

1. Master cell is inhibited.
2. Slave cell is enabled, data stored in the Master cell is passed through the Slave cell and the outputs. Q and Q are updated.
3. The new state is fed back to the input of the 1st SET/ RESET decoder.

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8. Synchronous State
Machine Analysis &
Design

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Mealy Model

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Moore Model

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State Diagrams

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Analysis of Synchronous Sequential Circuits

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Design of Synchronous Sequential Circuits

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9. Timing &
Synchronisation

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Timing in Digital System
Background
Needed to read data from real circuits which might have:
• Different frequencies (eg. Bluetooth, 3G, clock speed, display port speed)
• Dynamic voltage and frequency changing (eg. processor rest vs normal load)

Timing in digital system

All digital devices have associated minimum and maximum propagation delays, 𝑡p or 𝑡d

To avoid metastable behaviour, sequential devices have:

- Setup time, 𝑡su: time required for input data settle in before clock event
- Hold time, 𝑡h : time required for input data to be held steady after clock event

For a typical clocked synchronous FSM (finite-state machine) structure, the time parameters are: 𝑡p(comb) (for combinational logic component) and
𝑡p(ff), 𝑡su, 𝑡h (for flip-flop).

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Timing in Digital System
Setup constraint: 𝑡p(ff1) + 𝑡p(comb) + 𝑡su2 < 𝑇clk 𝑡su marg = 𝑇clk − 𝑡p(ff1) − 𝑡p(comb) − 𝑡su2

Hold constraint : 𝑡h < 𝑡p(ff1) + 𝑡p(comb) 𝑡h marg = 𝑡p(ff1) + 𝑡p(comb) − 𝑡h

Important notes
• Setup/hold time violation occurs when setup/hold margins respectively are < 0
• The range of values for 𝑡p(comb) is taken from combinational logic paths (only from Q and Q’, not inclusive external asychrous inputs)
• Use 𝑡p(comb, max) and 𝑡p(ff, max) for setup constraint (worse case scenario), but 𝑡p(comb, min) and 𝑡p(ff, min) for hold constraint (best case
scenario)

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Clock Skew & Metastability
Clock Skew
• The length of wire will introduce a small delay factor, Δ𝑡, called clock skew
• If clock skew is large enough, then only will it caused data to be misread
• Clock skew cannot be eliminated but can be reduced (eg. add delays)

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Synchronization
Handling asynchronous inputs .
The best way to deal with asynchronous signals is to synchronize them to the clocked system

• Never allow asynchronous inputs to fan-out to more than one flip-flop directly
• Synchronize the asynchronous inputs as soon as possible and then treat as synchronous signal (ie synchronize first then pass through
combinational logic block)
• Do not synchronize at more than one place (may cause different SYNCIN values due to delay factor of ASYNCIN)

Synchronization failure .
• If the asynchronous input to the synchronizer FF changes too close to clock edge, the FF may enter a metastable state. It may stay in this state for
an indefinite amount of time. This is not likely in practice but has some probability.
• Synchronization failure is said to occur if a system uses a synchronizer output while the output is still in metastable state; the only way to recover
is to reset the entire circuit.
• While the probability of synchronizer failure can be made small, it can never be eliminated as long as there are asynchronous inputs
• Two ways to get a flip flop out the metastable state:
- Force the flip flop into a valid logic state using input signals that meet the specifications for minimum pulse width, setup and hold time
- Wait “long enough”, so the flip flop comes out of metastability on its own

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10. Counters & Shift
Registers

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 Synchronous Counter Asynchronous Counter
• Synchronous has only one propagation delay of flip-flop + • Asynchronous is cheaper, has less circuitry (no decoding logic
propagation delay of decoding logic • Clock feeds into the first flip-flop only, however propagation delay of MSB
• All the flip-flops are connected to the clock, and there is decoding gets worse with more flip-flops added (𝑛 × propagation delay of 1 flip-flop)
logic

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Shift Register

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10. Memory

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Read-Only Memory (ROM)
2𝑛 ×𝑏memory → No. of data lines=𝑏; No. of address lines=𝑛 [K=210, M=220, G=230 ...]
•1 byte = 8 bits

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ROM Timing

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Static RAM
• Volatility – most RAMs lose their memory when power is removed [NVRAM = RAM + battery] •
Or use EEPROM (electrically erasable programmable read-only memory) on Arduino

Az

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SRAM Timing

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Dynamic RAM

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DRAM Timing

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Credits
Special thanks to Philip Lee for his notes!

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Thank You

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