XMC Usic

1 /**
2 * @file xmc_usic.h
3 * @date 2015-06-20
4 *
5 * @cond
6
************************************************************************************
*********************************
7 * XMClib v2.0.0 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list
of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the
distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be
used to endorse or promote
22 * products derived from this software without specific prior written
permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share
modifications, enhancements or bug fixes with
33 * Infineon Technologies AG
dave@infineon.com).
34
*************************************************************************************
********************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial draft 
41 * - Documentation improved 
42 *
43 * 2015-05-08:
44 * - Added XMC_USIC_CH_SetInputTriggerCombinationMode() and
XMC_USIC_CH_SetTransmitBufferStatus() 
45 *
46 * 2015-06-20:
47 * - Removed version macros and declaration of GetDriverVersion API
48 *
49 * @endcond
50 *
51 */
52
53 #ifndef XMC_USIC_H
54 #define XMC_USIC_H
55 /*******************************************************************************
56 * HEADER FILES
57 *******************************************************************************/
58
59 #include "xmc_common.h"
60
61 /**
62 * @addtogroup XMClib XMC Peripheral Library
63 * @{
64 */
65
66 /**
67 * @addtogroup USIC
68 * @brief Universal Serial Interface Channel(USIC) driver for serial communication.
69 *
70 * The Universal Serial Interface Channel(USIC) module is a flexible interface module
71 * covering several serial communication protocols. A USIC module contains two
72 * independent communication channels named USICx_CH0 and USICx_CH1, with x
73 * being the number of the USIC module. The user can program, during run-time, which
protocol will be handled
74 * by each communication channel and which pins are used.
75 * The driver provides APIs, configuration structures and enumerations to configure
common features of multiple serial
76 * communication protocols.
77 *
78 * USIC driver features:
79 * -# Allows configuration of FIFO for transmit and receive functions.
80 * -# Provides a structure type XMC_USIC_CH_t to represent the USIC channel registers
in a programmer
81 friendly format.
82 * -# Allows configuration of automatic update for frame length, word length, slave
select or slave address.
83 * -# Allows transmission of data to FIFO using XMC_USIC_CH_TXFIFO_PutData() and
XMC_USIC_CH_TXFIFO_PutDataFLEMode()
84 * -# Allows reading of received data in FIFO using XMC_USIC_CH_RXFIFO_GetData()
85 * -# Allows configuration of baudrate using XMC_USIC_CH_SetBaudrate()
86 * -# Provides API to trigger interrupts using XMC_USIC_CH_TriggerServiceRequest()
87 * @{
88 */
89
90 /*******************************************************************************
91 * MACROS
92 *******************************************************************************/
93
94 #define XMC_USIC0 ((XMC_USIC_t *)USIC0_BASE) /**< USIC0 module base
address */
95 #define XMC_USIC0_CH0 ((XMC_USIC_CH_t *)USIC0_CH0_BASE) /**< USIC0 channel 0 base
address */
address */
97
98 #if defined(USIC1)
address */
address */
address */
102 #endif
103
address */
address */
address */
108 #endif
109
111 /**
112 * Macro checks if the channel is available. It returns \a true if the channel is
available
113 * and returns \a false if the channel is not available.
114 */
115 #define XMC_USIC_CHECK_CH(channel) ((channel == XMC_USIC0_CH0) || \
116 (channel == XMC_USIC0_CH1) || \
120 (channel == XMC_USIC2_CH1) )
121 #elif defined(USIC1)
122 /**
available
125 */
130 #else
131 /**
available
134 */
137 #endif
138
139 #define USIC_CH_DXCR_DSEL_Msk USIC_CH_DX0CR_DSEL_Msk /**< Common mask for DSEL
bitfield mask in DXnCR register */
140 #define USIC_CH_DXCR_DSEL_Pos USIC_CH_DX0CR_DSEL_Pos /**< Common mask for DSEL
bitfield position in DXnCR register */
141 #define USIC_CH_DXCR_SFSEL_Pos USIC_CH_DX0CR_SFSEL_Pos /**< Common mask for SFSEL
142 #define USIC_CH_DXCR_SFSEL_Msk USIC_CH_DX0CR_SFSEL_Msk /**< Common mask for SFSEL
143 #define USIC_CH_DXCR_DPOL_Msk USIC_CH_DX0CR_DPOL_Msk /**< Common mask for DPOL
144 #define USIC_CH_DXCR_DFEN_Msk USIC_CH_DX0CR_DFEN_Msk /**< Common mask for DFEN
145 #define USIC_CH_DXCR_DSEN_Msk USIC_CH_DX0CR_DSEN_Msk /**< Common mask for DSEN
146 #define USIC_CH_DXCR_CM_Pos USIC_CH_DX0CR_CM_Pos /**< Common mask for CM
147 #define USIC_CH_DXCR_CM_Msk USIC_CH_DX0CR_CM_Msk /**< Common mask for CM
148
149 #if UC_FAMILY == XMC1
150 #include "xmc1_usic_map.h"
151 #endif
152
153 #if UC_FAMILY == XMC4
154 #include "xmc4_usic_map.h"
155 #endif
156
157 /*******************************************************************************
158 * ENUMS
159 *******************************************************************************/
160
161 /**
162 * USIC channel driver status
163 */
164 typedef enum XMC_USIC_CH_STATUS
165 {
166 XMC_USIC_CH_STATUS_OK, /**< USIC driver status : OK */
167 XMC_USIC_CH_STATUS_ERROR, /**< USIC driver status : ERROR */
168 XMC_USIC_CH_STATUS_BUSY /**< USIC driver status : BUSY */
169 } XMC_USIC_CH_STATUS_t;
170
171 /**
172 * USIC channel kernel mode
173 */
174 typedef enum XMC_USIC_CH_KERNEL_MODE
175 {
176 XMC_USIC_CH_KERNEL_MODE_RUN_0 = 0x0UL, /**< Run mode 0 (transmission and
reception possible)*/
177 XMC_USIC_CH_KERNEL_MODE_RUN_1 = 0x1UL << USIC_CH_KSCFG_NOMCFG_Pos, /**< Run mode
1 (transmission and reception possible)*/
178 XMC_USIC_CH_KERNEL_MODE_STOP_0 = 0x2UL << USIC_CH_KSCFG_NOMCFG_Pos, /**< Stop mode
0 (no transmission, but reception possible)*/
179 XMC_USIC_CH_KERNEL_MODE_STOP_1 = 0x3UL << USIC_CH_KSCFG_NOMCFG_Pos /**< Stop mode
1 (both transmission and reception not possible)*/
180 } XMC_USIC_CH_KERNEL_MODE_t;
181
182 /**
183 * USIC channel operating mode
184 */
185 typedef enum XMC_USIC_CH_OPERATING_MODE
186 {
187 XMC_USIC_CH_OPERATING_MODE_IDLE = 0x0UL, /**< USIC channel idle */
188 XMC_USIC_CH_OPERATING_MODE_SPI = 0x1UL << USIC_CH_CCR_MODE_Pos, /**< SPI mode */
189 XMC_USIC_CH_OPERATING_MODE_UART = 0x2UL << USIC_CH_CCR_MODE_Pos, /**< UART mode */
190 XMC_USIC_CH_OPERATING_MODE_I2S = 0x3UL << USIC_CH_CCR_MODE_Pos, /**< I2S mode */
191 XMC_USIC_CH_OPERATING_MODE_I2C = 0x4UL << USIC_CH_CCR_MODE_Pos /**< I2C mode */
192 } XMC_USIC_CH_OPERATING_MODE_t;
193
194 /**
195 * USIC channel inputs
196 */
197 typedef enum XMC_USIC_CH_INPUT
198 {
199 XMC_USIC_CH_INPUT_DX0, /**< DX0 input */
204 XMC_USIC_CH_INPUT_DX5 /**< DX5 input */
205 } XMC_USIC_CH_INPUT_t;
206
207 /**
208 * USIC channel input source sampling frequency
209 */
210 typedef enum XMC_USIC_CH_INPUT_SAMPLING_FREQ
211 {
212 XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH = 0x0UL, /**< Use fperiph
frequency for input source sampling*/
213 XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = 0x1UL << USIC_CH_DXCR_SFSEL_Pos
/**< Use fFD(fractional divider) frequency for input source sampling*/
214 } XMC_USIC_CH_INPUT_SAMPLING_FREQ_t;
215
216 /**
217 * USIC channel input combination mode
218 */
219 typedef enum XMC_USIC_CH_INPUT_COMBINATION_MODE
220 {
221 XMC_USIC_CH_INPUT_COMBINATION_MODE_TRIGGER_DISABLED = 0x0UL, /**< The trigger
activation is disabled.*/
222 XMC_USIC_CH_INPUT_COMBINATION_MODE_RISING_EDGE = 0x1UL, /**< A rising edge
activates DXnT*/
223 XMC_USIC_CH_INPUT_COMBINATION_MODE_FALLING_EDGE = 0x2UL, /**< A falling edge
activates DXnT*/
224 XMC_USIC_CH_INPUT_COMBINATION_MODE_BOTH_EDGES = 0x3UL, /**< Both edges
activate DXnT*/
225 } XMC_USIC_CH_INPUT_COMBINATION_MODE_t;
226
227 /**
228 * USIC channel data transmission start modes.
229 * Data shifted out of the transmit pin depends on the value configured for the
230 * TDEN bitfield of the TCSR register. Following enum values are used for configuring
231 * the TCSR->TDEN bitfield.
232 */
233 typedef enum XMC_USIC_CH_START_TRANSMISION_MODE
234 {
235 XMC_USIC_CH_START_TRANSMISION_DISABLED = 0x0U, /**< Passive data level is sent
out on transmission. */
236 XMC_USIC_CH_START_TRANSMISION_ON_TDV = 0x1UL << USIC_CH_TCSR_TDEN_Pos, /**<
Transmission of the data word in TBUF can be started if TDV = 1 */
237 XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0 = 0x2UL << USIC_CH_TCSR_TDEN_Pos, /**<
Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_0 */
238 XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1 = 0x3UL << USIC_CH_TCSR_TDEN_Pos /**<
Transmission of the data word in TBUF can be started if TDV = 1 while DX2S_1 */
239 } XMC_USIC_CH_START_TRANSMISION_MODE_t;
240
241 /**
242 * USIC channel interrupt node pointers
243 */
244 typedef enum XMC_USIC_CH_INTERRUPT_NODE_POINTER
245 {
246 XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = USIC_CH_INPR_TSINP_Pos,
/**< Node pointer for transmit shift interrupt */
247 XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = USIC_CH_INPR_TBINP_Pos,
/**< Node pointer for transmit buffer interrupt */
248 XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE = USIC_CH_INPR_RINP_Pos,
/**< Node pointer for receive interrupt */
249 XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = USIC_CH_INPR_AINP_Pos,
/**< Node pointer for alternate receive interrupt */
250 XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL = USIC_CH_INPR_PINP_Pos
/**< Node pointer for protocol related interrupts */
251 } XMC_USIC_CH_INTERRUPT_NODE_POINTER_t;
252
253 /**
254 * USIC channel events
255 */
256 typedef enum XMC_USIC_CH_EVENT
257 {
258 XMC_USIC_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start
event */
259 XMC_USIC_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event
*/
260 XMC_USIC_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift
event */
261 XMC_USIC_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer
event */
262 XMC_USIC_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
263 XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate
receive event */
264 XMC_USIC_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk /**< Baudrate
generator event */
265 } XMC_USIC_CH_EVENT_t;
266
267 /**
268 * USIC channel parity mode
269 */
270 typedef enum XMC_USIC_CH_PARITY_MODE
271 {
272 XMC_USIC_CH_PARITY_MODE_NONE = 0x0UL, /**< Disable parity mode */
273 XMC_USIC_CH_PARITY_MODE_EVEN = 0x2UL << USIC_CH_CCR_PM_Pos, /**< Enable even
parity mode */
274 XMC_USIC_CH_PARITY_MODE_ODD = 0x3UL << USIC_CH_CCR_PM_Pos /**< Enable odd
parity mode */
275 } XMC_USIC_CH_PARITY_MODE_t;
276
277 /**
278 * USIC channel data output mode
279 */
280 typedef enum XMC_USIC_CH_DATA_OUTPUT_MODE
281 {
282 XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL = 0x0UL, /**< Data output normal mode */
283 XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED = 0x1UL << USIC_CH_SCTR_DOCFG_Pos /**< Data
output inverted mode */
284 } XMC_USIC_CH_DATA_OUTPUT_MODE_t;
285
286 /**
287 * USIC channel data transmit buffer status
288 */
289 typedef enum XMC_USIC_CH_TBUF_STATUS
290 {
291 XMC_USIC_CH_TBUF_STATUS_IDLE = 0x0UL, /**< Transfer buffer is
currently idle*/
292 XMC_USIC_CH_TBUF_STATUS_BUSY = USIC_CH_TCSR_TDV_Msk /**< Transfer buffer is
currently busy*/
293 } XMC_USIC_CH_TBUF_STATUS_t;
294
295
296
297 /**
298 * USIC channel data transmit buffer status modification
299 */
300 typedef enum XMC_USIC_CH_TBUF_STATUS_SET
301 {
302 XMC_USIC_CH_TBUF_STATUS_SET_BUSY = 0x1UL, /**< Set Transfer buffer status to
busy*/
303 XMC_USIC_CH_TBUF_STATUS_SET_IDLE = 0x2UL /**< Set Transfer buffer status to
idle*/
304 } XMC_USIC_CH_TBUF_STATUS_SET_t;
305
306 /**
307 * USIC channel receive buffer status
308 */
309 typedef enum XMC_USIC_CH_RBUF_STATUS
310 {
311 XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 = USIC_CH_RBUFSR_RDV0_Msk, /**< RBUF0 data has
not yet been read out*/
312 XMC_USIC_CH_RBUF_STATUS_DATA_VALID1 = USIC_CH_RBUFSR_RDV1_Msk /**< RBUF1 data has
not yet been read out*/
313 } XMC_USIC_CH_RBUF_STATUS_t;
314
315 /**
316 * USIC channel output signal passive data level
317 */
318 typedef enum XMC_USCI_CH_PASSIVE_DATA_LEVEL
319 {
320 XMC_USIC_CH_PASSIVE_DATA_LEVEL0 = 0x0UL, /**< Passive level(idle mode signal level)
0 */
321 XMC_USIC_CH_PASSIVE_DATA_LEVEL1 = 0x1UL << USIC_CH_SCTR_PDL_Pos /**< Passive
level(idle mode signal level) 1 */
322 } XMC_USIC_CH_PASSIVE_DATA_LEVEL_t;
323
324 /**
325 * USIC channel receive FIFO size
326 */
327 typedef enum XMC_USIC_CH_FIFO_SIZE
328 {
329 XMC_USIC_CH_FIFO_DISABLED = 0x0U, /**< FIFO Disabled */
330 XMC_USIC_CH_FIFO_SIZE_2WORDS = 0x1U, /**< FIFO size: 2 words */
335 XMC_USIC_CH_FIFO_SIZE_64WORDS = 0x6U /**< FIFO size: 64 words */
336 } XMC_USIC_CH_FIFO_SIZE_t;
337
338 /**
339 * USIC channel transmit FIFO interrupt node pointers
340 */
341 typedef enum XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER
342 {
343 XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD = USIC_CH_TBCTR_STBINP_Pos,
/**< Node pointer for FIFO standard transmit interrupt */
344 XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE = USIC_CH_TBCTR_ATBINP_Pos
/**< Node pointer for transmit FIFO error interrupt */
345 } XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t;
346
347 /**
348 * USIC channel transmit FIFO event configuration
349 */
350 typedef enum XMC_USIC_CH_TXFIFO_EVENT_CONF
351 {
352 XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD = USIC_CH_TBCTR_STBIEN_Msk, /**< Enable
FIFO standard transmit interrupt */
353 XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR = (int32_t)USIC_CH_TBCTR_TBERIEN_Msk /**<
Enable transmit FIFO error interrupt */
354 } XMC_USIC_CH_TXFIFO_EVENT_CONF_t;
355
356 /**
357 * USIC channel transmit FIFO status
358 */
359 typedef enum XMC_USIC_CH_TXFIFO_EVENT
360 {
361 XMC_USIC_CH_TXFIFO_EVENT_STANDARD = USIC_CH_TRBSR_STBI_Msk, /**< Transmit FIFO
status: Standard event */
362 XMC_USIC_CH_TXFIFO_EVENT_ERROR = USIC_CH_TRBSR_TBERI_Msk /**< Transmit FIFO
status: Error event */
363 } XMC_USIC_CH_TXFIFO_EVENT_t;
364
365 /**
366 * USIC channel receive FIFO interrupt node pointers
367 */
368 typedef enum XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER
369 {
370 XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD = USIC_CH_RBCTR_SRBINP_Pos, /**<
Node pointer for FIFO standard receive interrupt */
371 XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE = USIC_CH_RBCTR_ARBINP_Pos /**<
Node pointer for FIFO alternative receive interrupt */
372 } XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t;
373
374 /**
375 * USIC channel receive FIFO event configuration
376 */
377 typedef enum XMC_USIC_CH_RXFIFO_EVENT_CONF
378 {
379 XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD = USIC_CH_RBCTR_SRBIEN_Msk, /**< Enable
FIFO standard receive interrupt */
380 XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR = (int32_t)USIC_CH_RBCTR_RBERIEN_Msk, /**<
Enable receive FIFO error interrupt */
381 XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE = USIC_CH_RBCTR_ARBIEN_Msk /**< Enable
FIFO alternative receive interrupt */
382 } XMC_USIC_CH_RXFIFO_EVENT_CONF_t;
383
384 /**
385 * USIC channel receive FIFO status
386 */
387 typedef enum XMC_USIC_CH_RXFIFO_EVENT
388 {
389 XMC_USIC_CH_RXFIFO_EVENT_STANDARD = USIC_CH_TRBSR_SRBI_Msk, /**< Receive FIFO
status: Standard event */
390 XMC_USIC_CH_RXFIFO_EVENT_ERROR = USIC_CH_TRBSR_RBERI_Msk, /**< Receive FIFO
status: Error event */
391 XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE = USIC_CH_TRBSR_ARBI_Msk /**< Receive FIFO
status: Alternative event */
392 } XMC_USIC_CH_RXFIFO_EVENT_t;
393
394 /**
395 * USIC channel baudrate generator clock source
396 */
397 typedef enum XMC_USIC_CH_BRG_CLOCK_SOURCE
398 {
399 XMC_USIC_CH_BRG_CLOCK_SOURCE_DIVIDER = 0x0UL, /**< Baudrate generator clock source
: Source divider. (Internal clock source)*/
400 XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T = 0x1UL << USIC_CH_BRG_CLKSEL_Pos /**<
Baudrate generator clock source : DX1T. (External clock source) */
401 } XMC_USIC_CH_BRG_CLOCK_SOURCE_t;
402
403 /**
404 * USIC channel baudrate generator divider mode
405 */
406 typedef enum XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE
407 {
408 XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_DISABLED = 0x0UL, /**< Baudrate generator
clock divider: Disabled */
409 XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL = 0x1UL << USIC_CH_FDR_DM_Pos, /**<
Baudrate generator clock divider: Normal mode */
410 XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL = 0x2UL << USIC_CH_FDR_DM_Pos /**<
Baudrate generator clock divider: Fractional mode */
411 } XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t;
412
413 /**
414 * USIC channel baudrate generator master clock passive level
415 */
416 typedef enum XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL
417 {
418 XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0 = 0x0UL, /**< Baudrate generator
master clock passive level(idle mode signal level) 0*/
419 XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1 = 0x1UL << USIC_CH_BRG_MCLKCFG_Pos
/**< Baudrate generator master clock passive level((idle mode signal level)) 1*/
420 } XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t;
421
422 /**
423 * USIC channel baudrate generator shift clock passive level
424 */
425 typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL
426 {
427 XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED = 0x0UL, /**< Shift
clock passive level 0, delay disabled */
428 XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED = 0x1UL <<
USIC_CH_BRG_SCLKCFG_Pos, /**< Shift clock passive level 1, delay disabled */
429 XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED = (int32_t)(0x2UL <<
USIC_CH_BRG_SCLKCFG_Pos), /**< Shift clock passive level 0, delay enabled */
430 XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED = (int32_t)(0x3UL <<
USIC_CH_BRG_SCLKCFG_Pos) /**< Shift clock passive level 1, delay enabled */
431 } XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t;
432
433 /**
434 * USIC channel baudrate generator shift clock output
435 */
436 typedef enum XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT
437 {
438 XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = 0x0UL, /**< Baudrate generator shift
clock output: SCL.(Internally generated shift clock)*/
439 XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = 0x1UL << USIC_CH_BRG_SCLKOSEL_Pos /**<
Baudrate generator shift clock output: DX1. (External input shift clock)*/
440 } XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t;
441
442 /*******************************************************************************
443 * DATA STRUCTURES
444 *******************************************************************************/
445
446 /*Anonymous structure/union guard start*/
447 #if defined(__CC_ARM)
448 #pragma push
449 #pragma anon_unions
450 #elif defined(__TASKING__)
451 #pragma warning 586
452 #endif
453
454 /**
455 * USIC module structure
456 */
457 typedef USIC_GLOBAL_TypeDef XMC_USIC_t;
458
459 /**
460 * USIC channel structure. The members of the structure are same as in the device
header file,
461 * except for some registers.
462 * DX0CR, DX1CR, DX2CR, DX3CR, DX4CR and DX5CR are replaced with the array DXCR[6].
463 * TBUF0 to TBUF31 are replaced with TBUF[32].
464 * IN0 to IN31 are replaced with IN[32].
465 */
466 typedef struct XMC_USIC_CH
467 {
468 __I uint32_t RESERVED0;
469 __I uint32_t CCFG; /**< Channel configuration register*/
470 __I uint32_t RESERVED1;
471 __IO uint32_t KSCFG; /**< Kernel state configuration register*/
472 __IO uint32_t FDR; /**< Fractional divider configuration register*/
473 __IO uint32_t BRG; /**< Baud rate generator register*/
474 __IO uint32_t INPR; /**< Interrupt node pointer register*/
475 __IO uint32_t DXCR[6]; /**< Input control registers DX0 to DX5.*/
476 __IO uint32_t SCTR; /**< Shift control register*/
477 __IO uint32_t TCSR;
478
479 union {
480 __IO uint32_t PCR_IICMode; /**< I2C protocol configuration register*/
481 __IO uint32_t PCR_IISMode; /**< I2S protocol configuration register*/
482 __IO uint32_t PCR_SSCMode; /**< SPI protocol configuration register*/
483 __IO uint32_t PCR; /**< Protocol configuration register*/
484 __IO uint32_t PCR_ASCMode; /**< UART protocol configuration register*/
485 };
486 __IO uint32_t CCR; /**< Channel control register*/
487 __IO uint32_t CMTR; /**< Capture mode timer register*/
488
489 union {
490 __IO uint32_t PSR_IICMode; /**< I2C protocol status register*/
491 __IO uint32_t PSR_IISMode; /**< I2S protocol status register*/
492 __IO uint32_t PSR_SSCMode; /**< SPI protocol status register*/
493 __IO uint32_t PSR; /**< Protocol status register*/
494 __IO uint32_t PSR_ASCMode; /**< UART protocol status register*/
495 };
496 __O uint32_t PSCR; /**< Protocol status clear register*/
497 __I uint32_t RBUFSR; /**< Receive buffer status register*/
498 __I uint32_t RBUF; /**< Receive buffer register*/
499 __I uint32_t RBUFD; /**< Debug mode receive buffer register*/
500 __I uint32_t RBUF0; /**< Receive buffer 0*/
501 __I uint32_t RBUF1; /**< Receive buffer 1*/
502 __I uint32_t RBUF01SR; /**< Receive buffer status register*/
503 __O uint32_t FMR; /**< Flag modification register*/
504 __I uint32_t RESERVED2[5];
505 __IO uint32_t TBUF[32]; /**< Tranmsit buffer registers*/
506 __IO uint32_t BYP; /**< FIFO bypass register*/
507 __IO uint32_t BYPCR; /**< FIFO bypass control register*/
508 __IO uint32_t TBCTR; /**< Transmit FIFO control register*/
509 __IO uint32_t RBCTR; /**< Receive FIFO control register*/
510 __I uint32_t TRBPTR; /**< Transmit/recive buffer pointer register*/
511 __IO uint32_t TRBSR; /**< Transmit/receive buffer status register*/
512 __O uint32_t TRBSCR; /**< Transmit/receive buffer status clear register*/
513 __I uint32_t OUTR; /**< Receive FIFO output register*/
514 __I uint32_t OUTDR; /**< Receive FIFO debug output register*/
515 __I uint32_t RESERVED3[23];
516 __O uint32_t IN[32]; /**< Transmit FIFO input register*/
517 } XMC_USIC_CH_t;
518
519
520 /*Anonymous structure/union guard end*/
521 #if defined(__CC_ARM)
522 #pragma pop
523 #elif defined(__TASKING__)
524 #pragma warning restore
525 #endif
526
527 /*******************************************************************************
528 * API PROTOTYPES
529 ******************************************************************************/
530
531 #ifdef __cplusplus
532 extern "C" {
533 #endif
534
535 /* Common APIs */
536
537 /**
538 * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n
539 * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support.
540 * @return None
541 *
542 * \parDescription 
543 * Enables the USIC module.\n\n
544 * Enables the clock for the USIC module by following the
545 * clock enabling sequence for the selected device.
546 *
547 * \parRelated APIs: 
548 * XMC_USIC_CH_Enable(), XMC_USIC_Disable() \n\n\n
549 */
550 void XMC_USIC_Enable(XMC_USIC_t *const usic);
551 /**
552 * @param usic Pointer to USIC module handler of type @ref XMC_USIC_t.\n
553 * \b Range: @ref XMC_USIC0 to @ref XMC_USIC2 based on device support.
554 * @return None
555 *
557 * Disables the USIC module.\n\n
558 * Disables the clock for the USIC module by following the clock
559 * disabling sequence for the selected device.
560 *
562 * XMC_USIC_CH_Disable(), XMC_USIC_Enable() \n\n\n
563 */
564 void XMC_USIC_Disable(XMC_USIC_t *const usic);
565 /**
566 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
567 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
568 * @return None
569 *
571 * Enables the USIC channel. \n\n
572 * USIC channel is enabled by setting the module enable bit in KSCFG register
bitfield MODEN.
573 * On enabling, the channel is set to idle mode.
574 *
576 * XMC_USIC_CH_Disable(), XMC_USIC_Enable() \n\n\n
577 */
578 void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel);
579 /**
582 * @return None
583 *
585 * Disables the USIC channel.\n\n
586 * USIC channel is disabled by setting the module enable bit(MDEN) to 0 in the
register KSCFG.
587 *
589 * XMC_USIC_CH_Enable(), XMC_USIC_Disable() \n\n\n
590 */
591 void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel);
592 /**
595 * @param rate Desired baudrate. \b Range: minimum value = 100, maximum value
depends on the peripheral clock frequency \n
596 * and \a oversampling. Maximum baudrate can be derived using the
formula: (fperiph * 1023)/(1024 * oversampling)
597 * @param oversampling Required oversampling. The value indicates the number of time
quanta for one symbol of data. \n
598 * This can be related to the number of samples for each logic
state of the data signal. \n
599 * \b Range: 1 to 32. Value should be chosen based on the
protocol used.
600 * @return Status indicating the baudrate configuration.\n
601 * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully
configured,
602 * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or
oversampling is invalid.
603 *
605 * Configures the baudrate of the USIC channel. \n\n
606 * Baudrate is configured by considering the peripheral frequency and the desired
baudrate.
607 * Optimum values of FDR->STEP and BRG->PDIV are calulated and used for generating
the desired
608 * baudrate.
609 *
611 * XMC_USIC_CH_SetStartTransmisionMode(), XMC_USIC_CH_SetInputSource() \n\n\n
612 */
613 XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t
rate, uint32_t oversampling);
614
615 /**
618 * @param input USIC channel input stage of type @ref XMC_USIC_CH_INPUT_t. \n
619 * \b Range: @ref XMC_USIC_CH_INPUT_DX0 to @ref XMC_USIC_CH_INPUT_DX5
620 * @param source Input source select for the input stage. The table below maps the
enum value with the input channel.
621 * <table><tr><td>0</td><td>DXnA</td></tr><tr><td>1</td><td>DXnB</td></tr><tr><td>2</
td><td>DXnC</td></tr><tr><td>3</td><td>DXnD</td></tr>
622 * <tr><td>4</td><td>DXnE</td></tr><tr><td>5</td><td>DXnF</td></tr><tr><td>6</td><td
>DXnG</td></tr><tr><td>7</td><td>Always 1</td>
623 * </tr></table>
624 * @return None
625 *
627 * Selects the data source for USIC input stage.\n\n
628 * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage.
The API can be used for all the input stages
629 * like DX0CR, DX1CR etc.
630 *
632 * XMC_USIC_CH_EnableInputInversion(), XMC_USIC_CH_EnableInputDigitalFilter(),
XMC_USIC_CH_EnableInputSync(),
633 * XMC_USIC_CH_SetInputSamplingFreq()\n\n\n
634 */
635 __STATIC_INLINE void XMC_USIC_CH_SetInputSource(XMC_USIC_CH_t *const channel, const
XMC_USIC_CH_INPUT_t input, const uint8_t source)
636 {
637 channel->DXCR[input] = (uint32_t)((channel->DXCR[input] & (uint32_t)(~
USIC_CH_DXCR_DSEL_Msk)) |
638 ((uint32_t)source << USIC_CH_DXCR_DSEL_Pos));
639 }
640 /**
645 * @return None
646 *
648 * Enables input inversion for USIC channel input data signal. \n\n
649 *
650 * Polarity of the input source can be changed to provide inverted data input.
652 * XMC_USIC_CH_DisableInputInversion()\n\n\n
653 */
654 __STATIC_INLINE void XMC_USIC_CH_EnableInputInversion(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_INPUT_t input)
655 {
656 channel->DXCR[input] |= USIC_CH_DXCR_DPOL_Msk;
657 }
658
659 /**
664 * @return None
665 *
667 * Disables input inversion for USIC channel. \n\n
668 *
669 * Resets the input data polarity for the USIC channel input data signal.
671 * XMC_USIC_CH_EnableInputInversion()\n\n\n
672 */
673
674 __STATIC_INLINE void XMC_USIC_CH_DisableInputInversion(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_INPUT_t input)
675 {
676 channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DPOL_Msk;
677 }
678 /**
683 * @return None
684 *
686 * Enables the input digital filter for USIC channel input data signal. \n\n
687 * Input data signal from the selected multiplexer will be digitally filtered.
688 *
690 * XMC_USIC_CH_DisableInputDigitalFilter()\n\n\n
691 */
692 __STATIC_INLINE void XMC_USIC_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel
, const XMC_USIC_CH_INPUT_t input)
693 {
694 channel->DXCR[input] |= (uint32_t)USIC_CH_DXCR_DFEN_Msk;
695 }
696 /**
701 * @return None
702 *
704 * Disables the input digital filter for USIC channel input data signal. \n\n
705 * Input data signal from the selected multiplexer will not be digitally filtered.
706 *
708 * XMC_USIC_CH_EnableInputDigitalFilter()\n\n\n
709 */
710 __STATIC_INLINE void XMC_USIC_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const
channel, const XMC_USIC_CH_INPUT_t input)
711 {
712 channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DFEN_Msk;
713 }
714 /**
719 * @return None
720 *
722 * Enables input synchronization for the USIC channel input data signal. \n\n
723 * Input data signal from the selected multiplexer will be synchronized with fPERIPH.
724 * A noisy signal can be synchronized and filtered by enabling the digital filter.
725 *
727 * XMC_USIC_CH_DisableInputSync(), XMC_USIC_CH_EnableInputDigitalFilter()\n\n\n
728 */
729 __STATIC_INLINE void XMC_USIC_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const
XMC_USIC_CH_INPUT_t input)
730 {
731 channel->DXCR[input] |=(uint32_t)USIC_CH_DXCR_DSEN_Msk;
732 }
733 /**
738 * @return None
739 *
741 * Disables input synchronization for the USIC channel input data signal. \n\n
742 * Input data signal from the selected multiplexer will not be synchronized.
743 *
745 * XMC_USIC_CH_EnableInputSync(), XMC_USIC_CH_DisableInputDigitalFilter() \n\n\n
746 */
747 __STATIC_INLINE void XMC_USIC_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const
XMC_USIC_CH_INPUT_t input)
748 {
749 channel->DXCR[input] &=(uint32_t)~USIC_CH_DXCR_DSEN_Msk;
750 }
751 /**
XMC_USIC2_CH1 based on device support..
756 * @param sampling_freq Sampling frequency value of type \a
XMC_USIC_CH_INPUT_SAMPLING_FREQ_t.
757 * @return None
758 *
760 * Sets sampling frequency for USIC channel input data signal. \n\n
761 *
763 * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(),
XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n
764 */
765 __STATIC_INLINE void XMC_USIC_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel,
766 const XMC_USIC_CH_INPUT_t input,
767 const
XMC_USIC_CH_INPUT_SAMPLING_FREQ_
t sampling_freq)
768 {
769 channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_SFSEL_Msk))
|
770 ((uint32_t)sampling_freq);
771 }
772
773 /**
XMC_USIC2_CH1 based on device support..
778 * @param combination_mode Combination mode value of type \a
XMC_USIC_CH_INPUT_COMBINATION_MODE_t.
779 * @return None
780 *
782 * Selects which edge of the synchronized signal DXnS activates the trigger output
DXnT of the input stage. \n\n
783 *
785 * XMC_USIC_CH_SetInputSource(), XMC_USIC_CH_EnableInputSync(),
XMC_USIC_CH_EnableInputDigitalFilter() \n\n\n
786 */
787 __STATIC_INLINE void XMC_USIC_CH_SetInputTriggerCombinationMode(XMC_USIC_CH_t *const
channel,
788 const
XMC_USIC_CH_INPUT_t
input,
789 const
XMC_USIC_CH_INPUT_COMB
INATION_MODE_t
combination_mode)
790 {
791 channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DXCR_CM_Msk)) |
792 ((uint32_t)combination_mode << USIC_CH_DXCR_CM_Pos);
793 }
794 /**
797 * @param word_length Number of bits to be configured for a data word. \n
798 * \b Range: minimum= 1, maximum= 16. \n
799 * e.g: For word length of 8, \a word_length should be provided
as 8.
800 * @return None
801 *
803 * Sets the data word length in number of bits. \n\n
804 * Sets the number of bits to represent a data word. Frame length should be a
multiple of word length.
805 *
807 * XMC_USIC_CH_SetFrameLength()\n\n\n
808 */
809 __STATIC_INLINE void XMC_USIC_CH_SetWordLength(XMC_USIC_CH_t *const channel, const
uint8_t word_length)
810 {
811 channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_WLE_Msk)) |
812 (uint32_t)(((uint32_t)word_length - 1UL) << USIC_CH_SCTR_WLE_Pos);
813 }
814
815 /**
818 * @param frame_length Number of bits in a frame. \n
819 * \b Range: minimum= 1, maximum= 0x3f. The maximum value for
fixed frame size is 0x3f. \n
820 * e.g: For a frame length of 16, \a frame_length should be
provided as 16.
821 * @return None
822 *
824 * Define the data frame length.\n\n
825 * Set the number of bits to be serially transmitted in a frame.
826 * The frame length should be multiples of word length. If the value is set to 0x40,
the frame length
827 * has to be controlled explicitly.
828 *
830 * XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl() \n\n\n
831 */
832 __STATIC_INLINE void XMC_USIC_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const
uint8_t frame_length)
833 {
834 channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_FLE_Msk)) |
835 (((uint32_t)frame_length - 0x1U) << USIC_CH_SCTR_FLE_Pos);
836 }
837
838 /**
841 * @param event Bit mask of the channel events to be enabled. Use @ref
XMC_USIC_CH_EVENT_t for the bit masks. \n
842 * \b Range: @ref XMC_USIC_CH_EVENT_RECEIVE_START, @ref
XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events
843 * can be combined using \a OR operation.
844 * @return None
845 *
847 * Enable the channel interrupt events.\n\n
848 * Common channel events related to serial communication can be configured using this
API.
849 * Multiple events can be combined using the bitwise OR operation and configured in
one function call.
850 * XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These
enumerations can be used as input to the API.
851 *
853 * XMC_USIC_CH_DisableEvent(), XMC_USIC_CH_SetInterruptNodePointer() \n\n\n
854 */
855 __STATIC_INLINE void XMC_USIC_CH_EnableEvent(XMC_USIC_CH_t *const channel, const
uint32_t event)
856 {
857 channel->CCR |= event;
858 }
859
860 /**
863 * @param event Bit mask of the channel events to be disabled. Use @ref
XMC_USIC_CH_EVENT_t for the bit masks. \n
864 * \b Range: @ref XMC_USIC_CH_EVENT_RECEIVE_START, @ref
XMC_USIC_CH_EVENT_DATA_LOST etc. Multiple events
865 * can be combined using \a OR operation.
866 * @return None
867 *
869 * Disable the channel interrupt events. \n\n
870 * Multiple events can be combined using the bitwise OR operation and configured in
one function call.
871 * XMC_USIC_CH_EVENT_t enumerates multiple protocol event bitmasks. These
enumerations can be used as input to the API.
872 *
874 * XMC_USIC_CH_EnableEvent(), XMC_USIC_CH_SetInterruptNodePointer() \n\n\n
875 */
876 __STATIC_INLINE void XMC_USIC_CH_DisableEvent(XMC_USIC_CH_t *const channel, const
uint32_t event)
877 {
878 channel->CCR &= (uint32_t)~event;
879 }
880
881 /**
884 * @param interrupt_node Interrupt node pointer to be configured. \n
885 * \b Range: @ref
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
886 * @ref
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
887 * @param service_request Service request number.\n
888 * \b Range: 0 to 5.
889 * @return None
890 *
892 * Sets the interrupt node for USIC channel events. \n\n
893 * For an event to generate interrupt, node pointer should be configured with service
request(SR0, SR1..SR5).
894 * The NVIC node gets linked to the interrupt event by doing so. 
895 * Note: NVIC node should be separately enabled to generate the interrupt.
896 *
898 * XMC_USIC_CH_EnableEvent() \n\n\n
899 */
900 void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
901 const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t
interrupt_node,
902 const uint32_t service_request);
903
904 /**
907 * @return Stataus @ref XMC_USIC_CH_TBUF_STATUS_IDLE if transmit buffer is free,
908 * @ref XMC_USIC_CH_TBUF_STATUS_BUSY if transmit buffer is busy.
909 *
911 * Gets transmit buffer status. \n\n
912 * Status indicates whether the transmit buffer is free, or busy transmitting data.
913 * The status depends on the value of TDV flag in TCSR register.
914 * This status can be used while transmitting data. Transmit data when the transmit
buffer
915 * status is @ref XMC_USIC_CH_TBUF_STATUS_IDLE.
916 *
918 * XMC_USIC_CH_SetDataOutputMode() \n\n\n
919 */
920 __STATIC_INLINE XMC_USIC_CH_TBUF_STATUS_t XMC_USIC_CH_GetTransmitBufferStatus(
XMC_USIC_CH_t *const channel)
921 {
922 return (XMC_USIC_CH_TBUF_STATUS_t)(channel->TCSR & USIC_CH_TCSR_TDV_Msk);
923 }
924
925 /**
926 * @brief API to get receive buffer status
929 * @return Status of data validity check for RBUF0 and RBUF1. \n
930 * Returned value should be masked with RDV0 and RDV1 bits to know the
status. \n
931 * \b Range: @ref XMC_USIC_CH_RBUF_STATUS_DATA_VALID0, @ref
XMC_USIC_CH_RBUF_STATUS_DATA_VALID1.
932 *
934 * Checks if RBUF0 and RBUF1 have valid unread data. \n\n
935 * It checks the bits RDV0 and RDV1 of the RBUFSR register.
936 * Returns the value of RBUFSR masked with bitmasks of RDV0 and RDV1.
937 * It can be used to decide whether 2bytes has to be read from RBUF or 1 byte.
938 * If both bitmasks XMC_USIC_CH_RBUF_STATUS_DATA_VALID0 and
XMC_USIC_CH_RBUF_STATUS_DATA_VALID1
939 * are set, then 2 bytes can be read from RBUF. If only either of them is set, then
only one byte
940 * can be read from RBUF.
942 * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n
943 */
944 __STATIC_INLINE uint32_t XMC_USIC_CH_GetReceiveBufferStatus(XMC_USIC_CH_t *const
channel)
945 {
946 return ((uint32_t) (channel->RBUFSR & (USIC_CH_RBUFSR_RDV0_Msk |
USIC_CH_RBUFSR_RDV1_Msk)));
947 }
948
949
950 /**
953 * @param start_transmision_mode Transmission mode to be enabled. \n
954 * \b Range: @ref XMC_USIC_CH_START_TRANSMISION_DISABLED,
955 * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV, @ref
XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0,
956 * @ref XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1
957 *
958 * @return None
959 *
961 * Configures data transmission. \n\n
962 * The configuration affects the data shifted on the DOUT0 pin.
963 *
965 * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetDataOutputMode() \n\n\n
966 */
967 __STATIC_INLINE void XMC_USIC_CH_SetStartTransmisionMode(XMC_USIC_CH_t *const channel,
968 const
XMC_USIC_CH_START_TRANSMISION
_MODE_t
start_transmision_mode)
969 {
970 channel->TCSR = (uint32_t)(channel->TCSR & (~USIC_CH_TCSR_TDEN_Msk)) | (uint32_t)
start_transmision_mode;
971 }
972
973
974 /**
977 * @param data_output_mode Data output mode. \n
978 * \b Range: @ref XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL, @ref
XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED
979 * @return None
980 *
982 * Configures the mode for data output. \n\n
983 * USIC channel can be configured to shift inverted data or direct data based on the
input to the API.
984 *
986 * XMC_USIC_CH_SetStartTransmisionMode() \n\n\n
987 */
988 __STATIC_INLINE void XMC_USIC_CH_SetDataOutputMode(XMC_USIC_CH_t *const channel,
989 const
XMC_USIC_CH_DATA_OUTPUT_MODE_t
data_output_mode)
990 {
991 channel->SCTR = (uint32_t)(channel->SCTR & (~USIC_CH_SCTR_DOCFG_Msk)) | (uint32_t)
data_output_mode;
992 }
993
994 /**
997 * @return None
998 *
1000 * Enables automatic update of frame length. \n\n
1001 * When the automatic update of frame length is enabled, frame length is configured
based on the
1002 * index of the TBUF[]/IN[] register array. When the data is written to TBUF[x],
frame length is configured
1003 * with the mask value of \a x at the last 5 bit positions. Same logic is applicable
if data is written to
1004 * IN[x] register.
1005 *
1007 * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_TXFIFO_PutDataFLEMode() \n\n\n
1008 */
1009 __STATIC_INLINE void XMC_USIC_CH_EnableFrameLengthControl(XMC_USIC_CH_t *const channel
)
1010 {
1011 channel->TCSR = (uint32_t)(channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk |
1012 USIC_CH_TCSR_SELMD_Msk |
1013 USIC_CH_TCSR_WAMD_Msk |
1014 USIC_CH_TCSR_HPCMD_Msk))) |
1015 (uint32_t)USIC_CH_TCSR_FLEMD_Msk;
1016 }
1017
1018 /**
1021 * @return None
1022 *
1024 * Disables automatic update of frame length. \n\n
1025 * When automatic update of frame length is disabled, frame length has to configured
explicitly.
1026 * Frame length remains fixed until it is changed again.
1027 *
1029 * XMC_USIC_CH_DisableFrameLengthControl(), XMC_USIC_CH_SetFrameLength() \n\n\n
1030 */
1031 __STATIC_INLINE void XMC_USIC_CH_DisableFrameLengthControl(XMC_USIC_CH_t *const
channel)
1032 {
1033 channel->TCSR &= (uint32_t)~USIC_CH_TCSR_FLEMD_Msk;
1034 }
1035
1036 /**
1039 * @param service_request_line service request number of the event to be triggered.
\n
1040 * \b Range: 0 to 5.
1041 * @return None
1042 *
1044 * Trigger a USIC interrupt service request.\n\n
1045 * When the USIC service request is triggered, the NVIC interrupt associated with it
will be
1046 * generated if enabled.
1047 *
1049 * XMC_USIC_CH_SetInterruptNodePointer() \n\n\n
1050 */
1051 __STATIC_INLINE void XMC_USIC_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel,
const uint32_t service_request_line)
1052 {
1053 channel->FMR |= (uint32_t)(USIC_CH_FMR_SIO0_Msk << service_request_line);
1054 }
1055
1056
1057 /**
1060 * @param transmit_buffer_status clearing or setting the TDV flag. \n
1061 *
1062 * @return None
1063 *
1065 * Modify TCSR.TDV and TCSR.TE to control the start of a data word transmission by
software.
1066 *
1068 * XMC_USIC_CH_GetTransmitBufferStatus() \n\n\n
1069 */
1070 __STATIC_INLINE void XMC_USIC_CH_SetTransmitBufferStatus(XMC_USIC_CH_t *const channel,
1071 const
XMC_USIC_CH_TBUF_STATUS_SET_t
transmit_buffer_status)
1072 {
1073 channel->FMR |= (uint32_t)transmit_buffer_status;
1074 }
1075
1076 /**
1079 * @param passive_level Value of passive level for the channel. \n
1080 * \b Range: @ref XMC_USIC_CH_PASSIVE_DATA_LEVEL0, @ref
XMC_USIC_CH_PASSIVE_DATA_LEVEL1
1081 * @return None
1082 *
1084 * Set the passive data level of the output signal. \n\n
1085 * When the USIC channel transmit stage is idle, the output signal level stays at the
1086 * configured passive level.
1087 *
1089 * XMC_USIC_CH_GetTransmitBufferStatus(), XMC_USIC_CH_SetStartTransmisionMode() \n\n\n
1090 */
1091 __STATIC_INLINE void XMC_USIC_CH_SetPassiveDataLevel(XMC_USIC_CH_t *const channel,
1092 const
XMC_USIC_CH_PASSIVE_DATA_LEVEL_t
passive_level)
1093 {
1094 channel->SCTR &= (~USIC_CH_SCTR_PDL_Msk);
1095 channel->SCTR |= (uint32_t)passive_level;
1096 }
1097
1098 /* TX FIFO APIs */
1099 /**
1102 * @param data_pointer Start position inside the FIFO buffer. \n
1103 * \b Range: 0 to 63.
1104 * @param size Required size of the transmit FIFO. \n
1105 * \b Range: @ref XMC_USIC_CH_FIFO_DISABLED, @ref XMC_USIC_CH_FIFO_SIZE_2WORDS..
@ref XMC_USIC_CH_FIFO_SIZE_64WORDS
1106 * @param limit Threshold of transmit FIFO filling level to be considered for
generating events. \n
1107 * \b Range: 0 to \a size -1.
1108 * @return None
1109 *
1111 * Initializes the transmit FIFO. \n\n
1112 * Transmit FIFO is a subset of a common FIFO sized 64 words. This FIFO is shared
between 2 channels of the USIC module.
1113 * Each channel can share the FIFO for transmission and reception. \a data_pointer
represents the start index in the common FIFO,
1114 * from where transmit data can be put, for the selected USIC channel. \a size
represents the size of transmit FIFO as a multiple of
1115 * 2. Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully
selected. A FIFO standard transmit buffer
1116 * event is generated when the FIFO filling level falls below the \a limit value.
1117 *
1119 * XMC_USIC_CH_TXFIFO_EnableEvent(), XMC_USIC_CH_TXFIFO_SetInterruptNodePointer()
\n\n\n
1120 */
1121 void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel,
1122 const uint32_t data_pointer,
1123 const XMC_USIC_CH_FIFO_SIZE_t size,
1124 const uint32_t limit);
1125
1126 /**
1129 * @param size Required size of the transmit FIFO. \n
1131 * @param limit Threshold for transmit FIFO filling level to be considered for
1132 * \b Range: 0 to \a size -1.
1133 * @return None
1134 *
1136 * Sets the size and trigger limit for the transmit FIFO. \n\n
1137 * The API is not to be called for initializing the transmit FIFO. The API shall be
used for the
1138 * runtime change of transmit FIFO trigger limit. FIFO start position will not be
affected on execution.
1139 *
1141 * XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit() \n\n\n
1142 */
1143 void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
1146
1147
1148 /**
1151 * @param event Events to be enabled. Multiple events can be bitwise OR combined. \n
1152 * \b Range: @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD, @ref
XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR.
1153 * @return None
1154 *
1156 * Enables the interrupt events related to transmit FIFO. \n\n
1157 * Event bitmasks can be constructed using the enumeration @ref
XMC_USIC_CH_TXFIFO_EVENT_CONF.
1158 * Multiple events can be enabled by providing multiple events in a single call. For
providing
1159 * multiple events, combine the events using bitwise OR operation. Events are
configured in the TBCTR register. 
1160 *
1161 * Note: API only enables the events. For interrupt generation, interrupt node must
be configured and NVIC node
1162 * must be enabled.
1163 *
1165 * XMC_USIC_CH_TXFIFO_SetInterruptNodePointer() \n\n\n
1166 */
1167 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_EnableEvent(XMC_USIC_CH_t *const channel,
const uint32_t event)
1168 {
1169 channel->TBCTR |= event;
1170 }
1171
1172
1173 /**
1176 * @param event Events to be disabled. \n
1177 * \b Range: @ref XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD, @ref
XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR.
1178 * @return None
1179 *
1181 * Disables the interrupt events related to transmit FIFO. \n\n
1182 * By disabling the interrupt events, generation of interrupt is stopped. User can
poll the event
1183 * flags from the status register using the API XMC_USIC_CH_TXFIFO_GetEvent().
XMC_USIC_CH_TXFIFO_EVENT_CONF. For providing
1185 * multiple events, combine the events using bitwise OR operation.
1186 *
1188 * XMC_USIC_CH_TXFIFO_GetEvent(), XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n
1189 */
1190 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_DisableEvent(XMC_USIC_CH_t *const channel,
1191 {
1192 channel->TBCTR &= (uint32_t)~event;
1193 }
1194
1195 /**
1198 * @param interrupt_node Node pointer representing the transmit FIFO events. \n
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD,
1200 * @ref
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
1201 * @param service_request The service request to be used for interrupt generation. \n
1202 * \b Range: 0 to 5.
1203 * @return None
1204 *
1206 * Sets an interrupt node for the transmit FIFO events.\n\n
1207 * A node pointer represents one or more interrupt events. Service request represents
the interrupt node to be used
1208 * among the 6 interrupt nodes available for USIC module.
1209 * API configures the service request to be used for interrupt generation for the
events selected.
1210 * A transmit FIFO event can generate an interrupt only if the interrupt node is
configured for the event and
1211 * the interrupt generation is enabled for the event. For example, transmit FIFO
standard transmit buffer
1212 * interrupt is generated if the interrupt node for the same is set and interrupt is
enabled. 
1213 *
1214 * Note: NVIC node should be explicitly enabled for the interrupt generation.
1215 *
1217 * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n
1218 */
1219 void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
1220 const
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POIN
TER_t interrupt_node,
1222
1223 /**
1226 * @param data Data to be transmitted. \n
1227 * \b Range: 16bit unsigned data. minimum= 0, maximum= 65535
1228 * @return None
1229 *
1231 * Writes data into the transmit FIFO. \n\n
1232 * The data provided is placed in the transmit FIFO.
1233 * The transmit FIFO should be configured before calling this API.
1234 *
1236 * XMC_USIC_CH_TXFIFO_EnableEvent() \n\n\n
1237 */
1238 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutData(XMC_USIC_CH_t *const channel, const
uint16_t data)
1239 {
1240 channel->IN[0] = data;
1241 }
1242
1243 /**
1246 * @param data Data to be transmitted.
1247 * @param frame_length Frame length to be configured while transmitting the data. \n
1248 * \b Range: minimum= 0, maximum= 31. e.g: For a frame length of 16, set \a
frame_length as 15.
1249 * @return None
1250 *
1252 * Writes data to the transmit FIFO in frame length control mode. \n\n
1253 * When frame length control is enabled for dynamic update of frame length, this API
can be used.
1254 * \a frame_length represents the frame length to be updated by the peripheral.
1255 * \a frame_length is used as index for the IN[] register array.
1256 *
1258 * XMC_USIC_CH_EnableFrameLengthControl() \n\n\n
1259 */
1260 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_PutDataFLEMode(XMC_USIC_CH_t *const channel,
1261 const uint16_t data,
1262 const uint32_t frame_length)
1263 {
1264 channel->IN[frame_length] = data;
1265 }
1266
1267 /**
1270 * @return None
1271 *
1273 * Clears the contents of transmit FIFO. \n\n
1274 * Transmit FIFO contents will be cleared and the filling level will be reset to 0.
1275 *
1277 * XMC_USIC_CH_TXFIFO_GetLevel() \n\n\n
1278 */
1279 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_Flush(XMC_USIC_CH_t *const channel)
1280 {
1281 channel->TRBSCR |= (uint32_t)USIC_CH_TRBSCR_FLUSHTB_Msk;
1282 }
1283
1284 /**
1287 * @return Status \a true if transmit FIFO is full
1288 * \a false if transmit FIFO is not full.
1289 *
1291 * Checks if transmit FIFO is full. \n\n
1292 * When the transmit FIFO filling level reaches the configured size, FIFO full flag
is set.
1293 * User should not write to the FIFO when the transmit FIFO is full.
1294 *
1296 * XMC_USIC_CH_TXFIFO_IsEmpty(), XMC_USIC_CH_TXFIFO_Flush() \n\n\n
1297 */
1298 __STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsFull(XMC_USIC_CH_t *const channel)
1299 {
1300 return (bool)(channel->TRBSR & USIC_CH_TRBSR_TFULL_Msk);
1301 }
1302
1303 /**
1306 * @return Status \a true if transmit FIFO is empty
1307 * \a false if transmit FIFO has some data.
1308 *
1310 * Checks if transmit FIFO is empty. \n\n
1311 * When the transmit FIFO is empty, data can be written to FIFO.
1312 * When the last written word to the transmit FIFO is transmitted out of the FIFO,
1313 * FIFO empty flag is set.
1314 *
1316 * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n
1317 */
1318 __STATIC_INLINE bool XMC_USIC_CH_TXFIFO_IsEmpty(XMC_USIC_CH_t *const channel)
1319 {
1320 return (bool)(channel->TRBSR & USIC_CH_TRBSR_TEMPTY_Msk);
1321 }
1322
1323 /**
1326 * @return Transmit FIFO filling level. \n
1327 * \b Range: minimum= 0(FIFO empty), maximum= transmit FIFO size.
1328 *
1330 * Gets the transmit FIFO filling level. \n\n
1331 * For every word written to the FIFO, filling level is updated. The API gives the
value
1332 * of this filling level.
1333 *
1335 * XMC_USIC_CH_TXFIFO_Flush(), XMC_USIC_CH_TXFIFO_PutData() \n\n\n
1336 */
1337 __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetLevel(XMC_USIC_CH_t *const channel)
1338 {
1339 return ((uint32_t)(channel->TRBSR & USIC_CH_TRBSR_TBFLVL_Msk) >>
USIC_CH_TRBSR_TBFLVL_Pos);
1340 }
1341
1342 /**
1345 * @return Status of standard transmit and transmit buffer error events. \n
1346 * \b Range: @ref XMC_USIC_CH_TXFIFO_EVENT_STANDARD, @ref
XMC_USIC_CH_TXFIFO_EVENT_ERROR.
1347 *
1349 * Gets the transmit FIFO event status. \n\n
1350 * Gives the status of transmit FIFO standard transmit buffer event and transmit
buffer error event.
1351 * The status bits are located at their bit positions in the TRBSR register in the
returned value.
1352 * User can make use of the @ref XMC_USIC_CH_TXFIFO_EVENT enumeration for checking
the status of return value.
1353 * The status can be found by using the bitwise AND operation on the returned value
with the enumerated value. 
1354 *
1355 * Note: Event status flags should be cleared by the user explicitly.
1356 *
1358 * XMC_USIC_CH_TXFIFO_ClearEvent() \n\n\n
1359 */
1360 __STATIC_INLINE uint32_t XMC_USIC_CH_TXFIFO_GetEvent(XMC_USIC_CH_t *const channel)
1361 {
1362 return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_STBI_Msk |
1363 USIC_CH_TRBSR_TBERI_Msk));
1364 }
1365
1366 /**
1369 * @param event Transmit FIFO events to be cleared. \n
1370 * \b Range: @ref XMC_USIC_CH_TXFIFO_EVENT_STANDARD, @ref
XMC_USIC_CH_TXFIFO_EVENT_ERROR.
1371 * @return None
1372 *
1374 * Clears the transmit FIFO event flags in the status register. \n\n
1375 * USIC channel peripheral does not clear the event flags after they are read.
1376 * This API clears the events provided in the \a mask value.
1377 * XMC_USIC_CH_TXFIFO_EVENT enumeration can be used as input. Multiple events
1378 * can be cleared by providing a mask value obtained by bitwise OR operation of
1379 * multiple event enumerations.
1380 *
1382 * XMC_USIC_CH_TXFIFO_GetEvent() \n\n\n
1383 */
1384 __STATIC_INLINE void XMC_USIC_CH_TXFIFO_ClearEvent(XMC_USIC_CH_t *const channel,
1385 const uint32_t event)
1386 {
1387 channel->TRBSCR |= event;
1388 }
1389
1390 /**
1393 * @param data_pointer Start position inside the FIFO buffer. \n
1394 * \b Range: 0 to 63.
1395 * @param size Required size of the receive FIFO. \n
1397 * @param limit Threshold of receive FIFO filling level to be considered for
1398 * \b Range: 0 to \a size -1.
1399 * @return None
1400 *
1402 * Configures the receive FIFO. \n\n
1403 * Receive FIFO is the subset of a common FIFO sized 64 words. This FIFO is shared
between 2 channels of the USIC module.
1404 * Each channel can share the FIFO for transmission and reception. \a data_pointer
represents the start index in the common FIFO,
1405 * from where received data can be put. \a size represents the size of receive FIFO
as a multiple of 2.
1406 * Since the FIFO is shared between 2 USIC channels, FIFO size should be carefully
selected. A FIFO standard receive buffer
1407 * event or alternative receive buffer event is generated when the FIFO filling level
exceeds the \a limit value.
1408 *
1410 * XMC_USIC_CH_RXFIFO_EnableEvent(), XMC_USIC_CH_RXFIFO_SetInterruptNodePointer()
\n\n\n
1411 */
1412 void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel,
1413 const uint32_t data_pointer,
1416
1417 /**
1420 * @param size Required size of the receive FIFO. \n
1422 * @param limit Threshold for receive FIFO filling level to be considered for
1423 * \b Range: 0 to \a size -1.
1424 * @return None
1425 *
1427 * Sets the size and trigger limit for the receive FIFO. \n\n
1428 * The API is not to be called for initializing the receive FIFO. The API shall be
used for the
1429 * runtime change of receive FIFO trigger limit. FIFO start position will not be
affected on execution.
1430 *
1432 * XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit()\ n\n\n
1433 */
1434 void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
1437
1438 /**
1441 * @param event Events to be enabled. Multiple events can be bitwise OR combined. \n
1442 * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD, @ref
XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR,
1443 * @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE.
1444 * @return None
1445 *
1447 * Enables the interrupt events related to transmit FIFO. \n\n
XMC_USIC_CH_RXFIFO_EVENT_CONF.
1449 * Multiple events can be enabled by providing multiple events in a single call. For
providing
1450 * multiple events, combine the events using bitwise OR operation. 
1451 *
1452 * Note: API only enables the events. For interrupt generation, interrupt node must
be configured and NVIC node
1453 * must be enabled.
1454 *
1456 * XMC_USIC_CH_RXFIFO_SetInterruptNodePointer() \n\n\n
1457 */
1458 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_EnableEvent(XMC_USIC_CH_t *const channel,
1459 {
1460 channel->RBCTR |= event;
1461 }
1462
1463
1464 /**
1467 * @param event Events to be disabled. \n
1468 * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD, @ref
XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR,
1469 * @ref XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE.
1470 * @return None
1471 *
1473 * Disables the selected interrupt events related to receive FIFO. \n\n
1474 * By disabling the interrupt events, generation of interrupt is stopped. User can
poll the event
1475 * flags from the status register using the API XMC_USIC_CH_RXFIFO_GetEvent().
1476 * Event bitmasks can be constructed using the enumeration \a
XMC_USIC_CH_RXFIFO_EVENT_CONF. For providing
1477 * multiple events, combine the events using bitwise OR operation.
1478 *
1480 * XMC_USIC_CH_RXFIFO_GetEvent(), XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n
1481 */
1482 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_DisableEvent(XMC_USIC_CH_t *const channel,
1483 {
1484 channel->RBCTR &= (uint32_t)~event;
1485 }
1486
1487 /**
1490 * @param interrupt_node Node pointer representing the receive FIFO events. \n
1491 * \b Range: @ref XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD,
1492 * @ref XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
1493 * @param service_request The service request to be used for interrupt generation.\n
1494 * \b Range: 0 to 5.
1495 * @return None
1496 *
1498 * Sets an interrupt node for the receive FIFO events. \n\n
1499 * A node pointer represents one or more interrupt events. Service request represents
the interrupt node to be used
1500 * among the 6 interrupt nodes available for USIC module.
1501 * API configures the service request to be used for interrupt generation for the
events selected.
1502 * A receive FIFO event can generate an interrupt only if the interrupt node is
configured for the event and
1503 * the interrupt generation is enabled for the event. For example, transmit FIFO
standard transmit buffer
1504 * interrupt is generated if the interrupt node for the same is set and interrupt is
enabled. 
1505 *
1506 * Note: NVIC node should be explicitly enabled for the interrupt generation.
1507 *
1509 * XMC_USIC_CH_RXFIFO_EnableEvent() \n\n\n
1510 */
1511 void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
1512 const
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POIN
TER_t interrupt_node,
1514
1515 /**
1518 * @return Value read from the receive FIFO. \n
1519 * \b Range: 16bit data. Length of data depends on the word length
configuration.
1520 *
1522 * Gets data from the receive FIFO. \n\n
1523 * Receive FIFO should be read only if data is availble in the FIFO. This can be
checked using
1524 * the API XMC_USIC_CH_RXFIFO_IsEmpty(). Receive FIFO error flag will be set if an
attempt is made
1525 * to read from an empty receive FIFO. To read all the received data, user should
keep reading data
1526 * until receive FIFO is empty.
1527 *
1529 * XMC_USIC_CH_RXFIFO_ClearEvent() \n\n\n
1530 */
1531 __STATIC_INLINE uint16_t XMC_USIC_CH_RXFIFO_GetData(XMC_USIC_CH_t *const channel)
1532 {
1533 return (uint16_t)(channel->OUTR);
1534 }
1535
1536 /**
1539 * @return None
1540 *
1542 * Clears the contents of receive FIFO. \n\n
1543 * Receive FIFO contents will be cleared and the filling level will be reset to 0.
1544 *
1546 * XMC_USIC_CH_RXFIFO_GetLevel() \n\n\n
1547 */
1548 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_Flush(XMC_USIC_CH_t *const channel)
1549 {
1550 channel->TRBSCR |= (uint32_t)USIC_CH_TRBSCR_FLUSHRB_Msk;
1551 }
1552
1553 /**
1556 * @return Status \a true if receive FIFO is full
1557 * \a false if receive FIFO is not full.
1558 *
1560 * Checks if receive FIFO is full. \n\n
1561 * When the receive FIFO filling level reaches the configured size, FIFO full flag is
set.
1562 * Any data received when the receive FIFO is full, is lost.
1563 *
1565 * XMC_USIC_CH_RXFIFO_IsEmpty(), XMC_USIC_CH_RXFIFO_Flush() \n\n\n
1566 */
1567 __STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsFull(XMC_USIC_CH_t *const channel)
1568 {
1569 return (bool)(channel->TRBSR & USIC_CH_TRBSR_RFULL_Msk);
1570 }
1571
1572 /**
1575 * @return Status \a true if receive FIFO is empty,
1576 * \a false if receive FIFO has some data.
1577 *
1579 * Checks if receive FIFO is empty. \n\n
1580 * When the receive FIFO is empty, received data will be put in receive FIFO.
1581 * When the last received word in the FIFO is read, FIFO empty flag is set. Any
attempt
1582 * to read from an empty receive FIFO will set the receive FIFO error flag.
1583 *
1585 * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n
1586 */
1587 __STATIC_INLINE bool XMC_USIC_CH_RXFIFO_IsEmpty(XMC_USIC_CH_t *const channel)
1588 {
1589 return (bool)(channel->TRBSR & USIC_CH_TRBSR_REMPTY_Msk);
1590 }
1591
1592 /**
1595 * @return uint32_t Receive FIFO filling level. \n
1596 * \b Range: minimum= 0(FIFO empty), maximum= receive FIFO size.
1597 *
1599 * Gets the receive FIFO filling level. \n\n
1600 * For every word received, the filling level is incremented. The API gives the value
1601 * of this filling level. The filling level is decremented when the data is read out
of the
1602 * receive FIFO.
1603 *
1605 * XMC_USIC_CH_RXFIFO_Flush(), XMC_USIC_CH_RXFIFO_PutData() \n\n\n
1606 */
1607 __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetLevel(XMC_USIC_CH_t *const channel)
1608 {
1609 return ((uint32_t)(channel->TRBSR & USIC_CH_TRBSR_RBFLVL_Msk) >>
USIC_CH_TRBSR_RBFLVL_Pos);
1610 }
1611
1612 /**
1615 * @return Status of standard receive buffer, alternative receive buffer and receive
buffer error events. \n
1616 * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref
XMC_USIC_CH_RXFIFO_EVENT_ERROR,
1617 * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE.
1618 *
1620 * Gets the receive FIFO events' status. \n\n
1621 * Gives the status of receive FIFO standard receive buffer event, alternative
receive buffer event and receive buffer error event.
1622 * The status bits are located at their bitpositions in the TRBSR register in the
returned value.
1623 * User can make use of the XMC_USIC_CH_RXFIFO_EVENT enumeration for checking the
status of return value.
1624 * The status can be found by using the bitwise AND operation on the returned value
with the enumerated value. 
1625 *
1626 * Note: Event status flags should be cleared by the user explicitly.
1627 *
1629 * XMC_USIC_CH_RXFIFO_ClearEvent()\n\n\n
1630 */
1631 __STATIC_INLINE uint32_t XMC_USIC_CH_RXFIFO_GetEvent(XMC_USIC_CH_t *const channel)
1632 {
1633 return (uint32_t)((channel->TRBSR) & (USIC_CH_TRBSR_SRBI_Msk |
1634 USIC_CH_TRBSR_RBERI_Msk |
1635 USIC_CH_TRBSR_ARBI_Msk));
1636 }
1637
1638 /**
1641 * @param event Receive FIFO events to be cleared. \n
1642 * \b Range: @ref XMC_USIC_CH_RXFIFO_EVENT_STANDARD, @ref
XMC_USIC_CH_RXFIFO_EVENT_ERROR,
1643 * @ref XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE.
1644 * @return None
1645 *
1647 * Clears the receive FIFO event flags in the status register. \n\n
1648 * USIC channel peripheral does not clear the event flags after they are read.
1649 * This API clears the events provided in the \a mask value.
1650 * XMC_USIC_CH_RXFIFO_EVENT enumeration can be used as input. Multiple events
1651 * can be cleared by providing a mask value obtained by bitwise OR operation of
1652 * multiple event enumerations.
1653 *
1655 * XMC_USIC_CH_RXFIFO_GetEvent() \n\n\n
1656 */
1657 __STATIC_INLINE void XMC_USIC_CH_RXFIFO_ClearEvent(XMC_USIC_CH_t *const channel,
1658 const uint32_t event)
1659 {
1660 channel->TRBSCR |= event;
1661 }
1662
1663 /**
1666 * @return None
1667 *
1669 * Enables time measurement using the capture mode timer. \n\n
1670 * Time measurement is enabled by setting the timer enable flag in BRG register.
1671 *
1673 * XMC_USIC_CH_DisableTimeMeasurement() \n\n\n
1674 */
1675 __STATIC_INLINE void XMC_USIC_CH_EnableTimeMeasurement(XMC_USIC_CH_t *const channel)
1676 {
1677 channel->BRG |= (uint32_t)USIC_CH_BRG_TMEN_Msk;
1678 }
1679
1680 /**
1683 * @return None
1684 *
1686 * Disables time measurement using the capture mode timer. \n\n
1687 * Time measurement is disabled by clearing the timer enable flag in BRG register.
1688 *
1690 * XMC_USIC_CH_EnableTimeMeasurement() \n\n\n
1691 */
1692 __STATIC_INLINE void XMC_USIC_CH_DisableTimeMeasurement(XMC_USIC_CH_t *const channel)
1693 {
1694 channel->BRG &= (uint32_t)~USIC_CH_BRG_TMEN_Msk;
1695 }
1696
1697 /**
1700 * @param passive_level Passive level for the master clock output. \n
1701 * \b Range: @ref XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0, @ref
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1.
1702 * @return None
1703 *
1705 * Sets the idle mode pin level for the master clock output. \n
1706 */
1707 __STATIC_INLINE void XMC_USIC_CH_SetMclkOutputPassiveLevel(XMC_USIC_CH_t *const
channel,
1708 const
XMC_USIC_CH_BRG_MASTER_CLOC
K_PASSIVE_LEVEL_t
passive_level)
1709 {
1710 channel->BRG = (uint32_t)(channel->BRG & (~USIC_CH_BRG_MCLKCFG_Msk)) | (uint32_t)
passive_level;
1711 }
1712 /**
1715 * @param passive_level Passive level for the clock output. \n
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED,
1717 * @ref
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED,
1718 * @ref
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED,
1719 * @ref
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED,
1720 * @param clock_output Shift clock source selection. \n
1721 * \b Range: Use @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK,
1722 * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
1723 * @return None
1724 *
1726 * Sets the idle mode shift clock output level and selects the shift clock source.
\n\n
1727 * Shift clock idle mode output level can be set to logic high or low. Shift clock
output can be configured to have a
1728 * delay of half shift clock period. Both the configurations are available as
enumeration values defined with type
1729 * @ref XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL.
1730 * This value should be configured based on the slave device requirement.
1731 * Shift clock source can be selected between internal clock(master) and external
input(slave).
1732 *
1733 */
1734 __STATIC_INLINE void XMC_USIC_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const
channel,
1735 const
XMC_USIC_CH_BRG_SHIFT_CLOCK
_PASSIVE_LEVEL_t
passive_level,
1736 const
XMC_USIC_CH_BRG_SHIFT_CLOCK
_OUTPUT_t clock_output)
1737 {
1738 channel->BRG = (uint32_t)(channel->BRG & (~(USIC_CH_BRG_SCLKCFG_Msk |
1739 USIC_CH_BRG_SCLKOSEL_Msk))) |
1740 (uint32_t)passive_level |
1741 (uint32_t)clock_output;
1742 }
1743
1744 /**
1747 * @param mode USIC channel operation mode. \n
1748 * \b Range: @ref XMC_USIC_CH_OPERATING_MODE_IDLE, @ref
XMC_USIC_CH_OPERATING_MODE_SPI,
1749 * @ref XMC_USIC_CH_OPERATING_MODE_UART, @ref
XMC_USIC_CH_OPERATING_MODE_I2S,
1750 * @ref XMC_USIC_CH_OPERATING_MODE_I2C.
1751 * @return None
1752 *
1754 * Sets the USIC channel operation mode.\n\n
1755 * A USIC channel can support multiple serial communication protocols like UART, SPI,
I2C and I2S.
1756 * The API sets the input operation mode to the USIC channel.
1757 *
1759 * XMC_USIC_Enable(), XMC_USIC_CH_Enable() \n\n\n
1760 */
1761 __STATIC_INLINE void XMC_USIC_CH_SetMode(XMC_USIC_CH_t *const channel, const
XMC_USIC_CH_OPERATING_MODE_t mode)
1762 {
1763 channel->CCR = (uint32_t)(channel->CCR & (~(USIC_CH_CCR_MODE_Msk))) | (uint32_t)mode
;
1764 }
1765 #ifdef __cplusplus
1766 }
1767 #endif
1768
1769 /**
1770 * @}
1771 */
1772
1773 /**
1774 * @}
1775 */
1776
1777 #endif
1778

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