 TDA7317

FIVE BANDS DIGITAL CONTROLLED GRAPHIC EQUALIZER

VOLUME CONTROL IN 0.375dB STEP

FIVE BANDS STEREO GRAPHIC EQUAL-
IZER
CENTER FREQUENCY, BANDWIDTH, MAX
BOOST/CUT DEFINED BY EXTERNAL COM-
PONENTS
±14dB CUT/BOOST CONTROL IN 2dB/STEP
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIALBUS
VERY LOW DISTORTION SDIP30
VERY LOW NOISE AND DC STEPPING BY
ORDERING NUMBER: TDA7317
USE OF A MIXED BIPOLAR/CMOS TECH-
NOLOGY

tenuated up to -17.625dB in 0.375dB step.

DESCRIPTION All the functions can be programmed via serial
The TDA7317 is a monolithic, digitally controlled bus making easy to build a µP controlled system.
graphic equalizer realized in BiCMOS mixed technol- Signal path is designed for very low noise and distor-
ogy. The stereo signal, before any filtering, can be at- tion.

BLOCK DIAGRAM

November 1999 1/12

TDA7317

PIN CONNECTION

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VS Supply Voltage 10.2 V
Top Operating Temperature Range -40 to +85 °C
Tstg Storage Temperature Range -55 to +150 °C
R tjvins Thermal Resistance Junction pins max 85 °C/W

ELECTRICAL CHARACTERISTICS (Tamb = 25°C, VS = 9V, RL = 10KΩ, Rg = 600Ω, f = 1KHz VIN =

1Vrms, all controls in flat position (AV = 0dB) unless otherwise specified).
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS Supply Voltage 6 9 10 V
IS Supply Current 8 14 20 mA
SVR Ripple Rejection f = 300Hz to 10KHz 60 80 dB

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 TDA7317

ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT
RI Input Resistance 20 30 40 KΩ
VIN max Max Input Signal THD = 0.3% 2 2.5 VRMS
IN S Input Separation (1) 80 100 dB
VOLUME CONTROL
C RANGE Control Range 17.625 dB
AVMIN Min. Attenuation -0.5 0 0.5 dB
AVMAX Max. Attenuation 16.7 17.625 18.6 dB
ASTEP Step Resolution 0.175 0.375 0.575 dB
EA Attenuation Set Error -1 1 dB
ET Tracking Error 0.5 dB
VDC DC Steps adjacent attenuation steps 0 3 mV
GRAPHIC EQUALIZER
THD Distortion 0.01 0.1 %
Cs Channel Separation 80 100 dB
e NO Output Noise BW = 20Hz to 20KHz 8 20 µV
flat, AV = 0dB
A curve 6 µV
BW = 20Hz to 20KHz AV = 0dB
All bands = max. boost 24 µV
All bands = max. cut 6 µV
S/N Signal to Noise Ratio AV = 0dB; Vref = 1VRMS 100 dB
Bstep Step Resolution 1 2 3 dB
C RANGE Control Range max boost/cut ±12 ±14 ±16 dB
VDC DC Steps Adiacent Control Steps 0.5 3 mV
AUDIO OUTPUTS
VO Output Voltage THD = 0.3% 2 2.5 VRMS
RL Output Load Resistance 2 KΩ
CL Output Load Capacitance 10 nF
RO Output Resistance 5 10 20 Ω
VOUT DC Voltage Level 4.2 4.5 4.8 V
BUS INPUTS
V IL Input Low Voltage 1 V
VIH Input High Voltage 3 V
IIN Input Current -5 +5 µA
VO Output Voltage SDA IO = 1.6mA 0.4 V
Acknowledge
ADDRESS PIN (Internal 50KΩ pull down resistor)
V IL Input Low Voltage 1 V
VIH Input High Voltage VCC -1V V
NOTE: The input is grounded thru the 2.2µP capacitors

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TDA7317
fo
Q=
DEVICE DESCRIPTION f2 − f1
The TDA7317 is a five bands, digitally controlled
stereo Graphic Equalizer. where f2, f1 = 3dB Bandwidth limits.
The device is intended for high quality audio ap-
plication in Hi-Fi, TV and car radio systems where (R2 ⋅ C2 ) + (R2 ⋅ C1 ) + (R1 ⋅ C1 )
Av =
feature like low noise and THD are key factors. A (R2 ⋅ C1 ) + (R2 ⋅ C2 )
mixed Bipolar Cmos Technology allows:
Cmos analog switches for pop free commuta- (R1 ⋅ C1 ⋅ R2 ⋅ C2 )
√

tions, high frequency op.amp. (GWB = 10MHz) Q=
and high linearity polisilicon resistor for THD = (R2 ⋅C1 ) + (R2 ⋅ C2 )
0.01 (at Vin = 1Vrms) and a S/N ratio of 102dB.
The internal Block Diagram is shown on page 1. 1
fo =
The first stage is a volume control. The control (R1 ⋅ R2 ⋅ C1 ⋅ C2)
2π ⋅ √
range is 0 to -17.625dB with 0.375dBstep.
The very high resolution (0.375dB step) allows If C1 is fixed, then:
the implementation of closed loop amplitude con-
trol system completely free from any acustical ef- Q2
C2 = ⋅ C1
fect (stepping variation and pumping effect). Av − 1 − Q2
The volume control is followed by a serial five
bands equalizer. Each filtering cell is the biquad 1
cell shown in fig. 1 R2 =
(Av −1 ) ⋅ Q
The internal resistor string is fixing the boost/cut 2 π ⋅ C1 ⋅ fo ⋅
value while the buffer makes the Q (quality factor) (Av − 1 − Q2)
and central frequency, set by external compo-
nents, fully indipendent from the internal resistors. (Av − 1)2
R1 = ⋅ R2
Each filtering cell is realized using only 4 external Av − 1 − Q2
components (2 capacitors and 2 resistors) allow-
ing a flexible selection of centre frequency fo, Q Likewise, the components’values can be deter-
factor and gain. Here below the basic formulae mined by fixing one of the other three parameters.
and the key features of each band pass filter are Referring to fig. 1 the suggested R2 value should
reported: be higher than 2KΩ in order to have a good THD
(internal op. amp. current limit).
Viceversa the R1 value should be equal or lower
fo = center frequency than 51KΩ in order to keep the ”click”(DC step)
Gv = gain/loss at the center frequency fo very low.
Gv = 20log(Av) A typical application is shown by fig. 2

Fig. 1

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 TDA7317

Figure 2: Application Circuit

The five bands graphic equalizer is used in con- dedicated ADDR pin allows 2 addresses selec-
junction with a TDA7318 (or another audioproces- tion. Anyway, the address of the graphic equalizer
sor of the SGS-THOMSON 731X family). is different from the audioprocessor one.
For example 11 bands are implemented by use of
The audioprocessor bass and treble tone can fur- 2 TDA7317 plus an audioprocessor (TDA731X
nish two extra filter bands. family).
Application requiring higher number of external In case one filtering cell is not needed, a short cir-
equalizer bands could be implemented by cas- cuit must be provided between the P1xy and
cading 2 or more TDA7317 devices. In fact the P2xy pins.

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TDA7317

I2C BUS INTERFACE Acknowledge

Data transmission from microprocessor to the The master (µP) puts a resistive HIGH level on the
TDA7317 and viceversa takes place thru the 2 SDA line during the acknowledge clock pulse (see
wires I2C BUS interface, consisting of the two fig. 5). The peripheral (audioprocessor) that ac-
lines SDA and SCL (pull-up resistors to positive knowledges has to pull-down (LOW) the SDA line
supply voltage must be externally connected). during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
Data Validity The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
As shown in fig. 3, the data on the SDA line must tion of each byte, otherwise the SDA line remains
be stable during the high period of the clock. The at the HIGH level during the ninth clock pulse
HIGH and LOW state of the data line can only time. In this case the master transmitter can gen-
change when the clock signal on the SCL line is erate the STOP information in order to abort the
LOW. transfer.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to Transmission without Acknowledge
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran- Avoiding to detect the acknowledge of the audio-
sition of the SDA line while SCL is HIGH. processor, the µP can use a simplier transmis-
sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
Byte Format sends the new data.
Every byte transferred to the SDA line must con- This approach of course is less protected from
tain 8 bits. Each byte must be followed by an ac- misworking and decreases the noise immunity.
knowledge bit. The MSB is transferred first.
Figure 3: Data Validity on the I2CBUS

Figure 4: Timing Diagram of I2CBUS

Figure 5: Acknowledge on the I2CBUS

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 TDA7317

SOFTWARE SPECIFICATION address (the 8th bit of the byte must be 0). The
TDA7317 must always acknowledge at the end
Interface Protocol of each transmitted byte.
The interface protocol comprises: A sequence of data (N-bytes + acknowledge)
A start condition (s)
A stop condition (P)
A chip address byte, containing the TDA7317

TDA7316 ADDRESS

MSB first byte LSB MSB LSB MSB LSB

S 1 0 0 0 0 1 A 0 ACK DATA ACK DATA ACK P

Data Transferred (N-bytes + Acknowledge)

ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s

SOFTWARE SPECIFICATION
Chip address (84 or 86 Hex)
1 0 0 0 0 1 A 0
MSB LSB

A = Logic level on pin ADDR

A = 1 if ADDR pin = open
A = 0 if ADDR pin = connected to ground

SOFTWARE SPECIFICATION (continued)

DATA BYTES (detailed description)
Volume
MSB LSB FUNCTION
0 X B2 B1 B0 A2 A1 A0 Volume 0.375dB steps
0 0 0 0
0 0 1 -0.375
0 1 0 -0.75
0 1 1 -1.125
1 0 0 -1.5
1 0 1 -1.875
1 1 0 -2.25
1 1 1 -2.625
0 X B2 B1 B0 A2 A1 A0 Volume -3dB steps
0 0 0 0
0 0 1 -3
0 1 0 -6
0 1 1 -9
1 0 0 -12
1 0 1 -15

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TDA7317

Graphic Equalizer
MSB LSB FUNCTION
1 D3 D2 D1 D0 S2 C1 C0
0 0 0 Band 1
0 0 1 Band 2
0 1 0 Band 3
0 1 1 Band 4
1 0 0 Band 5
D3 D2 D1 1 C2 C1 C0 cut
D3 D2 D1 0 C2 C1 C0 Boost
0 0 0 0dB
0 0 1 2dB
0 1 0 4dB
0 1 1 6dB
1 0 0 8dB
1 0 1 10dB
1 1 0 12dB
1 1 1 14dB
AX = 0.375dB steps, BX = 3dB steps, CX = 2dB steps, X = dont’care

STATUS AFTER POWER-ON RESET

Volume -17.25dB
Graphic equalizer bands -12dB

APPLICATION INFORMATION the P.C. Board and components layout are re-
ported in figure 5. The external components, are
A typical application is indicated in figure 4, while calculated for 2 different max boost/cut conditions

TABLE 1: Max Boost/cut = 20 dB (each cell = ±14dB)

F (HZ) Q R1 (KΩ) R2 (KΩ) C1 (nF) C2 (nF) Av max (dB)

BAND 1 10363.38 1.49 47 5.1 0.820 1.2 13.52
BAND 2 261.03 1.49 47 5.1 33 47 13.63
BAND 3 1036.34 1.49 47 5.1 8.2 12 13.52
BAND 4 3168.08 1.49 47 5.1 2.7 3.9 13.57
BAND 5 59.75 1.11 43 7.5 220 100 13.88
For THD performance the sequence Band 1, 2, 3, 4, 5, is recommended

TABLE2: Max Boost/cut = 17dB (each cell = ±12dB)

F (HZ) Q R1 (KΩ) R2 (KΩ) C1 (nF) C2 (nF) Av max (dB)

BAND 1 10158.00 1.15 33 6.2 1.2 1 11.83
BAND 2 250.81 1.21 30 5.1 47 56 11.33
BAND 3 977.34 1.20 39 6.8 10 10 11.75
BAND 4 3429.00 1.25 39 6.2 2.7 3.3 11.67
BAND 5 61.82 1.15 33 6.2 180 180 11.27

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 TDA7317

Figure 4

Figure 5: PCP Board and components layout of the figure 4 (scale 1:1)

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TDA7317

Measurements done on the test jig of fig. 5 using in figg. 6, 7,8.

the components indicated in table2, are reported
Figure 6: Frequency Response Figure 7 THD vs Frequency Max Boost/cut =
:±14dB

Figure 8: Cross Talk vs Frequency

Purchase of I2C Components of SGS-THOMSON Microlectronics, conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to
the I2C Standard Specifications as defined by Philips.

10/12
 TDA7317

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA
A 5.08 0.20

A1 0.51 0.020

A2 3.05 3.81 4.57 0.12 0.15 0.18

B 0.36 0.46 0.56 0.014 0.018 0.022

B1 0.76 0.99 1.40 0.030 0.039 0.055

C 0.20 0.25 0.36 0.008 0.01 0.014

D 27.43 27.94 28.45 1.08 1.10 1.12

E 10.16 10.41 11.05 0.400 0.410 0.435

E1 8.38 8.64 9.40 0.330 0.340 0.370

e 1.778 0.070

e1 10.16 0.400

L 2.54 3.30 3.81 0.10 0.13 0.15

M 0°(min.), 15°(max.)
SDIP30 (0.400”)
S 0.31 0.012

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TDA7317

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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