BSP75N Transistor Inhibodor Arranque
BSP75N Transistor Inhibodor Arranque
BSP75N Transistor Inhibodor Arranque
Description
S
Self-protected low side MOSFET. Monolithic over temperature, over
current, over voltage (active clamp) and ESD protected logic level
functionality. Intended as a general purpose switch. S D
IN
Features Note:
The tab is connected to the source pin and must
• Short circuit protection with auto restart be electrically isolated from the drain pin.
• Over-voltage protection (active clamp) Connection of significant copper to the drain pin
is recommended for best thermal performance.
• Thermal shutdown with auto restart
• Over-current protection
• Input protection (ESD)
• High continuous current rating
• Load dump protection (actively protects load)
• Logic level input
Ordering information
Device marking
BSP75N
Over voltage
protection
dV/dt
IN
limitation
Over current
protection
Human body
ESD protection Logic
Over temperature
protection
Applications
• Especially suited for loads with a high in-rush current such as lamps and motors.
• All types of resistive, inductive and capacitive loads in switching applications.
• C compatible power switch for 12V and 24V DC applications.
• Automotive rated.
• Replaces electromechanical relays and discrete circuits.
Linear mode capability - the current-limiting protection circuitry is designed to de-activate at low
Vds, in order not to compromise the load current during normal operation. The design maximum
DC operating current is therefore determined by the thermal capability of the package/board
combination, rather than by the protection circuitry. This does not compromise the products
ability to self protect itself at low VDS.
Thermal resistance
Parameter Symbol Limit Unit
Junction to ambient (a) R⍜JA 83 °C/W
NOTES:
(a) For a device surface mounted on 25mm x 25mm x 1.6mm FR4 board with a high coverage of single sided 2oz weight
copper. Allocation of 6cm2 copper 33% to source tab and 66% to drain pin with tab and drain pin electrically isolated.
(b) For a device surface mounted on FR4 board as (a) and measured at t<=10s.
(c) For a device surface mounted on FR4 board with the minimum copper required for connections.
NOTES:
(*) The drain current is limited to a reduced value when VDS exceeds a safe level.
(†) Protection features may operate outside spec for VIN<4.5V.
(‡) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
datasheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed
for continuous, repetitive operation.
Application information
The current-limit protection circuitry is designed to de-activate at low VDS to prevent the load
current from being unnecessarily restricted during normal operation. The design max DC
operating current is therefore determined by the thermal capability of the package/board
combination, rather than by the protection circuitry (see graph on page 7 'Typical Output
Characteristic'). This does not compromise the products ability to self protect at low VDS.
The overtemperature protection circuit trips at a minimum of 150°C. So the available package
dissipation reduces as the maximum required ambient temperature increases. This leads to the
following maximum recommended continuous operating currents.
Typical characteristics