VLSI Design 18EC72

Module 5
Memory, Registers and Aspects of System Timing
System Timing Considerations
1. Two phase non-overlapping clock is assumed to be available and this clock will be
used throughout the system.
2. Clock phases are assumed to be ϕ1 and ϕ2 and ϕ1 is assumed to lead ϕ2.
3. Bits (data) to be stored are written to registers, storage elements and subsystems on ϕ1
of the clock i.e., WR (write) signal is ANDed with ϕ1.
4. Bits written into storage elements may be assumed to have settled before ϕ2 signal
(which follows immediately) and ϕ2 signal may be used for refreshing the stored data.
5. Delay through data paths, combinational logic etc., are assumed to be less than the
interval between leading edge of ϕ1 of the clock and leading edge of following ϕ2
signal.
6. Bits or data may be read from storage elements on the next of ϕ1. RD (read) signal is
ANDed with ϕ1. Thus RD and WR signals are mutually exclusive.
7. General requirement for system stability is that there must be at least one clocked
storage element in series with every clocked loop signal path.

Some commonly used storage/memory elements:

The storage elements are compared based on three parameters
1. Area requirement
2. Estimated dissipation per bit stored.
3. Volatility

A three-transistor Dynamic RAM Cell (3T DRAM Cell)

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VLSI Design 18EC72

 In this cell arrangement it uses a single transistor for storing data and 2 transistors for
each RD and WR access switch.
 It has a pull-up network with either CMOS or nMOS technology and RD/WR circuit
as pull-down network.
 The binary data is stored at gate capacitance of transistor in the form of charge; RD
and WR are the control lines.
 T1 with T2 is used for writing the data and T3 with T2 is used for reading the data. At
point I data is written and read.
 Here T2 is the storage transistor and T1 & T3 are pass transistors which acts as access
switches for control lines RD and WR and also for read and write operations.

Write Operation
 WR and RD signals are mutually exclusive i.e., compliment to each other.
 When WR = 1, RD will be 0
 Because of WR = 1, T1 is ON but T3 and T2 are OFF.
 If data bit on bus is 1, as T1 pass transistor is ON it will pass the signal (VDD
– Vth) towards T2. The capacitor is charged to this potential at I
 If data bit is 0, as T1 is ON it will pass the signal and charge stored at I is 0.
 After the data is stored at I or capacitor WR signal is made to 0
Read Operation
 For this RD = 1, WR = 0
 As WR = 0, T1 is OFF and T3 is ON as RD = 1
 T2 will be ON/OFF depending on the voltage/charge stored at I (gate
capacitance of T2)
 If logic 1 is stored at I, then T2 will be ON. Thus T3 and T2 is ON and
path for discharge and the bus is pulled down to ground.
 If logic 0 is stored at I, the T2 is OFF and charge does not any path for
discharge and retains logic at logic1
Note: The compliment of stored bit is read on the data bus
 In DRAM sensing amplifiers will be connected and as the output begins to
decrease from 1 to 0 and this makes the sensing amplifier output as logic 1. If
the output does not change then sensing amplifier will make the output as logic
0.
Static Power:
 Static power dissipation is nil since current flows only when i )RD signal is
high and ii)logic 1 is stored
 Thus actual dissipation associated with each stored bit depends on the bus pull-
up and the duration RD and on switching frequency

Area:
 In 4mm× 4mm, silicon chip area data storage can be >4.8kbits.
Volatility:
 Cell is dynamic and will hold data only for as long as sufficient charge remains
on gate capacitance of T2
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VLSI Design 18EC72

One-Transistor Dynamic Memory Cell:

 This is an approach which reduces area/bit
 It consists of capacitor Cm and pass transistor. The circuit arrangement and
stick diagram is shown in Fig a & b.

Write operation
 The capacitor Cm will be charged when Read/Write = 1 and Row Select = 1
 If the Read/Write line is provided with logic 1, Cm will be charged to logic 1
and if the line is provided with logic 0 charge stored will be logic 0.
Read operation
 If logic 0 is stored in Cm and when Row select line is high M1 is ON. Then
the sense amplifier at the bit line will sense and give the output as logic 0
 If logic 1 is stored in Cm and when Row select line is high M1 is ON, the logic
1 stored will begin to discharge as the path exists. The sense amplifier senses
this and this gives the output as logic 1
 The area occupied in 1T DRAM cell configuration is of a single transistor and a
capacitor
 Larger the value of Cm longer is the duration of storage of charge. Thus Cm should
be large. But this in turn consumes more space.
 However the transistor and capacitor can be built in a single transistor.
 Cm can be fabricated by extending and enlarging the diffusion area forming the source
of process transistor. For this capacitance between n-diffusion and p-substrate is
considered.
 But this value is very small compared to gate capacitance
 Thus in order to get higher Cm larger area is required.
 An alternate solution to this by using a polysilicon plate used over diffusion area. This
results in the formation of a 3 plate capacitor structure, where polysilicon plate is
connected to VDD. This is shown in the Fig c.

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VLSI Design 18EC72

Area:
 In 4mm× 4mm, silicon chip area data storage is about 12 Kbits.
Dissipation:
 With the cell there is no static dissipation but switching energy while reading
and writing must be considered.
Volatility:
 The data in Cm will be held only up-to 1msec or less. Thus periodic refreshing
must be provided

Pseudo-static RAM/register cell:

 This is a memory cell which combines high storage capability of DRAM and ease of
use of SRAM
 It can be used as SRAM as no external refreshing circuit is required and also used as
a DRAM having built-in refresh logic.
 This is a static storage cell which will hold data indefinitely. This is achieved by
storing bit in 2 inverters with feedback. This feedback is used to refresh the data in
every clock cycle.
 But care to be taken by not allowing read/write operation during internal refreshing.
 Circuit arrangement is as shown in the Fig.
 Φ1 and ϕ2 are mutually exclusive clock signals, WR and RD signal coincides with ϕ1
signals
 When ϕ1 is high and WR = 1, transistor T1 is ON and data is charged/stored on Cg
(gate capacitance) of inverter. This is write operation
 When ϕ1 is high and RD = 1, transistor &the data stored at inverter stage is made
available at the output and also the compliment. Thus data is read at the output. 
 When Φ2 = 1, T3 is ON. The output is read and feedback i.e., refreshed (reading and
storing back the data). The gated feedback path from output of T2 is fed to the input
of T1.
 The bit will be held as long as ϕ2 rescues and this time is less than decay time of stored
charged bit.

Note:
 WR and RD must be mutually exclusive but both should coincide with ϕ1
 During refreshing of memory cell i.e., at ϕ2 the cell must not be read. If an attempt is
made to read the cell data onto the bus, the charge sharing effect between bus and Cg
(input gate capacitance) may cause destruction of stored bit.
 Other bus lines should be allowed to run through the cells so that register and memory
arrays can be easily configured.

 The Pseudo-static memory cell can also be implemented using transmission gate (TG).
This is seen the Fig. [replace nMOS transistors with TG]

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VLSI Design 18EC72

Area:
 In 4mm× 4mm, silicon chip area data storage is about 1.4 Kbits.
Dissipation:
 The nMOS cell uses 2 inverters, one with 8:1and other with 4:1 ratio. Thus
power dissipation depends on the current drawn and actual geometry of the
inverters.
Volatility:
 The cell is non-volatile until unless ϕ2 is present.
Four Transistor Dynamic and Six-Transistor CMOS memory cell:
 The cells here include both n-type and p-type transistors and are intended for
CMOS systems.
 Both the dynamic and static elements uses 2 bus per bit arrangement so that the
bit is available in both normal and compliment form on bit and bit’ bus
 Prior to reading and writing operation of the data, the buses are pre-charged to VDD
or logic 1.
4 Transistor Dynamic memory cell:

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VLSI Design 18EC72

Fig. four transistor dynamic RAM with sense amplifier

Write operation:
 Before writing onto memory the bit and bit’ line is pre-charged to logic 1 using
pMOS transistor T5 and T6 in coincidence with clock signal ϕ1
 Next appropriate column is selected in coincidence with the clock signal ϕ2.
 Depending on the data on the bus either bit or bit’ is discharged.
 At the same clock signal ϕ2 the row select line is activated, turning on
transistors T3 and T4.
 Thus value on bit and bit’ are written via T3 and T4 stored at T2 and T1 as
gate capacitances Cg2 and Cg1 respectively.
 The way in which T2 and T1 are connected always gives the complimentary
states when row select line is activated. When row line is deactivated the data
stored will remain until the gate capacitance can hold the value.
 For refreshing sense amplifier is provided which will permanently hold the
data.
Read operation:
 Before reading again bit and bit’ lines are pre-charged to VDD using T5 and T6
transistors.
 Suppose in the memory element if logic 1 is stored i.e., at gate of T2 and at
gate of T4 logic 1 is stored.

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VLSI Design 18EC72

 When column and row lines are selected i.e., T3 and T4 will be in ON state.
 As logic 1 is available at T2, T2 will be in ON state and T1 will be in OFF
state. Thus T3 = ON, T1 = OFF, T4 = ON, T2 = ON. With this condition bit’
which was pre-charged to VDD has now a path to discharge to VSS. Hence bit’
= 0 and bit = 1 as shown in the Fig.
 When sense amplifier senses this voltage variation on bit’ line and outputs the
data on bus line. The bit = 1 and bit’ = 0, which represents the data in the
memory.
 The sense amplifier formed from the arrangement of T1, T2, T3 and T4, which
forms a flip flop circuit.
 If the “sense” de-active/ inactive, then the bit line state is reflected in the gate
capacitances of T1 and T3 and this is w.r.t VDD. This will cause one of the
transistor to turn ON and other to turn OFF.
 When sense = enabled, current flows from VDD through ON transistor and
helps to maintain the state of the bit line.
 Sense amplifier performs 2 function
1. Rewriting the data after reading i.e., refreshing the memory cell so that it
holds the data without signal degradation
2. It predetermines the state of the data lines.

Fig. shows Read operation in the memory cell and in the sense amplifier.

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VLSI Design 18EC72

Six Transistor Static RAM cell:

Fig. six transistor static RAM cell with sense amplifier

 Figure shows 6 T SRAM with the adaption of dynamic cell and modifying it to form
a static memory cell.
 It includes 2 additional transistor per store bit thus it is called 6 transistor. The
transistor T5 and T6 acts as the access switch for memory element which is formed
by connecting two inverters back to back (i.e., output of one is connected as the input
of the other)
 Similar to 4T Dynamic RAM the information is stored in memory cell. The memory
cell is connected in such a way that it gives the complimentary states when row select
line is activated. When row line is deactivated the data stored will remain in the
memory cell.

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VLSI Design 18EC72

Below Fig. shows dynamic and static RAM cell together as the sense amplifier is same
in both the memory cell.

JK flip flop:
 It is a memory element. It is the widely used arrangement for static memory
element.
 Also with JK other flip-flop arrangements can be obtained such as T and D
flip-flop.

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VLSI Design 18EC72

 The flip-flop has inputs clocked J and K along with asynchronous clear and
has the output as Q and Q’
 The inputs J and K are read for the rising edge of clock signal and data is
passed to the output for the falling edge of clock.
Note: here JK is implemented in master slave configuration in order to solve the race around
condition

Gate Implementation of flip-flops:

 The expressions for the flip-flops can be implemented using either NAND or NOR
logic
 If NAND arrangement is used (in NAND inputs have to be connected in series) then
it would take large area. Also it is seen that when connected in series the overall delay
increases and in practice not more than 4 transistors should be connected in series.
However the number can be increased by including buffers in between and next four
transistors. Also it is seen that performance of NAND is slower than NOR.
 In NOR the implementation can be done easily (as the inputs have to be connected in
parallel)

Switch logic and inverter implementation:

 If n pass transistors are used to realize the logical requirements, it must be kept in
mind that
1. There should be more than 4 pass transistors connected in series.
2. One pass transistor should not drive the gate of other pass transistor.
D and T flip-flop circuit:
D flip-flop can be formed from JK by connecting an inverter between both inputs.
T flip-flop can be readily formed from JK by connecting JK to form T input. This is
shown in the Fig.

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