A. Y.

:2022-23
Name of the Course
YS. : III Sem :II

Course File

Name of the Faculty: SK.SHABANA

Department :ECE Regulation:R20
Course :B-TECH Course Code:R2022042
Year :II Sem :II Academic year:2022-2023

S. No Description Remarks
1. Vision, Mission and PEOs
2. College Academic Calendar
3. Time Table (Class & Individual)
4. Students Nominal List
5. Attendance Register
6. Syllabus
7. Content Beyond Syllabus
8. POs and PSOs
9. Course Outcomes (COs)
10. Mapping of COs with POs and PSOs
11. Lesson Plan
12. Conceptual Plan
13. Question Bank (with COs)
14. Assignment Questions (With COs)
15. Sample Assignment Copies
16. Internal Exam Question Paper
17. Scheme of Valuation for Internal Exam Question Paper
18. Sample Answer Booklet Copies (Good, Average, Poor)
19. Internal Exam Marks sheets
20. COs Assessment
21. COs Attainments
22. Course Material (Manu Script/Printed)
23. University Exam Results & Analysis
24. Previous Question Papers

Faculty Head of the Department Principal

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Institution
Vision: To contribute for sustainable development of nation through achieving
excellence in technical education and research while facilitating transformation of
students into responsible citizens and competent professionals.

Mission:
 To impart affordable and quality education in order to meet the needs of industries
and achieve excellence in teaching-learning process.
 To collaborate with other academic & research institutes as well as industries in
order to strengthen education and multidisciplinary research.
 To promote equitable and harmonious growth of students, academicians, staff,
society and industries, thereby becoming a centre of excellence in technical
education.

Department of ECE

Vision

To be recognised by the society at large as a full- fledged department, offering

quality higher education in the Electronics and Communication Engineering field
with research focus catering to the needs of the public and staying in tune with the
advancing technological revolution and challenging cultural changes.

Mission

M1: To engage modern education aids, laboratories and competent faculty ensuring
effective teaching learning process to meet the ever growing and changing industrial
and business environment.
M2: To continuously challenge the young minds with ideas to carry out innovative
research through interaction with the research organizations & industry.
M3: To develop responsible citizens and professional leaders with high ethical and
moral values, who contribute in dissemination of universal science and technology
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Program Educational Objectives (PEO’s) of the Department

PEO-1:To prepare Graduates with sound foundation in fundamentals of basic

sciences and to assist them exhibit strong, independent learning, analytical
&problem-solving skills in Electronics and Communication Engineering domain.
PEO-2:To facilitate learning in the core field of Electronics and Communication
Engineering so as to integrate technological progression and software & firmware
skills to produce high impact, energy efficient and futuristic solutions.
PEO-3:To prepare Graduates to effectively use modern equipmentand programming
tools to solve real life multi-disciplinary problems that are technically sound,
economically feasible and socially acceptable.
PEO-4:To inculcate professional and ethical attitude, team spirit, leadership qualities
and effective communication skills in Graduates and to make them aware of their
social responsibilities.
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Faculty Details
Name of the Faculty : SK.SHABANA

Designation :ASSOCIATIVE PROFESSOR

Department : ELECTRONICS AND COMMUNICATION ENGINEERING

Course Details

Name of the Programme :B-TECH

Batch : 2022-2023

Branch : ECE

Semester : II/II

Title of the Course : DIGITAL IC DESIGN

Course Code : R2022042

Course Type : Core: √ Open Elective: Elective: Add-on: Lab:

Number of Students : 15

Faculty Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

PAPER STATUS
1. ATTAINMENT
1.1. Pass Percentage :
1.2. Pass with I Class Percentage :
1.3. Overall COs Attainment :
1.4. CO Code : R2022042

COs CO-1 CO-2 CO-3 CO-4 CO-5

Attainment

2. COURSE PLAN
Unit-1: Contents of this unit will be covered by Class room Lectures, Power Point
Presentations, Video presentations, Assignments.
Unit-2: Contents of this unit will be covered by Class room Lectures, Power Point
Presentations, Video presentations, Assignments.
Unit-3: Contents of this unit will be covered by Class room Lectures, Power Point
Presentations, Video presentations, Assignments.
Unit-4: Contents of this unit will be covered by Class room Lectures, Power Point
Presentations, Video presentations, Assignments.
Unit-5: Contents of this unit will be covered by Class room Lectures, Power Point
Presentations, Video presentations, Assignments.

3. METHOD OF EVALUATION
3.1. Continuous Assessment Examinations (MID-1, MID-2)
3.2. Assignments / Seminars
3.3. Mini Projects
3.4. Quizzes
3.5. University Examinations
3.6. Others, Specify if any

Faculty Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

PREREQUISITES FOR THE COURSE OF STUDY

1. Courses of study to be completed as prerequisites

2. Title of the course: SUBJECT NAME: DIGITAL IC DESIGN

3. Course Objectives :
The main objectives of this course are:
 Introduction of digital logic families and inter facing concepts for digital design is
considered.
 VHDL fundamentals were discussed to modeling the digital system design blocks.
 Design and implementation of combinational and sequential digital logic circuits is
explained.

Faculty Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

ACADEMIC CALENDAR

DESCRIPTION FROM TO WEEKS

I UNIT OF INSTRUCTIONS 30-01-2023 25-03-2023 8W

I MID EXAMINATIONS 20-03-2023 25-03-2023 1W

II UNIT OF ONSTRUCTIONS 27-03-2023 20-05-2023 8W`

II MID EXAMINATIONS 19-06-2023 24-06-2023 1W

SUMMER INTERNSHIP 22-05-2023 17-06-2023 4W

PREPARATION & PRACTICALS 26-06-2023 01-07-2023 1W

END EXAMINATIONS 03-07-2023 15-07-2023 2W

Faculty Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

TIME TABLE

CLASS TIMETABLE
DAY 1 2 3 4 5 6 7
MON ECA MOB COI DID LIB LCS AC

TUE ECA MOB AC LCSI DID LAB

WED AC MOB LCS DID ECA LAB

THU MOB COI AC ECA LCS DID SPORTS

FRI LCS ECA DID COI AC LAB

SAT MOB AC ECA DID SOFT SKILS

INDIVIDUAL TIMETABLE
DAY 1 2 3 4 5 6 7
MON DID

TUE DID LAB

WED DID
DID
THU

FRI DID

SAT DID

Faculty Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

STUDENTS NOMINAL LIST

S.NO HALL TICKET NO. NAME OF THE STUDENT

1 21GK1A0401 BANDI. SRAVAN
2 21GK1A0402 GOLLA. GANESH
3 21GK1A0403 JAMMALAMUDI. DAVID RAJU
4 21GK1A0404 MEENUGUKASA. KEERTHANA
5 21GK1A0405 SATHULURI. SAI VARMA
6 21GK1A0406 SREERAM KISHORE KUMAR
7 21GK1A0407 BANDLA. NAGA BHUSHANAM
8 21GK1A0408 KURRA. VAMSI KRISHNA
9 21GK1A0410 MATTEPALLI. DEEPAK KUMAR
10 21GK1A0411 PATHAKAMURI. AJAY
11 22GK5A0401 SHAIK. HASEENA
12 22GK5A0402 G. MADHU KIRAN
13 22GK5A0403 K. MAHESH
14 22GK5A0404 M. SANEEP NAIK
15 22GK5A0405 Y. VENKATA SAI BHAVANI

Faculty Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Course Outcomes
After the completion of the course the student should be able to:
CO Code Course Outcome

22042.1 Understand the structure of commercially available digital integrated circuit families.

22042.2 Learn the IEEE Standard 1076 Hardware Description Language (VHDL)..

22042.3 Model complex digital systems at several levels of abstractions, behavioral, structural, and
rapid system prototyping

Analyze and design basic digital circuits with combinatorial and sequential logic circuits
22042.4
using VHDL.

Faculty

Note:
1. COs are to be formulated as ONE per each unit with a total of four to six course outcomes.
2. Internal / Mid questions should contain the related course outcomes in brackets.
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Program Outcomes

Engineering Knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and
PO1
Engineering specializations to the solution of complex engineering problems.
Problem Analysis: Identify, Formulate, review research literature and analyze complex
PO2 engineering problems to arrive at substantiated conclusions using first principles of
mathematics, natural and engineering sciences
Design/Development of Solutions: Design solutions for complex engineering problems and design system
PO3 components, processes to meet the specifications with consideration for the public health and safety, and the
cultural, societal, and environmental considerations
Conduct Investigations of Complex Problems: Use research-based knowledge including design of experiments,
PO4
analysis and interpretation of data, and synthesis of the information to provide valid conclusions
Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT
PO5 tools including prediction and modelling to complex engineering activities with an understanding of the
limitations
The Engineer and Society: Apply Reasoning informed by the contextual knowledge to assess
PO6 societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice
Environment and Sustainability: Understand the impact of the professional engineering
PO7 solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development
Ethics: Apply Ethical Principles and commit to professional ethics and responsibilities and
PO8
norms of the engineering practice
Individual and Team Work: Function effectively as an individual and as a member or leader in
PO9
teams and in multidisciplinary Settings
Communication: Communicate effectively with the engineering community and with society at large. Be able to
PO10 comprehend and write effective reports documentation. Make effective presentations, and give and receive clear
instructions.
Project Management and Finance: Demonstrate knowledge and understanding of engineering and management
PO11 principles and Apply these to one’s own work, as a member and leader in a team. Manage projects in
multidisciplinary environments
Life-Long Learning: Recognize the need for, and have the preparation and ability to engage in independent and
PO12
life-long learning in the broadest context of technological change

Program Specific Outcomes

PSO-1: Apply the fundamental concepts of electronics and communication engineering to
PSO1 design a variety of components and systems for real time applications.

PSO-1: Apply the fundamental concepts of electronics and communication engineering to

PSO2 design a variety of components and systems for real time applications.
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

 COs – POs Relationship Matrix (Levels of Matrix: 3-High Level, 2-Moderate Level and 1-Low
Level of attainments).

CO-PO Matrix
CO Code PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

22042.1 3 2 3 2 3 2 1 3 2 3 1 3

22042.2 3 2 3 2 3 2 1 3 2 3 1 3

22042.3 3 2 3 2 3 2 1 3 2 3 1 3

22042.4 3 2 3 2 3 2 1 3 2 3 1 3

22042.5 3 2 3 2 3 2 1 3 2 3 1 3

Average 3 2 3 2 3 2 1 3 2 3 1 3

CO Code PSO1 PSO2

22042.1 3 3
22042.2 3 3
22042.3 3 3
22042.4 3 3
22042.5 3 3
Average 3 3

Faculty Academic Coordinator Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

COURSE SCHEDULE
Name of the Course : B-TECH
Course Code : R2022042
Branch : ECE
Un Duration (Dates) Total No.
Description of
it From To Hours

UNIT – I:
Hardware Description Languages.
VHDL: Introduction to VHDL, entity declaration,
architecture, data-flow, behavioral and structural style
ofmodelings,datatypes,dataobjects,configurationdeclaratio
1 n,package,generic,operatorsandidentifiers,PROCE 01-02-2023 25-02-2023 23
SS,IF, CASE & LOOP statements, VHDL libraries.
Verilog HDL: Introduction to Verilog HDL, data types,
data operators, module statement, wire statement, if else
statement,
case-end case statement, Verilog syntax and
semantics(qualitative approach)
UNIT –II:
Combinational Logic Design: Parallel binary adder,
carry look ahead adder, BCD adder, Multiplexers
And de multiplexers and their use in combinational logic
2 design, ALU, digital comparators, parity generators, 27-02-2023 31-03-2023 11
Code converters, priority encoders. (Qualitative approach
of designing and modeling the mentioned
Combinational logic circuits with relevant digital ICs
using HDL
UNIT –III:
Sequential Logic Design: Registers, applications of shift
registers, ripple or a synchronous counters,
3 synchronous counters, synchronous and a synchronous 03-04-2023 13-04-2023 09
sequential circuits, hazards in sequential circuits.
(Qualitative approach of designing and modeling the
mentioned sequential logic circuits with relevant digital
ICs using HD
UNIT – IV:
Combinational MOS Logic Circuits: Introduction, MOS
logic circuits with depletion n MOS loads: two input NO
gate, generalized NOR structure with multiple inputs,
transient analysis of NOR gate, two-input NAND gate,
4 generalized NAND structure with multiple inputs, 17-04-2023 12-05-2023 21
transient analysis of NAND gate, CMOS logic
circuits :CMOS NOR2 gate, CMOS NAND2 gate,
complex logic circuits, complex CMOS logic gates, AOI
and OAI gates, Pseudo-n MOS gates, CMOS full-adder
circuit, CMOS transmission gates (Pass Gates),
Complementary pass-transistor logic
UNIT –V:
5 Sequential MOS Logic Circuits: Introduction, behavior 12-05-2023 20-05-2023 14
bistable elements, SR latch circuit, clocked latch
And flip-flop circuits: clocked SR latch, clocked JK latch,
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

master-slave flip-flop, CMOS D-latch and Edge triggered

flip-flop, Schmitt trigger circuit, basic principles of pass
transistor circuits

Faculty Academic Coordinator Head of the Department

LESSON PLAN
DEPT : Electronics and Communication Engineering
COURSE: DID
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Sched
uled
Actual
Unit
Schedule of Topics/Activities No of No of Remarks
No. Date
hours hours
UNIT – I
1 Introduction to VHDL 1 1 01-02-2023
2 entity declaration 1 1 2-02-2023
3 architecture 1 1 3-02-2023
4 Data -flow 1 1 4-02-2023
5 behavioral and structural style of modelling s 1 2 6-02-2023
6 Data types 1 1 8-02-2023
7 Data objects 1 1 9-02-2023
8 Configuration declaration 1 1 10-02-2023
9 Package ,generic, operators and identifiers 1 1 11-02-2023
10 PROCE SS,IF, CASE & LOOP statements 1 2 13-02-2023
11 VHDL libraries 1 1 16-02-2023
12 Verilog HDL: Introduction to Verilog HDL 1 2 17-02-2023
13 data types, data operators 1 1 20-02-2023
14 module statement 1 1 21-02-2023
15 wire statement 1 2 22-02-2023
16 if- else statement 1 1 23-02-2023
17 case-end case statement 1 1 24-02-2023
18 Verilog syntax and semantics(qualitative approach) 1 2 25-02-2023
UNIT II
19 Parallel binary adder 1 1 27-02-2023
20 carry look ahead adder 1 1 01-03-2023
21 BCD adder 1 2 2-03-2023
Multiplexers and de multiplexers and their use in combinational
22 1 1 3-03-2023
logic design
23 ALU, digital comparators 1 1 4-03-2023
24 parity generators 1 1 6-03-2023
25 Code converters 1 1 27-03-2023
26 priority encoders 1 1 29-03-2023
Qualitative approach of designing and modelling the mentioned
27 combinational logic circuits with relevant digital ICs using 1 2 31-03-2023
HDL
UNIT III
28 Registers 1 1 03-04-2023
29 applications of shift registers 1 1 5-04-2023
30 ripple or a synchronous counters 1 1 6-04-2023
31 synchronous counters 1 2 8-04-2023
32 synchronous and a synchronous sequential circuits 1 1 10-04-2023
33 hazards in sequential circuits 1 1 12-04-2023
34 Qualitative approach of designing and modelling the mentioned 1
sequential logic circuits with relevant digital ICs using HDL) 2 13-04-2023

UNIT IV
35 Combinational MOS Logic Circuits: Introduction 1 1 17-04-2023
36 MOS logic circuits with depletion n MOS loads: two- input
1 1 19-04-2023
NOR gate
37 generalized NOR structure with multiple inputs 1 2 20-04-2023
38 transient analysis of NOR gate 1 1 24-04-2023
39 two-input NAND gate 1 2 26-04-2023
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

40 generalized NAND structure with multiple inputs 1 1 27-04-2023

41 transient analysis of NAND gate 1 1 28-04-2023
42 CMOS logic circuits: CMOS NOR2 gate 1 2 29-04-2023
43 CMOS NAND2 gate 1 1 01-05-2023
44 complex logic circuits 1 1 3-05-2023
45 complex CMOS logic gates 1 1 4-05-2023
46 AOI and OAI gates 1 2 6-05-2023
47 Pseudo- n MOS gates 1 1 8-05-2023
48 CMOS full-adder circuit 1 1 10-05-2023
49 CMOS transmission gates (Pass Gates) 1 1 11-05-2023
50 Complementary pass-transistor logic. 1 2 12-05-2023
UNIT V
51 Sequential MOS Logic Circuits: Introduction 1 2 12-05-2023
52 Behavior bi- stable elements 1 1 13-05-2023
53 SR latch circuit 1 1 14-05-2023
54 clocked latch and flip-flop circuits 1 1 14-05-2023
55 clocked SR latch 1 2 15-05-2023
56 clocked JK latch 1 1 16-05-2023
57 master-slave flip-flop 1 1 17-05-2023
58 CMOS D-latch and Edge- triggered flip-flop 1 2 18-05-2023
59 Schmitt trigger circuit 1 2 19-05-2023
60 basic principles of pass transistor circuits 1 1 20-05-2023

Text Books:
1. Modern Digital Electronics–R.P.Jain-Fourth Edition–Tata McGraw Hill Education Private
Limited,2010.
2. CMOS Digital Integrated Circuits-Analysis and Design–Sung-MoKang & Yusuf Leblebici
Tata
McGraw Hill Publishing Company Limited, 2006.
3. VHDL/VerilogPrimer - J.Bhasker, Pearson Education/PHI, 3rd Edition.

Reference Books:

1. Digital Design Principles & Practices-John F.Wakerly, PHI/Pearson Education Asia, 3rd Edition,
2005.
2. Fundamentals of Digital Logic with VHDL Design - Stephen Brown, Zvonko Vranesic, McGraw Hill,
3rd Edition.

Faculty Academic Coordinator Head of the Department

COURSE COMPLETION STATUS
Nos. of
Actual Date
COs Signature
Unit Description of
Achiev of HOD
Completion
ed
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

UNIT – I:
Hardware Description Languages.
VHDL: Introduction to VHDL, entity declaration, architecture,
data-flow, behavioral and structural style Of modeling, data
types, data objects, configure action declaration, package,
1 25-02-2023 CO-1
generic, operators and identifiers, PROCESS,IF, CASE &
LOOP statements, VHDL libraries. Verilog HDL: Introduction
to Verilog HDL, data types, data operators, module statement,
wire statement, if else statement, case-end case statement,
Verilog syntax and semantics(qualitative approach)
UNIT –II:
Combinational Logic Design: Parallel binary adder, carry look
ahead adder, BCD adder, Multiplexers And de multiplexers and
their use in combinational logic design, ALU, digital
2 31-03-2023 CO-2
comparators, parity generators, Code converters, priority
encoders. (Qualitative approach of designing and modeling the
mentioned Combinational logic circuits with relevant digital ICs
using HDL
UNIT –III:
Sequential Logic Design: Registers, applications of shift
registers, ripple or a synchronous counters, synchronous
3 counters, synchronous and a synchronous sequential circuits, 13-04-2023 CO-3
hazards in sequential circuits. (Qualitative approach of designing
and modeling the mentioned sequential logic circuits with
relevant digital ICs using HD
UNIT – IV:
Combinational MOS Logic Circuits: Introduction, MOS logic
circuits with depletion n MOS loads: two input NO
gate, generalized NOR structure with multiple inputs, transient
analysis of NOR gate, two-input NAND gate, generalized
4 NAND structure with multiple inputs, transient analysis of 12-05-2023 CO-4
NAND gate, CMOS logic circuits :CMOS NOR2 gate, CMOS
NAND2 gate, complex logic circuits, complex CMOS logic
gates, AOI and OAI gates, Pseudo-n MOS gates, CMOS full-
adder circuit, CMOS transmission gates (Pass Gates),
Complementary pass-transistor logic
UNIT –V:
Sequential MOS Logic Circuits: Introduction, behavior
bistable elements, SR latch circuit, clocked latch
5 And flip-flop circuits: clocked SR latch, clocked JK latch, 20-05-2023 CO-5
master-slave flip-flop, CMOS D-latch and Edge triggered flip-
flop, Schmitt trigger circuit, basic principles of pass transistor
circuits

Faculty Academic Coordinator Head of the Department

Mid – Quality & Evaluation

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Year: II Semester: II Academic Year:2022-2023

Conduct
Mid Evaluation Entry of HoD’s
Questions of
Exam of Mid Date Marks Review
Test Date
Q1 EXPLAIN THE VHDL STATEMENTS?
a) Process statement
b) IF statement
c) case statement
d) loop statement

Q2what is parallel binary adder? Write

Mid-I VHDL program for parallel binary
adder ?
21-03-2023 27-03-2023 28-03-2023

Q3.What is ripple counter? W x plain

asynchronous up counter and down
counter with clock pulse?

Q1

Q2

Mid-II

Q3

Head of the Department

HOD REVIEW (Fortnightly)

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

S. No. Date of Review Signature of HOD

Details of Internal Quality Audit

Auditee Auditor
S. No. Date of Audit Report of Observations/ Remarks
Signature Signature
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

CONCEPTUAL PLAN
Unit-I: At the end of the session the student is able to
S No Session Concept-1 Cognitive Level Concept - 2 Cognitive Level Mode of Teaching
1 Session 1 Introduction to VHDL Understanding PPT
2 Session 2 entity declaration Understanding PPT
3 Session 3 architecture Understanding Examples PPT
4 Session 4 Data –flow Understanding PPT

5 Session 5 behavioral and structural style of modelling Understanding PPT

s
6 Session 6 Data types Understanding Explanation Remembering PPT
7 Session 7 Data objects Understanding PPT
8 Session 8 Configuration declaration Understanding Chalk & Talk
9 Session 9 Package ,generic, operators and identifiers Understanding Explanation Remembering Chalk & Talk
10 Session 10 PROCE SS,IF, CASE & LOOP statements Understanding Explanation Remembering Chalk & Talk
11 Session 11 VHDL libraries Understanding Chalk & Talk
12 Session 12 Verilog HDL: Introduction to Verilog HDL Understanding Examples PPT
13 Session 13 data types, data operators Understanding Examples PPT
14 Session 14 module statement Understanding PPT
15 Session 15 wire statement Understanding PPT
16 Session 16 if- else statement Understanding Explanation Remembering PPT
17 Session 17 case-end case statement Understanding PPT
18 Session 18 Verilog syntax and semantics(qualitative Understanding Chalk & Talk
approach)
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Unit-II: At the end of the session, the student is able to

S No Session Concept-1 Cognitive Level Concept - 2 Cognitive Level Mode of Teaching
19 Session 19 Parallel binary adder Understanding PPT
20 Session 20 carry look ahead adder Understanding PPT
21 Session 21 BCD adder Understanding Examples PPT
22 Session 22 Multiplexers and de multiplexers and Applying PPT
their use in combinational logic design
23 Session 23 ALU, digital comparators Remembering PPT
24 Session 24 parity generators Remembering Explanation Remembering PPT
25 Session 25 Code converters Applying PPT
26 Session 26 priority encoders Applying PPT
Qualitative approach of designing and Remembering Explanation Remembering Chalk & Talk
27 Session 27 modelling the mentioned
combinational logic circuits with
relevant digital ICs using HDL

Unit-III: At the end of the session, the student is able to

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

S No Session Concept-1 Cognitive Level Concept - 2 Cognitive Level Mode of Teaching

28 Session 28 Registers Understanding PPT
29 Session 29 applications of shift registers Understanding PPT
30 Session 30 ripple or a synchronous counters Remembering PPT
31 Session 31 synchronous counters Applying Explanation Remembering Chalk & Talk
32 Session 32 synchronous and a synchronous sequential Understanding Chalk & Talk
circuits
33 Session 33 hazards in sequential circuits Understanding PPT
Qualitative approach of designing and Remembering Explanation Remembering
modelling the mentioned sequential logic
34 Session 34 circuits with relevant digital ICs using Chalk & Talk
HDL)
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Unit-IV: At the end of the session the student is able to

S No Session Concept-1 Cognitive Level Concept - 2 Cognitive Level Mode of Teaching

35 Session 35 Combinational MOS Logic Circuits: Understanding Chalk & Talk

Introduction
36 Session 36 MOS logic circuits with depletion n MOS Applying PPT
loads: two- input NOR gate
37 Session 37 generalized NOR structure with multiple Understanding PPT
inputs
38 Session 38 transient analysis of NOR gate Understanding Examples PPT
39 Session 39 two-input NAND gate Remembering PPT
40 Session 40 generalized NAND structure with multiple Understanding Chalk & Talk
inputs
41 Session 41 transient analysis of NAND gate Understanding Explanation Remembering Chalk & Talk
42 Session 42 CMOS logic circuits: CMOS NOR2 gate Understanding Chalk & Talk
43 Session 43 CMOS NAND2 gate Understanding Chalk & Talk
44 Session 44 complex logic circuits Remembering Explanation Remembering Chalk & Talk
45 Session 45 complex CMOS logic gates Remembering Explanation Remembering Chalk & Talk
46 Session 46 AOI and OAI gates Understanding PPT
47 Session 47 Pseudo- n MOS gates Understanding Examples PPT
48 Session 48 CMOS full-adder circuit Applying PPT
49 Session 49 CMOS transmission gates (Pass Gates) Remembering PPT
50 Session 50 Complementary pass-transistor logic Understanding

Unit-V: At the end of the session the student is able to

S No Session Concept-1 Cognitive Level Concept - 2 Cognitive Level Mode of Teaching
51 Session 51 Sequential MOS Logic Circuits: Introduction Understanding PPT
52 Session 52 Behavior bi- stable elements Understanding PPT
53 Session 53 SR latch circuit Understanding PPT
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

54 Session 54 clocked latch and flip-flop circuits Applying Examples PPT

55 Session 55 clocked SR latch Understanding PPT
56 Session 56 clocked JK latch Applying PPT
57 Session 57 master-slave flip-flop Applying Explanation Remembering
58 Session 58 CMOS D-latch and Edge- triggered flip-flop Remembering
59 Session 59 Schmitt trigger circuit Understanding
60 Session 60 basic principles of pass transistor circuits Understanding Explanation Remembering

Faculty Academic Coordinator Head of the Department Dean Academics Principal

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Question Bank

Unit-I
Q. No Question CO
Define the following terms relevant to Verilog HDL i) Parameters iii) Constants ii)
1 CO-1
Keywords iv) identifiers
2 What is the use of library clause and use clause? Give example CO-1
Explain the difference in program structure of VHDL and any other procedural
3 language. Give an example CO-1

4 Write a Verilog code for a 4X1 MUX using CASE statement? CO-1
5 Explain various architectural bodies/modeling styles in VHDL with examples CO-1

Unit-II
Q. No Question CO
1 Design a 2 input 4-bit multiplexer. Write the truth table and draw the logic diagram. CO-2
2 Using a process statement write a VHDL source code for 4 to 1 multiplexer. CO-2
3 Write a VHDL code for four bit parallel adder/subtractor CO-2
Design the logic circuit for even parity checker and write the behavioral VHDL
4 CO-2
program?
5 Design a first and second highest priority encoder circuit using 74LS148 and 74LS138? CO-2

Unit-III
Q. No Question CO
Draw the logic diagram for n-bit left to right shift register? Write down the VHDL code
1 CO-3
for an n-bit left to right shift register?
2 List out the applications of shift register? CO-3
3 Give brief note on hazards in sequential circuits? CO-3
4 List the basic types of shift registers in terms of data movement with diagrams? CO-3
Explain the operation of a 4 bit synchronous binary counter with the required diagram CO-3
5 and waveforms.
UNIT-IV
Q. No Question CO
How does a transmission gate work? Explain four different representations of the CMOS
1 CO-4
transmission gate (TG). Design 2X1 MUX using it?
2 Draw and explain the CMOS Half adder? CO-4
3 With neat schematic explain D latch using CMOS Inverter and Transmission gate? CO-4
Draw the logic diagram and truth table of a CMOS clocked SR flip-flop and explain its CO-4
4
operation?
Design an area efficient layout diagram for the CMOS logic shown below CO-4
5
Y = (A + B + C) 1

UNIT-V
Q. No Question CO
1 Design and Explain the operation of CMOS clocked JK flip-flop CO-5
2 List out the comparisons between latch and flip flop. CO-5
List out the differences between regenerative logic circuits and non-regenerative logic CO-5
3
circuits
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Draw different styles of D-FlipFlops using CMOS and transmission gates and explain CO-5
4
any one?
5 Design Schmitt trigger using CMOS and explain its operation? CO-5

Faculty Academic Coordinator Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

Assignment-1

Q. No Question CO Blooms
Level
Taxonomy level
Explain various architectural bodies/modeling
1 CO-1 L1
styles in VHDL with examples
Design the logic circuit for even parity checker
2 CO-2 L3
and write the behavioral VHDL program?
Draw the logic diagram for n-bit left to right
3 shift register? Write down the VHDL code for CO-3 L4
an n-bit left to right shift register?

Assignment-2

Q. No Question CO Blooms
Level
Taxonomy level
Give brief note on hazards in sequential
1 CO-3 L4
circuits?
2 Draw and explain the CMOS Half adder? CO-4 L1
List out the comparisons between latch and flip CO-5
3 L1
flop.

Faculty Academic Coordinator Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

SCHEME OF VALUATION FOR INTERNAL EXAM QUESTION PAPER

YEAR:II
Mid
Questions Scheme of valuation
Exam
Q1 Explain the VHDL statements? Concept-3M
a) Process statement b) IF statement
Diagram-2M
c) case statement d) loop statement

Q2what is parallel binary adder? Write Concept-2M

VHDL program for parallel binary adder
Diagram-1M
Mid-I
Equations-2

Q3.What is ripple counter? W x plain Concept-2M

asynchronous up counter and down
Diagram-1M
counter with clock pulse
Equations-2M

Concept-3M

Diagram-2M

Concept-2M
Mid-II
Diagram-1M

Equations-2

Concept-2M

Diagram-1M

Equations-2M

Head of the Department

 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

INTERNAL EXAM MARKS SHEET

AC- R2032042
HALL TICKET
S.NO NO. MID-1 Q1 A1 MID-2 Q2 A2

1 21GK1A0401

2 21GK1A0402

3 21GK1A0403

4 21GK1A0404

5 21GK1A0405

6 21GK1A0406

7 21GK1A0407

8 21GK1A0408

9 21GK1A0410

10 21GK1A0411

11 22GK5A0401

12 22GK5A0402

13 22GK5A0403

14 22GK5A0404

15 22GK5A0405
 A. Y. :2022-23
Name of the Course
YS. : III Sem :II

UNIVERCITY EXAM RESULTS

UNIVERCITY EXAM RESULTS

TOTAL NUMBER OF STUDENTS

NUMBER OF STUDENTS ABSENT
NUMBER OF STUDENTS PRESENT
NUMBER OF STUDENTS PASSED
PASS PERCENTAGE

SUBJECT MP&MC VLSI DSP M&CM FUEE MP&MC VLSI DSP AB&
LAB LAB LAB ABP
TOTAL NUMBER OF STUDENTS
NUMBER OF STUDENTS ABSENT
NUMBER OF STUDENTS PRESENT
NUMBER OF STUDENTS PASSED
PASS PERCENTAGE