Chapter Five

MAIN MEMORY SYSTEM DESIGN

Memory that interfaces directly to the microprocessor is referred to as main memory. It

has the following characteristics:

1. Any location can be accessed at random.

2. Each byte has its own unique address.
3. Data is read or written in one CPU bus cycle.

Devices like floppy-disk drive are referred to as secondary storage device. The data from
secondary storage device is read byte by byte from the sane (I/O port) address.thi s means
that to the CPU, each byte of data on the disk appears to be stored at the same address.

5.1 TYPES OF MAIN MEMORY

There are four common types of main memory

Mask-programmable read–only–memory (ROM) It is programmed at the factory

according to a truth table supplied by the user. In this way the manufacturer can sell the
same ROM chip to many different customers, altering only the mask that defines the
diode connections.

Field-programmable ROMs There are several types of ROMs that can be programmed
by the user in the field. These devices are referred to as programmable read-only
memories (PROMs).

Fusible-link PROMs one type PROM uses a low current fusible link in series with the
output. By applying a current pulse to the desired output, the fuse can be melted and a
logic 1 or 0 permanently programmed. A typical application would be a “boot” PROM in
microcomputer system.

UV–light-erasable PROMs (EPROMs) The most popular types of PROM used in

microcomputer systems is the erasable programmable read-only memory (EPROM). This
device can be programmed, erased, and reprogrammed many times over by the user.

EPROMs use a floating-gate avalanche injection MOS (FAMOS) transistor cell to store
charge. Applying a special programming voltage (Vpp) causes a high electric field to be
developed in the channel region of the transistor. This in turn causes electrons to jump the
silicon dioxide barrier between the channel region and the floating gate.

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During programming the select gate is given a positive bias which helps attract these
electrons to the floating-gate electrode. Because the floating gate is surrounded by silicon
dioxide (an excellent insulator), the injected charge is effectively trapped.

Cells with trapped charge cause the transistor to be biased ON, where as those cells
without trapped charge are biased OFF. Blank EPROMs have no charge and each cell
stores a logic 1. The EPROM can be erased by subjecting each to ultraviolet (UV) light,
which has a wave length of 2537 angstroms. The electrons on the floating gate absorb
photons from the UV-light source and acquire enough energy to reverse the programming
process and return to the substrate.

EPROMs are packaged in special ceramic packages with quartz windows to allow
erasure. In operation the EPROM window should be covered with an opaque label
because normal room fluorescent lighting could erase the device.

Electrically erasable PROMs (EEPROMs)

There are several disadvantages to the UV EPROM. These are:

1. The device must be removed from the circuit board to be erased.

2. Byte erasure is not possible; all cells are erased when exposed to UV light.
3. The quartz window package is expensive.

Because of these problems the EEPROM is developed. This device can be programmed
and erased without removing the chip from its socket. In addition, both byte and bulk
erasure modes are possible.

Some applications of EEPROM are , although it will not replace conventional RAM, it
can be used to hold programs and data that are that are subject to frequent changes: for
example, inventory records, set points for NC (numerical controlled) machine tools, and
motion paths for industrial robots.

A particular interesting application of the EEPROM is programming via a remote data

link. Using a telephone interface called a modem; the central factory can call up the
EEPROM field system and transfer new data or modify the system software.

Static and dynamic RAMs Two types of semiconductor RAM are popular. In static
RAM four to six transistors are connected to form a simple RS flip-flop. In a static RAM,
data, once entered, remain valid as long as the power supply is not turned off.

On the other hand, to retain data in a DRAM, in addition to power supply, a periodic
refreshing with in specific interval of time is required, because the elements are made of
capacitive. Because of the refresh and address multiplexing requirements, interfacing a

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DRAM to a microprocessor is more complex than SARM interface. However, DRAM
controller chips are available to simplify this task.

5.2 INTERFACING MEMORY

The one basic characteristic of all 8086 memory designs is the requirement to partition
the memory in to two banks. One bank stores the even-addressed bytes and the other the
 control signal must be used in the
odd-addressed bytes. The A0 address line and BHE
memory interface to select the appropriate bank as required by the current CPU
instruction.

Pin connections common to all memory devices are

- The address inputs

- Data outputs or input/ outputs.
- ) and
Some type of selection input (chip select CS
- -output
At least one control input used to select a read or write operation (OE
enabled; 
WE-write enabled)

Figure 5.1 pin description common to all memory

Address connections All memory devices have address inputs that select a memory
location within the memory device. A 2K memory device has 11 address pins (A0-A10);
therefore, 11 address inputs are required to select any of its 2048 (2K) internal memory
locations. The remaining nine address pins (A19–A11) are connected to the inputs of a
decoder. The decoder selects the memory from the many 2KB sections of the entire 1MB
address range of the microprocessor.

Data connections Data connections are the points at which data are entered for storage or
extracted for reading. Most devices are 8-bits (a byte) wide memory.

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Chip select (  input is active
) Chip select Selects or enables the memory device. If CS
(a logic 0), the memory device performs a read or write operation; if it is inactive (a
logic-1) the memory device cannot perform a read or write operation because it is turned
off or disabled.

Figure 5.2 Interfacing 8k-byte memory to the 8086 CPU.

Control connection A ROM usually has only one control input, output enabled (OE )
connection, which allows data to flow out of the output data pins of the ROM. A RAM
memory device has either one or two control inputs:

i) R/W  or
ii) WE and 
 OE (write and output enabled)

) and write enabled (WE

If a memory write or read cycle is to occur, the chip select (!" ,
R/W  or R/W
 = 0) or output enabled (OE  = 1) are active. Figure 5.2 shows that two ships
are required. One stores the even bytes and connects to DB0–DB7. The other stores the
odd bytes and connects to DB8–DB15.

A13-address lines are required to access all of the 8K-bytes. AB1–AB13 address lines are
connected to the memory chip address lines A0–A12. You must remember that AB0 and

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 are required to select the appropriate bank. Thus the interface provides a total of
BHE
16Kbytes of memory.

The memory idles with all data pins open-circuited until the 
CS input is taken low. When

CS is low, a read cycle will occur provided that WE is high (disabled) and 
 OE is low (then
used to enable the output buffers).

For even byte transfer only AB0 will be low and memory-A is selected. For odd byte
transfer memory-b will be selected and  WE and 
BHEB only will be low. Note that  OE are
   
driven by MEMW and MEMR which are generated from BHE, WR, and A0 pins of the
microprocessor as shown in the figure below.


BHE  (MEMW
HWR )

WR

AO  (MEMW
LWR )

Figure 5.3 The memory bank write selection input signal:

 (MEMW
HWR ) high bank write

 ) low bank write

LWR (MEMW

The address decoder must decode the unused address lines AB0–AB19. Figure below
shows one possibility. This circuit forces the unused address lines to be 111111B and
maps the circuit to the range FC000 – FFFFFH

AB14
AB15
AB16 
MEMORY SELECT
AB17
AB18 This line is low for any address
AB19 between FC000 - FFFFFH

Figure 5.4 simple address decoding technique.

This address decoder causes the memory interface to reside in the 16k-byte range FC000
– FFFFFH.

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5.3 ADDRESS DECODING TECHNIQUES

The 8086 microprocessor provides a 20 bit memory address that allows up to 1MB of
main memory. Most memory interface, however, do not fill this entire range. This means
that for a given memory design, several of the address lines are going to be “unused”.
However, these unused lines are very important because they determine the range of the
address the memory interface will occupy.

An address decoder is a circuit that examines these extra address lines and enables the
memory for a special range of addresses. This is an important part of any memory design,
as one block of memory must not be allowed to overlap another. The decoder ranges
from simple NAND gates to programmable array logic (PAL) devices.

5.3.1 THE 3-TO-8 LINE DECODER (74LS138)

One of the most common although not only, integrated circuit decoders found in many
microprocessor-based systems is the 3-to-8 line decoder shown below.

Figure 5.5 pin description of 3-to-8 line decoder.

For any of the decoder’s output to go low, the three enable inputs (G2A, G2B, and G1)
must all be active. To be active the G2A and G2B inputs must both be low (logic 0) and
G1 must be high (logic 1). Once the decoder is enabled the address inputs (A, B, and C)
select which output pin should goes low. Only one of the eight outputs ever goes low at
any time. Eight memory devices !"  inputs can be connected to the eight outputs of the
decoder at the same time. That is why it is called a very powerful device because it
selects eight different memory devices at the same time.

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 Figure 5.6 the 74LS138 3-to-8 line decoder connected to memory
The 74LS138 3-to-8 line decoder can be used to provide eight consecutive memory-block
select signals. A 256 KB memory array is shown in the figure 5.6. It consists of four
64Kbyte blocks of memory and a 74LS138, 3 to 8 line decoder. The low order address
lines AB1–AB16 select one of 64KB in each memory bank.

The decoder allows only one bank to be enabled at a time. Example output 0 will be
active when the enable inputs are active and A17–A19 are 000. This corresponds to the
address range 00000H – 1FFFFH.

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