CND 121

Design Project Project #1

Introduction to Silicon Process and VLSI

Title: VLSI flow for logic circuits.

Supervisor: Dr Hatem Yousry, Dr Ahmed Saeed
In this project, you will go through the whole digital VLSI flow including the schematic entry,
symbol creation, building the test design, creating the layout view, checking DRC, LVS
verification, parasitic extraction, and post-layout simulation. The topic of this project is to design
one of the following:

a. 2-bit Multiplier.
b. 2-bit Comparator.
c. 1-Bit simple ALU.

The design style should be fully static CMOS, dynamic, or pseudo-NMOS. You are allowed to
use pass transistor logic internally in the cell only if the outputs are buffered. Research and
decide on the architectures you will implement. The textbook includes a chapter on this worth
reading. In addition, reviewing IEEE XPLORE papers is also a good idea. The report must
justify the design decisions and provide all the vital information. In addition, you should discuss
your overall design philosophy and the important design decisions you made. The report should
be based on the following outlay:
— Initial design
— Capture the design as a schematic
— Create a symbol of your design
— Create a testbench circuit
— Simulate your design to verify operation
— Layout a cell for this design
— Check for layout rule violations (DRC)
— Check layout against schematic (LVS)
— Verify circuit operation.
— Extract parasitics and back annotate
— Re-simulate

Assessment Criteria:
— Circuit design and flow steps --- 60%
— Functionality --- 20%
— Design metrics (Area, Power, Delay) evaluation --- 20%
— Bonus: Advanced design considerations (Non-CMOS structure, low-power techniques,
… ) --- 15%
Best of Luck!

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 CND 121
Design Project Project #2
Introduction to Silicon Process and VLSI

Title: Automatic Transistor Sizing for combinational CMOS logic circuits.

Supervisor: Dr Mohamed Saleh

Description: The purpose of this project is to:

1. Implement a software algorithm (preferably using python) to identify transistor sizes in CMOS
combinational logic circuits. The transistor sizes should be selected in a way that meets minimum
area, makes t = t , and achieve minimum delay.
pHL pLH

2. Verify your algorithm over the following logic circuits:

1. Output = (A+B) CD
2. 4 Input NAND Gate.
3. Provide simulation results of your algorithm and verify them using truth tables.
4. Implement the corresponding Layout for the previous two Gates and verify them using DRC and
LVS.
Requirements:
1. Python (you can use Anaconda platform) or any other language.
2. Read on linear programming or/and unsupervised machine learning.
3. Understanding CMOS combinational logic circuits.
4. Circuit Simulator, Layout Editor, DRC, and LVS.
Assessment Criteria:
The metric to achieve the highest grades:
1. Providing a working python code.
2. Getting correct logic results.
3. Passing DRC and LVS.
4. Achieving t = t
pHL pLH

5. Achieving minimum delay2*layout Area.

Best of Luck!

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 CND 121
Design Project Project #3
Introduction to Silicon Process and VLSI

Title: Design of bandgap passive filter

Supervisor: Dr Mourad Elsobky

Description: we are facing an issue in the project in which the thermal noise of the on-chip
bandgap reference (nominal 1.2V) is out of spec, especially at a critical frequency of 25kHz. for
a quick fix, one idea is to filter this reference voltage noise using a 1st order passive RC filter.
Note, no current is being sourced or sinked by the bandgap reference from any other block in the
system.

Requirements:
Assumptions:
• reference voltage spot noise before filtering: 1µV/sqrtHz flat across all frequencies
• In this technology,
o CMOS 5M layers
o ppoly sheet resistance is 600 ohm/square, npoly sheet resistance is 200 ohm/square
o minimum poly spacing is 250nm, minimum poly width is 420nm

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 o cap isa uniform interdigitated metal oxide metal (MOM) structures and its density
is 1fF/µm /layer
2

o minimum distance inter-metal and intra-metal is 90nm, minimum metal width is

90nm
- specs
reference voltage noise after RC filter at 25kHz must be less than 0.25µV/sqrtHz (factor 4x less)
- design
Design the passive 1st order RC filter in order to have attenuation of input signals of ¼ at 25kHz.
After deciding the proper R and C values, implement them using
R 🡪 poly resistors
C 🡪 MOM capacitors
- schematic
Create a schematic “bg_rc_filt” with one input and one output pin
Create the corresponding testbench “tb_bg_rc_filt”

- simulation
Simulate the tb using ac analysis to show the transfer function of the filter.
Simulate the tb using noise analysis using an ideal noiseless voltage source in the input. Note, when using
resistors from analogLib, activate the generate noise option in the res properties.
What is the noise at 1Hz, 25kHz and 1MHz of the RC filter alone? What is the total noise at 25kHz (noise
of reference noise before filter + noise of filter itself)
- layout
Create layout view of “bg_rc_filt”
Create the resistor layout and capacitor layout that achieves the smallest area while keeping the specs.
Suggest 2-3 options for evaluation if you are not sure.
- LVS
- DRC
- back annotation
Bonus: extract the layout parasitics and rerun the testbench. Why the low pass filter corner freq. and noise
values changes?

Best of Luck!

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 CND 121
Design Project Project #4
Introduction to Silicon Process and VLSI

Title: Design delay locked loop (DLL)

Supervisor: Dr Mourad Elsobky

Description: choose the simplest DLL architecture of your choice.

Razavi:
The Delay-Locked Loop [A Circuit for All Seasons]
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8447468

Requirements:
- specs
Use an input reference clock of 100MHz, the output clock phase delay can be adjusted by 20%.
- design
Design a voltage-controlled delay line (VCDL), other components can be simply modeled like phase
detector (PD) or charge pump (CP)
- schematic
Make a separate schematic for the VCDL in open loop and determine the relation between its control input
and output delay.
- simulation
Tran. And or pss simulations are essential
- layout
Make a layout of the VCDL
- LVS
- DRC
- back annotation
Recognize and document the difference between schematic and post layout simulations.

Assessment Criteria: most complete designs including all DLL components in compact layout get the
highest points.
Best of Luck!

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 CND 121
Design Project Project #5
Introduction to Silicon Process and VLSI

Title: Design of 4-bit Full Adder

Supervisor: Prof. Magdy Elmorsy

Description: The aim of this project is to design 4-bit Full Adder using different
techniques (Ripple Carry, Carry LookAhead)

Requirements:
1- Student should build the design with all its abstraction layers RTL, Schematic, and
Layout.
2- Student should use simulation tools to validate the functionality of the design.
3- Student should go through all design steps and being able to evaluate the design
performance.
4- Student should report the design Area, Delay, and Power Dissipation.

Assessment Criteria:
1- Was the design validated to work correctly or not?
2- Were the abstraction layers of the design (RTL, Schematic, and Layout) validated to be
identical or not?
3- Was the performance of the design evaluated from all aspects (Area, Delay, and Power
Dissipation)?

Best of Luck!

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 CND 121
Design Project Project #6
Introduction to Silicon Process and VLSI

Title: Design two 4-bit adders

Supervisor: Prof. Mohamed Sowailm, Dr. Esraa Sowailm

1. Description:
The topic of this project is to design two 4-bit adders with two different architectures and
compare between them. It means that you have to realize the following equations for each
of the full adder cells. The primary goal of the project is to minimize the worst case
propagation delays of the sum and the carry generation. The secondary objective is to
minimize the area and average power consumption. The faster, smaller, and more power-
efficient your circuit, the better is your grade.

2. Specifications.
The full adders cell should fulfill the following specifications:
Research and decide on the adders architectures they will implement. The text book includes
a chapter on this worth reading. In addition, reviewing IEEE XPLORE papers is also a good
idea.
The design style must be fully static CMOS (i.e. no dynamic, pseudo-NMOS). You are
allowed to use pass transistor logic internally in the cell only if the outputs are buffered.
This means that each output needs to have “full driving capability”.

Inputs: To mimic real-life environments, it is assumed that inputs A, B, Cin come from a
minimum size inverter. Those minimum size invertors are driven by ideal voltage sources.
The ideal voltage sources have a rise and fall times of 10ps.

Delays: Optimize for the worst case propagation delay, tpHL or tpLH for both the sum and
the carry output. You have to determine which are the worst-case propagation delays. Justify
in your report.

NOISE MARGINS: You are free to choose your logic swing. The noise margins should be
at least 10% of the voltage swing. Test this by computing the VTC between one of the inputs
and the output signals (with the other inputs set to the appropriate values) for a static design.

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3. Simulation
You should verify your design by running Hspice on the circuit. Measure the propagation
delay for the worst case transition and measure total energy consumed by your circuit.
Create the layout of the design, make sure it passes DRC and LVS Run parasitic extraction
and backannotate the results Assess and compare the delay and area of the 2 designed
adders.

4. Report and Presentation

The report must justify the design decisions and provide all the vital information. In
addition, you should discuss your overall design philosophy and the important design
decisions you made. Include schematics, and the resulting SPICE and layout outputs. Prove
that your alleged results are TRUE by providing the crucial plots (don't forget to mention
the input patterns you used to obtain those plots).

The report should be based on the following outlay:

- Abstract, Logic Diagram, Remarks and motivations
- Transistor diagram - annotated with transistor sizes and worst-case timing path.
- Plot showing the functional operation of the cell. Comments.
- Timing simulation - derive value of worst-case path - comments on the optimizations.
- Layout with area and physical verification results

GRADING
- The quality of the report is an important part of the project grade!
- The grade will be divided as follows:
o 40% Result + Correctness
o 20% Creativity of Approach
o 30% Report Quality
o 10% Presentation Quality

Best of Luck!

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