Practical -1:

AIM: Implement Booth’s Algorithm

ANS:

Booth algorithms give a procedure for multiplying binary integers in signed 2’s
complement representation in efficient way, i.e., less number of additions/subtractions
required. It operates on the fact that strings of 0’s in the multiplier require no addition
but just shifting and a string of 1’s in the multiplier from bit weight 2^k to weight 2^m
can be treated as 2^(k+1 ) to 2^m. As in all multiplication schemes, booth algorithm
requires examination of the multiplier bits and shifting of the partial product. Prior to
the shifting, the multiplicand may be added to the partial product, subtracted from the
partial product, or left unchanged according to following rules:

1. The multiplicand is subtracted from the partial product upon encountering the
first least significant 1 in a string of 1’s in the multiplier

2. The multiplicand is added to the partial product upon encountering the first 0
(provided that there was a previous ‘1’) in a string of 0’s in the multiplier.

3. The partial product does not change when the multiplier bit is identical to the
previous multiplier bit.

Hardware Implementation of Booths Algorithm – The hardware implementation

of the booth algorithm requires the register configuration shown in the figure below.

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 Booth’s Algorithm Flowchart –

We name the register as A, B and Q, AC, BR and QR respectively. Qn designates the least
significant bit of multiplier in the register QR. An extra flip-flop Qn+1is appended to
QR to facilitate a double inspection of the multiplier.The flowchart for the booth
algorithm is shown below.

AC and the appended bit Qn+1 are initially cleared to 0 and the sequence SC is set to
a number n equal to the number of bits in the multiplier. The two bits of the multiplier
in Qn and Qn+1are inspected. If the two bits are equal to 10, it means that the first 1
in a string has been encountered. This requires subtraction of the multiplicand from
the partial product in AC. If the 2 bits are equal to 01, it means that the first 0 in a
string of 0’s has been encountered. This requires the addition of the multiplicand to
the partial product in AC. When the two bits are equal, the partial product does not
change. An overflow cannot occur because the addition and subtraction of the
multiplicand follow each other. As a consequence, the 2 numbers that are added
always have a opposite signs, a condition that excludes an overflow. The next step is
to shift right the partial product and the multiplier (including Qn+1). This is an
arithmetic shift right (ashr) operation which AC and QR to the right and leaves the
sign bit in AC unchanged. The sequence counter is decremented and the
computational loop is repeated n times. Product of negative numbers is important,
while multiplying negative numbers we need to find 2’s complement of the number to
change its sign, because it’s easier to add instead of performing binary subtraction.
product of two negative number is demonstrated below along with 2’s complement.

Example – A numerical example of booth’s algorithm is shown below for n = 4. It

shows the step by step multiplication of -5 and -7.

BR = -5 = 1011,
BR' = 0100, <-- 1's Complement (change the values 0 to 1 and 1 to 0)
BR'+1 = 0101 <-- 2's Complement (add 1 to the Binary value obtained after 1's
complement)

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HARSH VAGADIYA (220470107180)
QR = -7 = 1001 <-- 2's Complement of 0111 (7 = 0111 in Binary)
The explanation of first step is as follows: Qn+1
AC = 0000, QR = 1001, Qn+1 = 0, SC = 4
Qn Qn+1 = 10
So, we do AC + (BR)'+1, which gives AC = 0101
On right shifting AC and QR, we get
AC = 0010, QR = 1100 and Qn+1 = 1
OPERATION AC QR Q SC
(n+1)
0000 1001 0 4
AC+BR’+1 0101 1001 0
ASHR 0010 1100 1 3
AC+BR 1101 1100 1
ASHR 1110 1110 0 2
ASHR 1111 0111 0 1
AC+BR’+1 0100 0111 0
ASHR 0010 0011 1 0

Product is calculated as follows:

Product = AC QR
Product = 0010 0011 = 35

117.

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HARSH VAGADIYA (220470107180)
 Practical -2

AIM: Write the working of 8085 simulator GNUsim8085 and basic

architecture of 8085 along with small introduction.
Introduction to 8085 Microprocessor:

The 8085 is an 8-bit microprocessor introduced by Intel in 1976. It became very popular
due to its ease of use and versatility. The 8085 has a 16-bit address bus and can address
up to 64 KB of memory. It has a 8-bit data bus, which means it can process 8 bits of data
at a time. The architecture of the 8085 consists of various registers, an arithmetic logic
unit (ALU), control unit, and a set of instructions.

Basic Architecture of 8085:

1. Registers: The 8085 has six general-purpose registers, labeled B, C, D, E, H, and L.

These registers can be paired to form three 16-bit register pairs: BC, DE, and HL.
It also has a 16-bit stack pointer (SP) and a 16-bit program counter (PC).
Additionally, there is an 8-bit accumulator (A) which is used for arithmetic and
logic operations.

2. Arithmetic Logic Unit (ALU): The ALU performs arithmetic and logic operations
on data. It can perform operations like addition, subtraction, logical AND, logical
OR, etc.

3. Control Unit: The control unit controls the flow of data and instructions within
the microprocessor. It generates control signals to coordinate the operations of
other units.

4. Memory: The 8085 can address up to 64 KB of memory using its 16-bit address
bus. It uses separate address and data buses (multiplexed address/data bus).

5. Instruction Set: The 8085 has a rich set of instructions, including arithmetic,
logical, branching, and data transfer instructions. Instructions are encoded as 8-
bit binary codes.

Working of GNUSim8085 Simulator:

GNUSim8085 is a graphical simulator, debugger, and assembler for the 8085

microprocessor. It allows you to write 8085 assembly language programs and simulate
their execution on a virtual 8085 microprocessor.

1. Writing Programs: You can write 8085 assembly language programs using the
built-in editor or any text editor. Each line of code represents an instruction or a
label.

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 2. Assembling: After writing the program, you need to assemble it using the built-in
assembler. The assembler converts the assembly language code into machine code
(hexadecimal).

3. Simulating: Once the program is assembled, you can start the simulation. The
simulator will execute the instructions step by step, showing the state of the
registers and memory at each step. You can observe how the program modifies the
data and control flow.

4. Debugging: GNUSim8085 provides debugging features like breakpoints, single-

stepping, and viewing the contents of registers and memory. This helps in
understanding the program's behavior and identifying any errors.

5. Visualization: The simulator provides visual representations of the 8085

architecture, making it easier to understand how data flows through the various
units of the microprocessor.

Overall, GNUSim8085 is a valuable tool for learning and experimenting with 8085
assembly language programming, helping users understand the fundamentals of
microprocessor operation.

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 Practical-3

AIM: Write an assembly language code in GNUsim8085 to store numbers in

reverse order in memory location.
code output
lxi h,var1
lxi d,varr5

back: mov a,m

inx h
stax d
dcx d
dcr c
jnz back
hlt

var1: db 03h
var2: db 05h
var3: db 07h
var4: db 08h
var5: db 09h

varr1: db 00h
varr2: db 00h
varr3: db 00h
varr4: db00h
varr5: db 00h

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 Practical-4

AIM: Write an assembly language code in GNUsim8085 to implement

arithmetic instruction.
code output

LXI H, 0000H
MOV A, M
INX H
ADD M
INX H
MOV M, A
HLT

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 Practical-5

AIM:Write an assembly language code in GNUsim8085 to find the factorial of

a number.
MVI B,04

MOV C, B

DCR C

LABEL2: MOV E, C

SUB A

LABEL1: ADD B

DCR E

JNZ LABEL1

MOV B, A

DCR C

JNZ LABEL2

STA 00H

HLT

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 Practical-6

AIM:Write an assembly language code in GNUsim8085 to implement logical

instructions.
OR :

Lda0001;
Mov b,a;
Lda0003;
ORA b;
Sta 0005;
Hlt;

AND:

Lda0001;
Mov b,a;
Lda0003;
ANA b;
Sta 0005;
Hlt;

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XOR:

Lda0001;
Mov b,a;
Lda0003;
XRA b;
Sta 0005;
Hlt;

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 Practical-7

AIM:Design ALU using Logisim.

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 Practical-8

AIM:Implement 16-bit single-cycle MIPS processor in Verilog HDL

Designing a 16-bit single-cycle MIPS processor in Verilog HDL involves several steps, each
representing different components of the processor. Here's a high-level overview of how
you might approach this:

1. Instruction Fetch (IF) Stage:

• Implement an instruction memory module to store instructions.

• Fetch instructions from memory based on the program counter (PC) value.

• Decode the fetched instruction to determine the opcode and other relevant
information.

2. Instruction Decode (ID) Stage:

• Decode the fetched instruction to determine the operation to be performed.

• Read register values from the register file based on register addresses
provided by the instruction.

3. Execution (EX) Stage:

• Perform arithmetic or logical operations based on the decoded instruction.

• Calculate memory addresses for load and store instructions.

• Calculate branch target addresses and determine whether to take the

branch.

4. Memory Access (MEM) Stage:

• For load instructions, read data from memory based on the calculated
memory address.

• For store instructions, write data to memory at the calculated memory

address.

• For branch instructions, handle branch resolution.

5. Write Back (WB) Stage:

• Write the result of the ALU operation back to the register file if required.

• Update the PC with the next instruction address.

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Each of these stages will be implemented as separate modules in Verilog HDL.
Additionally, you'll need to design modules for the register file, ALU (Arithmetic Logic
Unit), control unit, and other necessary components.

Here are some key considerations for designing each stage:

• Ensure proper data and control flow between stages.

• Implement appropriate control signals to manage the execution of instructions.

• Handle data hazards, control hazards, and structural hazards.

• Optimize for performance and resource utilization.

Once each stage and component has been designed and implemented in Verilog HDL, they
can be interconnected to form the complete 16-bit single-cycle MIPS processor. Testing
and verification are crucial at each step to ensure the correctness and functionality of the
processor design.

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HARSH VAGADIYA (220470107180)