Vipcat11 30 081

VIP Catalog Release Information
Product Version 11.3

February 2022
Document Last Updated: February 15, 2022

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Table of Contents
Contents
1 7
Preface 7
1.1 Terminology 7
1.2 Documentation 8
1.3 Customer Support 8
1.4 Training Videos 9
2 10
Release Information 10
2.1 Verification IP Catalog 10
2.2 Introduction to Virtual Protocols 11
2.2.1 Introduction to Virtual Protocols for Palladium and Protium 11
2.3 Using Save and Restore 14
2.3.1 Questa 15
2.3.2 VCS 15
2.3.3 Xcelium 15
2.4 Verification IP Compatibility and Dependencies 15
2.4.1 Supported Simulators 15
2.4.2 Compatibility with Other Products 16
2.4.3 UVM and Simulator Support 16
2.4.4 UVM and OVM 16
2.4.5 vr_ad Package 17
2.4.6 Accelerated VIP 18
2.5 VIP Catalog Platform Support 19
2.5.1 Platform Support Update 19
2.6 Viewing Documentation with the Cadence Help Tool 19
2.7 Deprecation Notices 20
2.7.1 Recently Deprecated VIPs 21
3 22
New in This VIPCAT Release 22
3.1 New Products 22
3.2 Update on Licensing 23
3.3 New in Memory Models 23
February 2022 3 Product Version 11.3

Table of Contents
3.4 New in Simulation VIP 25

3.5 New in Virtual Protocols 29
3.6 New in Accelerated VIP 30
3.7 New in Assertion-Based VIP 30
4 31
Known Problems and Solutions 31
4.1 VIRTUALBRIDGE 31
4.2 XRUN 32
4.3 AVIP_USB4 32
4.4 AVIP-DisplayPort 32
4.5 AVIP-HDMI 32
4.6 VIP-CAN 33
4.7 VIP-DOCS 34
4.8 VIP-USB 34
5 35
Limitations and Workarounds 35
5.1 Catalog-Wide Limitations 35
5.1.1 VCS Memory Leak with libcdnsv.so 36
5.1.2 Licensing 36
5.1.3 Accessing Memory in a UVM or OVM SystemVerilog Environment 36
5.1.4 UVM and OVM 37
5.1.5 User Interface 38
5.1.6 Compilation with irun 39
5.1.7 SystemVerilog 39
5.1.8 Heap Memory 40
5.2 Simulation VIP Limitations 41
5.2.1 AMBA AXI 41
5.2.2 DisplayPort 42
5.2.3 HDMI 42
5.2.4 I2C 42
5.2.5 Interconnect Validator 42
5.2.6 JTAG 42
5.2.7 LIN 43
5.2.8 MIPI PHY 43
5.2.9 MIPI SLIMbus 43
5.2.10 OCP 44

Table of Contents
5.2.11 PCIE 44
5.2.12 SAS 44
5.2.13 USB 45
5.3 Accelerated VIP (AVIP) Limitations 45
5.3.1 Bug Fixes 45
5.3.2 Known Limitations 45
5.4 Assertion-Based VIP (ABVIP) Limitations 51
5.4.0.1 ACE5 ABVIP 51
5.4.0.2 CHI-E-SYS ABVIP 51
5.4.0.3 DDR5 ABVIP 51
5.4.0.4 I2C ABVIP 51
5.4.0.5 OCP ABVIP 51
5.4.0.6 CHI and CHI-D ABVIP 51
5.4.0.7 CHI-D SYS ABVIP 52
5.4.0.8 CHI-E ABVIP 52
5.4.0.9 CHI-D and CHI-E ABVIP 52
5.4.0.10 SPI ABVIP 52
6 53
Fixed Issues in this Release 53
6.1 List of Defects (since VIPCAT release 11.30.080) 53
6.1.1 AMBA 53
6.1.2 BLE 53
6.1.3 CXL 54
6.1.4 DFI 55
6.1.6 DOCS 55
6.1.7 HDL-DH 56
6.1.8 MIPI 56
6.1.9 MMAV 59
6.1.10 PCIe 60
6.1.11 USB 64
6.1.12 USB4 64
6.2 List of Enhancements (since VIPCAT release 11.30.080) 65
6.2.1 AMBA 65
6.2.2 BLE 65
6.2.3 CXL 66

Table of Contents
6.2.4 DFI 66
6.2.6 HDL-DH 67
6.2.7 MIPI 67
6.2.8 MMAV 68
6.2.9 PCIE 71
6.2.10 PIPEPHY 73
6.2.11 USB 74
6.2.12 USB4 74

Preface
Preface
This document provides Cadence® Verification IP Catalog (VIPCAT) release information including
new products and features, dependencies, licensing, limitations, and fixed issues when moving
from one VIPCAT release to a newer VIPCAT release.
See the following sections for detailed information:
Release Information
New in this VIPCAT Release
Limitations and Workarounds
Known Problems and Solutions
Fixed Issues in this Release
This preface contains the following topics:
Terminology
Documentation
Customer Support
Training Videos
1.1 Terminology
Included below is a set of definitions of terms used throughout this document.
$CDN_VIP_ROOT An environment variable that contains the path to the root directory of the
VIPCAT release installation.
$DENALI An environment variable that points to $CDN_VIP_ROOT/tools/denali.
Bus Functional Verification software that emulates a given device or protocol.

Model (BFM)

Preface--1.2 D ocumentation
Data-Driven The Data-Driven Verification API (DDVAPI) is an extension to the

Verification API Verification IP software. The DDVAPI can be used to integrate
(DDVAPI) applications within the simulation process. For further information, see
Verification IP.
Design Under Test This is the device being verified.

(DUT)/Design
Under Verification
PureView PureView is a graphical user interface (GUI) used to configure the VIP
products. It facilitates the creation of Specification of Model Architecture
(SOMA) files and the generation of HDL instantiation interfaces.
HDL Instantiation An instantiation interface is an HDL design unit that you use to instantiate
Interface a VIP model and connect it to the rest of your design. The instantiation
interface identifies the model type (AXI, USB, etc.), provides parameters
for configuring the instance, and defines ports for connecting the instance
to the signal networks in the design.
SOMA Specification of Model Architecture. SOMA is a Cadence-standard format

to parameterize the model for user-specific verification needs. For further
information, see VIP Configuration and Run-Time Control.
1.2 Documentation
Verification IP (VIP) documentation is available online. Click https://support.cadence.com/vip
You can also download the VIP Catalog documentation library from
https://downloads.cadence.com. For more information, see VIP Catalog Download and Installation.
1.3 Customer Support

The Cadence VIP Catalog is supported by Cadence Global Customer Support. Customers with a
maintenance contract with Cadence can obtain current information on the tools at the following web
site: http://support.cadence.com or e-mail support@cadence.com.
The Cadence Online Support provides access to advanced use training for selected protocols,
expanded collateral such as Application Notes and Rapid Adoption Kits (RAKs), and product
documentation.

Preface--1.4 Training Videos
1.4 Training Videos

VIP Training
Short video topics cover integration, creating test scenarios, using callbacks, messaging and
debugging, coverage, and error injection.
Running Cadence VIP Demo
Integrating Cadence VIPs into SV-UVM verification environment
Using Cadence’s RapidCheck Test-Suites for VIPs
Getting started with Indago™ Protocol Debug App
Indago™ Protocol Debug App Simplifies SoC Verification
What's New in Cadence Help 3.0
Download the tool and VIP documentation library from download.cadence.com
So You Think You're an Expert - Cadence Support Portal

Release Information
Release Information
This section contains information about the content of the VIPCAT 11.30.081, February 2022 release, and dependencies.
The following topics provide detailed information:
VIP Catalog Platform Support
Verification IP Compatibility and Dependencies
Using Specman Save and Restore
Important Note
1. The Verification IP Catalog no longer supports INCISIVE beginning the 11.30.81 release. No workaround is provided for continued
use of INCISIVE. You can move to Xcelium version 20.09 or later. For more information, contact the Cadence support team.
2. The Verification IP Catalog documentation library is now available on https://downloads.cadence.com. For more information, see
Viewing Documentation with the Cadence Help Tool.
2.1 Verification IP Catalog

The list of Cadence Verification IP (VIP) products available in the "VIP Catalog Product Introduction" document.
For a high-level introduction to each product in the VIP Catalog, see the following sections:
Memory Models
Simulation VIP
Virtual Protocols
Assertion-Based VIP
Interconnect Solution
Cross-Portfolio Technologies
VIP Portfolio Licensing

Release Information--2.2 Introduction to Virtual Protocols
2.2 Introduction to Virtual Protocols

This section contains the following topics:
Introduction to Virtual Protocols for Palladium and Protium
Directory Structure
Platform Support
VIPCAT Compatibility
Download Options for the VP Package
2.2.1 Introduction to Virtual Protocols for Palladium and Protium

The Virtual Protocols (VP) package includes the following products:
AVIP Portfolio
Ethernet Virtual Tester Interface
VirtualBridge Portfolio
VirtualBridge System Protocol Debugger
Virtual Device Model
2.2.1.1 Directory Structure

The following table lists the directory structure of the VP package:
Release Naming Convention of <vp_root> Path Example Path Version
Official pdapp<version>/<pdapp_version>/vp pdapp21.07/21.07.000.s000/vp 21.07

VP build
released
in
PDAPP
Official pdapp<version>/<pdapp_version>/vp_<vipcat_version> pdapp21.07/21.07.000.s000/vp_11.30.081-s 21.07_vp_11.30.081-

VP build s
released
with
VIPCAT
*
Nightly pdapp<version>/<pdapp_version>/vp_<date> pdapp21.07/21.07.000.s000/vp_15_Feb_2022 21.07_vp_11.30.081-

build s_<date>
The official VP build released with VIPCAT will be available from the VIPCAT 11.30.079 release.
When the VP package is installed from the official release and the nightly release, there might be multiple 'vp' directories under the same
PDAPP version. For example,
When VP package is installed from the PDAPP 21.07 release, the following directory is created:
pdapp21.07/21.07.000.s000/vp
When VP package is installed from an official VIPCAT release, released between PDAPP 21.07 and the next PDAPP release, the
following directory is created:
pdapp21.07/21.07.000.s000/vp_11.30.081-s
When VP package is installed from a nightly build, built on August 17, 2021, between PDAPP 21.07 and the next PDAPP release, the

following directory is created:

pdapp21.07/21.07.000.s000/vp_15_Feb_2022
The new and old platform locations in the root area <vp_root> are as follows:
Cadence 2020 platform: <vp_root>/rhel6_gcc63_abi0
Cadence 2021 platform: <vp_root>/rhel7_gcc93_abi1

The following diagram shows the VP root structure and location in the PDAPP release:
2.2.1.2 Platform Support

The VP package includes support for these platforms:
Platform Run compiler ABI11 OS Version C++ C Location in <vp_root>

* Standard Standard
Cadence 2021 GCC 9.3 (Default compiler in 1 RHEL 7.x (RHEL C++17 C18 <vp_root>/rhel7_gcc93_abi1
platform Xcelium 21.03s) 7.4, RHEL 7.6)
Cadence 2020 GCC 6.3 (Default compiler 0 RHEL 6.x (RHEL 6.5 C++14 C11 <vp_root>/rhel6_gcc63_abi0
platform in Xcelium 20.09s) and higher)
RHEL 7.x (RHEL
7.4, RHEL 7.6)
* The Library ABI (Application Binary Interface) is defined as the C++ interface version, that is, “Library API + Compiler ABI = Library ABI.”
Where,
ABI11=1—Refers to the ABI11 introduced in the libstdc++ library of the GCC 5.1 release, which conforms to the 2011 C++ ABI standard. It
breaks compatibility with the old ABI and might require some source code changes. The ABI11=1 support is first introduced in the PDAPP
21.07 release.
ABI11=0—Refers to the older library ABI, which was the default mode supported in the previous releases. For release guidelines to
migrate from the old ABI to the new ABI, see Migrating to the New VP Package in the PDAPP Release Information.
The UVM SystemVerilog flow is supported with the Cadence 2021 platform. However, the ease-of-use scripts shipped in the Denali
VIPCAT area are only demonstrating the Cadence 2020 platform flow.
For information about the platform support, see the VP Catalog Platform Support section of VP Catalog Release Information in the VP
documentation set.
2.2.1.3 VIPCAT Compatibility

The VP package is released within PDAPP and is also released in sync with VIPCAT releases. The VP package released in PDAPP may not
be compatible with an official VIPCAT release.
When VIPCAT compatibility is required, for cases where UVM SystemVerilog interface is used, or any of the VIP models are used, it is

Release Information--2.3 Using Save and Restore
recommended to pick the VP package that is available and in sync with the relevant VIPCAT release.
You can download the VP package from the VIP Portal. The compatible VIPCAT release will be available from the same page.
The build version of the VIPCAT used for building the specific VP build is available under: <vp_root>/vipcat_version.txt
2.2.1.4 Download Options for the VP Package

You can download the VP package from several locations:
Downloads
Latest official PDAPP release, including VP package.
VIP Portal
Latest official VP package released in sync the VIPCAT official release.
Latest nightly VP package released in sync with the VIPCAT nightly build.
Both VP build and VIPCAT build can be downloaded from the VP Portal
Important
In the environments, where any of the following is true:
The UVM SystemVerilog interface of the AVIPs is used
Any VIP model is required
Shared AVIP and VIP models (for example, NVMe, CCIX, BLE) are required
The sysApi interface for the PCIe AVIP is used
You must download a compatible combination of VP package and VIPCAT package from the VIP Portal.
The VP package in the official PDAPP release might not be compatible with any VIPCAT release, and can be used only when there is no
VIPCAT dependency.
For example, there is no VIPCAT dependency when using the C++ interface of the AVIPs without any of the items mentioned above.
Regardless of whether the VP package is downloaded from the Downloads or from the VIP Portal, the structure of the package remains
consistent. For details, see Directory Structure.
You can also download the VP package from the VIP Portal to install a hotfix regardless of the download source of the existing VP package
installed.
The naming convention of the VP official release tar file is pdapp<pdapp_version>_vp_<vipcat_version>_lnx86.tar.gz.
The naming convention of the VP nightly build tar file is pdapp<pdapp_version>_vp_<vipcat_version>_lnx86_<date>_<time>.tar.gz.
2.3 Using Save and Restore

The tables in this section provide information on the Save and Restore feature availability with various simulators.
Instead of re-initializing your simulation every time you want to run a test, using the save and Restore feature you can initialize once and save
the simulation as a snapshot and re-run if from that point to avoid hours of initialization time. Using this feature, simulators can gain productivity
gains.
Related topics:
Running Specman with Third-Party Simulators and Tools
Save & Restore with More: Preserve Your Entire SoC
Using save and restore commands in Specman

Release Information--2.4 Verification IP Compatibility and Dependencies
2.3.1 Questa
Cadence Verification IPs do not support Save and Restore with Questa. Only Cadence memory models support Save and Restore with Questa.
Environment Structure Supported Denalirc Checkpoint Parameter
Questa + Verilog or SystemVerilog Testbench VIP (C core) Yes (Memory models only) checkpoint 1
Questa + Verilog or SystemVerilog Testbench VIP (e core) No NA
Questa + Specman Testbench + VIP (C core) Yes (Memory models only) checkpoint 1
Questa + Specman Testbench + VIP (e core) No NA
2.3.2 VCS
All Cadence Verification IPs support the proprietary process-based solution of VCS simulator.
VCS ignores checkpoint variable setting.
VCS + Verilog or SystemVerilog Testbench VIP (C core) Yes Ignored
VCS + Verilog or SystemVerilog Testbench VIP (e core) Yes Ignored
VCS + Specman Testbench + VIP (C core) Yes Ignored
VCS + Specman Testbench + VIP (e core) Yes Ignored
2.3.3 Xcelium
All Cadence Verification IPs support the proprietary process-based solution.
Do not enable the checkpoint variable.
Xcelium + Verilog or SystemVerilog Testbench VIP (C core) Yes checkpoint 0
Xcelium + Verilog or SystemVerilog Testbench VIP (e core) Yes checkpoint 0
Xcelium + Specman Testbench + VIP (C core) Yes checkpoint 0
Xcelium + Specman Testbench + VIP (e core) Yes checkpoint 0
2.4 Verification IP Compatibility and Dependencies

This section lists release compatibility and dependencies for VIPCAT release 11.30.081.
VIP Catalog releases are tested with Xcelium for Universal and Open Verification Methodologies (UVM and OVM, respectively).
2.4.1 Supported Simulators

Cadence Verification IPs are supported with the following simulators:

Tested Simulators Version
XCELIUM 19.03 and later
VCS 2017.03 and later
MTI 10.6b and later
Note
The libsn_uvc.so file in this VIPCAT 11.30.064s release was compiled with INCISIVE version 14.20.020-s (Specman Elite version).
Consider compiling the libsn_uvc.so file if using a different version of Incisive or Specman version.
2.4.2 Compatibility with Other Products

The following table lists the compatibility of VIPCAT release with other products.
Product Supported Version
SYSVIP SYSVIP 01.22.02
AVIP/Virtual Protocol 21.07_vp_11.30.081
PERSPEC PERSPEC 22.01 and 22.02
See the following separate sections on information about Xcelium compatibility for these categories of products:
Accelerated VIP
New in Assertion-Based VIP (ABVIP)
2.4.3 UVM and Simulator Support

The Catalog VIPs are tested against the following native versions of the UVM library present with the simulator:
UVM1.2 (<path_to_xcelium>/tools/uvm-1.2) and Xcelium
UVM1.1 (<path_to_xcelium>/tools/uvm-1.1) and Xcelium
UVM1.1 (<mti_inst_dir>/modeltech/verilog_src/uvm_reg-1.1) and Questa (MTI, version 10.6)
UVM1.1 (<vcs_inst_dir>/etc/uvm-1.1) and VCS (version 2017.03)
Other than above native installations, the VIPs are also tested with uvm-1.1d, uvm-1.0p1, uvm1.1c, uvm-1.1b, uvm1-1a, ovm-2.1.1.
Note
The Catalog VIPs support the IEEE standard for UVM.
Cadence VIPs are compatible with UVM1.0ea, UVM1.0 (third-party simulators only), and UVM1.1. To maintain compatibility with all UVM
versions, the UVC's SystemVerilog code is still implemented using UVM1.0ea functionality.
The VIP Catalog UVM SystemVerilog API is compatible with UVM 1.1 and OVM 2.1.
Info
At present, UVM support is available only in SystemVerilog.
2.4.4 UVM and OVM

The language-independent PS-UI VIPs support UVM 1.1 and up as well as OVM 2.1.
In addition, the following VIPs are compatible with older versions of UVM: LIN, SLIMbus, and PCI.

Remember to use the Cadence UVM or OVM libraries, as they can contain bug fixes above and beyond the open-source versions of OVM
and UVM.
For UVM compatibility, ensure that you have the latest Xcelium release available at http://downloads.cadence.com/.
Cadence Verification IPs are tested against the following versions of the UVM library with NC-SIM, VCS, and MTI:
uvm-1.1, uvm1-1a, uvm-1.1b, uvm-1.1c, uvm-1.1d, ovm-2.1.1
2.4.5 vr_ad Package

The following UVCs use the vr_ad package from Specman:
PCI
SRIO
APB
MIPI SLIMbus

2.4.6 Accelerated VIP

Accelerated VIP (AVIP) is part of the VIP Catalog that enables design acceleration using the Cadence Palladium® Verification Computing
Platform. Cadence Accelerated and Simulated VIP support a variety of use modes to enable both validation of systems and subsystems, as well
as more extensive protocol compliance verification of block- and IP-level designs.
AVIPs require the Palladium Z1 or Z2 hardware, and VXE or WXE software, and Xcelium tools, and can use Universal Verification
Methodologies (UVM).
The following table lists Virtual Protocols compatibility for GCC 6.3, ABI11=0, and RHEL 6.5 and higher version in the VIPCAT 11.30.081
release:
Products Version Virtual Protocols
Palladium Z2 WXE21.00.006 and later Compatible
Palladium Z1 VXE21.02.005 and later Compatible
Protium X1 1 PTM21.03.006 and later Compatible
HDLICE HDLICE21.07.003 and later Compatible
IXCOM IXCOM21.07.003 and later Compatible
Simulator XCELIUM21.03.013 and later Not Supported
XCELIUM20.09.021 and later Compatible
Arm® Fast Model 11.10, 11.12, 11.13 Compatible
Internet Protocol IPv4 (Default), IPv6 2 Compatible
The following table lists Virtual Protocols compatibility for GCC 9.3, ABI11=1, and RHEL 7.4 and higher version in the VIPCAT 11.30.081
release:
Products Version Virtual Protocols
Palladium Z2 WXE21.00.006 and later Compatible
Palladium Z1 VXE21.02.005 and later Compatible
Protium X1 1 PTM21.03.006 and later Not Supported
HDLICE HDLICE21.07.003 and later Compatible
IXCOM IXCOM21.07.003 and later Compatible
Simulator XCELIUM21.03.013 and later Compatible
XCELIUM20.09.021 and later Not Supported
Arm® Fast Model 11.10, 11.12, 11.13 Compatible
Internet Protocol IPv4 (Default), IPv6 2 Compatible
1 For details on the Protium X1 support availability and status, see Support for Protium X1 in the Virtual Protocols Release Update Guide. For
Protium X2 support, contact your AE.
2 For details regarding support for IPv6, see Using the IPv6 Addressing Scheme in the Virtual Protocols Release Update Guide.
Currently, the AVIP and VirtualBridge are available for the Linux platform only.

Release Information--2.5 VIP Catalog Platform Support
For information about limitations in the accelerated VIPs, see Accelerated VIP (AVIP) in "Limitations and Workarounds."

Release Information--2.7 Deprecation Notices
2.5 VIP Catalog Platform Support

This VIPCAT release includes support for the following platforms:
Red Hat Red Hat Red Hat SLES12 CentOS

Platform 6.0 7.0 8.0
32- 64- 32- 64- 32- 64- 32- 64- 32- 64-
bit bit bit bit bit bit bit bit bit bit
Catalog Yes Yes Yes Yes No Yes Yes Yes Yes Yes
UVCs
Verification Yes Yes Yes Yes No Yes Yes Yes Yes Yes
IPs
Accelerated No Yes No Yes No No No Yes

VIPs 1 1 2
Memory Yes Yes Yes Yes Yes Yes Yes Yes

Models
ABVIPs Yes Yes Yes Yes Yes Yes Yes Yes
1 Starting with the VIPCAT 11.30.059 release, the 32-bit mode is not supported in the Accelerated VIPs.
2 Limited support is available only for the VirtualBridge use case
2.5.1 Platform Support Update

Starting Cadence VIPCAT release 11.30.052, Red Hat Linux 6.5 and above are supported. VIPCAT ended support for Red Hat Linux 5.
For information specific to Xcelium release platform support, see the Hardware and Software Requirements for that release.
2.6 Viewing Documentation with the Cadence Help Tool

The Verification IP Catalog documentation is now available for download as a separate item with each VIPCAT release. The documentation
library is packaged with the latest Cadence Help tool.
Use the following steps:
1. Download the VIPCATDOC.tgz file and extract the contents using the tar command.
2. If <VIPCATDOC>/tools.lnx86/bin is in your path, type:
cdnshelp &
otherwise, type:
<VIPCATDOC>/tools.lnx86/bin/cdnshelp &
The Cadence Help documentation tool appears on your desktop.

Release Information--2.7 Deprecation Notices
You can search for content, and search-string matches are displayed in a reading pane to the right of the search and navigation pane.
Explore "Verification IP" folder in the navigation pane, sub-folders for each of the protocols are displayed using the icon shown below:
Also see Troubleshooting common issues with Cadence Help
2.7 Deprecation Notices

Starting VIPCAT 11.30.075 release, the following product is being deprecated.
VIP for MHL

2.7.1 Recently Deprecated VIPs
Serial RapidIO VIP
Serial RapidIO 3.0 VIP
Old Denali Models:
AHB
ETHERNET
APB
AXI
I2C

New in This VIPCAT Release
New in This VIPCAT Release
This chapter lists new products, features, and major changes in the VIPCAT release 11.30.081.
New Products
Update on Licensing
New in Memory Models
New in Simulation VIP
New in Virtual Protocols
New in Accelerated VIP
New in Assertion-Based VIP
3.1 New Products

DFI GDDR7 - Initial Release

New in This VIPCAT Release--3.2 U pdate on Licensing
3.2 Update on Licensing

VIPCAT will be integrated with FLEXnet version 11.16.4.0 on September 2021, which means you will require Cadence license
server version 19.03-p001, which is integrated with FLEXnet version 11.16.4.0 or later. If you have not migrated to license servers
integrated with FLEXnet version 11.16.4.0, you should do so before September 2021. Otherwise, the product will not be able to
consume licenses and will fail to run.
The latest version of the license server also has some additional enhancements and fixes, such as support for the IPv6 network and
updates in the lmReRead utility behavior which enables the license server to read a new license file without interrupting the
ongoing client connections provided the new license file has sufficient number of licenses.
Cadence license server version 19.03-p001 is available for download at downloads.cadence.com under "Lic+Config_Utils".
3.3 New in Memory Models

Memory New Features
Name
LPDDR5
Added custom ZQ latch check support under enableDqZInZqLatChecks SOMA feature.
Added support for rank to rank tWCKDQI variation validation.
Updated the model to validate WCK frequency based on rank termination settings during Multi-Rank
CBT training.
Added support for the custom power-on state using chipStateAfterReset SOMA parameter.
Added support for the Ballot 1862.79.
Model now supports following timing parameters (applies when E-DVFSC Mode is enabled):
tRFCab_enh_dvfsc
tRFCpb_enh_dvfsc
tRFMab_enh_dvfsc
tpbR2pbR_enh_dvfsc
Updated with a changes to make sure model checks for error messages severity only between error
IDs of [1- max numbers of errors].
Changed the tOSCAL time to min. Even though the Lpddr5 Spec timing definition of tOSCAL mentions it
as max, it is a min timing requirement for the DRAM device.
Added CS pulse time information in tXSR_DSM and tXDSM_XP violation error message.

New in This VIPCAT Release--3.2 U pdate on Licensing
HBM3
Updated the model to trigger an error when dynamic configuration of timing specification is not correct.
Updated the model to trigger UVM_WARNING when configured DCA through MRS command matches the
desiredWdqsDCA.
Updated the model to store and drive all 8 UIs during DWORD MISR register mode.
Added feature awordMisrEvenCycles to check for even cycles during AWORD MISR modes excluding
preamble cycle.
Updated HBM3 model for Refresh Counter Reset whenever refreshchecks is set to 1.
Updated the HBM3 model to Bypass Vrefa/Vred training when Mode Register Dump Set (MRDS)
command is issued.
Updated stable clock count functionality.
The tCKSRX timer and checker has been marked as obsolete.
Enabled data corruption for DPAR signal on setup violation and sent feedback on DERR.
Bypassed intra/inter skew violation for DWORD MISR register mode.
Updated model to disable clock tracking when AWORD MISR mode is enabled.
Model bypasses validity checkers for Data pins such as DQ, DBI, ECC, and SEV
when inDCMTraining feature is set to 1.
G7
WL and RL starts from the rising edge of the second CK4 cycle as per the latest JEDEC ballots.
DDR4 DIMM
Updated RDIMM example to run with UVM-IEEE.
DDR5
Added a feature, customizeRefForEcsOp, to allow the host to choose the Ref command on which it
wants the DDR5SDRAM to perform ECS operation. When this feature is enabled, for each Ref
command in automatic ECS mode, a callback is sent to the host.
Two new transaction fields related to this feature have been introduced.
1) CA: Indicates the CA bus value for this command.
2) CustomRefEcs: If host wants a particular Ref command to perform ECS operation, it can set this field
to 1 and DDR5SDRAM will perform ECS operation for this Ref command. One of the unused bits (
CA{6] or CA[7] ) of Ref command can be set to 1 for the Ref command on which host wants
DDR5SDRAM to perform ECS operation in automatic ECS mode. During callback the CA comparison
can be done on host side to set CustomRefEcs field of transaction.
Updated command-to-command spacing coverage to exclude NOP and DESELECT commands.
Added TTFT examples to demonstrate manual-ECS and automatic-ECS operation.
During automatic ECS mode, the inter command timing gap from Ref to other commands is now same
for both ECS operation performing refresh command and normal refresh command.
DDR5 DIMM
Added TTFT example for DDR5 RCD model with DRAM model using RDIMM-Verilog-wrapper.
Added support for cases when the DIMM with x4 DRAMs have components mapped to different nibble
than the default 1-1 mapping with DQ Maps.
DDR5
Updated the model to exclude continuous burst MRR data callbacks from ddr5dimm data callbacks.
LRDIMM
GDDR6
Per bit skew between DQs is now as expected.

New in This VIPCAT Release--3.4 N ew in Simulation VIP
LPDDR4
Added support for differential checks error ID.
Default
Removed pulse width checker for sda on detecting start after stop
Flash
Updated QuadIoReadModeDummyMapping feature for SOMA part number MX25U25643G and
MX25U12832F.
xSPI
Added support to use specific timings from SFDP dword or SOMA.
3.4 New in Simulation VIP

VIP Name New Features
AMBA
AHB: Enhanced AHB VIP to send strobe value at ended burst.
APB: Updated the model to trigger checker CDN_APB_NONFATAL_ERR_CDN_APB025_UNMAPPED_ADDRESS for passive
master agent.
DTI: Added UVM sequence library for connect/disconnect messages.
chi: Added support of odd parity check for CHI-F specification.
ahb: Enhanced AHB VIP to support the following data masks:
DataMaskX[0] reflects hrdata[7:0]
Also, Datamask values are now reflected in ended burst.
chi: Node IDs can be configured as miscellaneous nodes using following register writes:
agent.regInst.writeReg(DENALI_CHI_REG_MapNodeType, DENALI_CHI_NODETYPE_Mn);
agent.regInst.writeReg(DENALI_CHI_REG_MapNodeID, #NODE_ID);
AHB: Updated VIP to check x and z checkers for active VIP.

LPI: Added support for Waveform debugger.
APB: Added register support to clear memory when bus reset occurs and enhanced VIP for partial data
consistency check support.
BLE
TripleCheck: Added IAL test as per BLE5.2 CTS SIG test scenarios.

CXL
CXL1.1: Enhanced model to support the CXL TL CM packet injection directly to CXL TL CM queue from the
testbench.
CXL2.0: Added ALMP flit pkt_data EI support through Rx CB at ArbMux layer.
CXL2.0: Added support of trans.log for CXL TL.mem packets. As of now, CXL TL Mem message is only
supported in newly added CXL tracker log file. You can enable this by doing the following settings in .denalirc.
PcieTransLogFile denali.log
PcieTransLogTypes cxltl
CXL2.0: Enabled dynamic SOMA reconfiguration for SOMA parameter CommonClkSupp.

CXL2.0: Added checker PCIE_TL_NONFATAL_CXL_PM_VDM_PAYLOAD_RSVD_NON_ZERO for CXL PM VDM Payload
reserved field check.
DFI
DFI-DDR5: Updated BFM for DDR5 and LP5 example for memory storage.
DFI Controller: Added support to drive DQS/DQ from MC.
DFI Controller: Added fields to support comparison between LP5/LP5 command truth table.
DisplayPort
edp1.4a: Added Active Source VIP support of sending Tps1 during PSR Exit when Link Training is bypassed.
dp1.4a: Added SOMA parameters, DpAuxManTxPreChargeLenMin/Max,
DpAuxManTxPreambleLen and DpAuxManTxSyncLen.
HDL-DH
PCIE: Updated implementation of SerDes polarity inversion in GEN 3.
PCIE: Added FastTxProcess (bit 12) in PCIE_REG_DEN_TLQ_CTRL_ST_2 register, with the following effect: TLP is
processed as soon as it arrives at TL (Monitor TX).
CAN: Enabled CAN bit timing configuration in UVM run time.

MIPI
soundwire: Added enhancement for sending bit array through VIP instead of char array.
csi2: Updated constraint on constraintPktNumOfPixels.
i3c: Modified test cdnTcI3cIBIDutArbitrationLoseTest as per update in I3c V1.1.1.
i3c: Added cdnTcI3cPassiveHotJoinSeq test in TripleCheck and support in VIP for Passive Hot Join feature.
i3c: Modified TripleCheck test cdnTcI3cENDXFERCcc_SDRSeq.
i3c: Modified test cdnTcI3cENDXFERCcc_SDRTest. Added ENDXFER support for Basic V1_1_1.
spmi: Added checker 138_SDATA_IS_HIGH_AFTER_COMMAND_SEQ_END to trigger at the end of the command
sequence if SDATA interface line is not released to zero.
mphy: Updated the model by adding a condition that CAPABILITY related bins get hit by reading its value.
i3c: Updated the model by adding cdnTcI3cPassiveHotJoinSeq test.
i3c: Added TC environment for I3c_Basic_V1_1_1 and a test for ENDXFER CCC.
i3c: Added basic V1_1_1 support for ENDXFER and in general.
i3c: Updated the model by adding Passive Hot Join feature.
unipro: Added
registers DENALI_UNIPRO_REG_TxUnitIntervalTolerance and DENALI_UNIPRO_REG_RxUnitIntervalTolerance for
unit interval tolerance.
csi2: Added support for LP11->LP00->anything error injection in CPHY.
MIIPIPHY_ACD: Added logic for word clock when data width is 64-bit.
MIIPIPHY_ACD: Added cdnTcMipiphy_acdCphy_HsTransactionwithRandomTriggers_Test for sending random

triggers with Hs transactions.
mphy: Added a register to enable SYNC pattern transmission on RMMI I/F in case of external sync. Until there
is no confirmation from M-PHY WG for the statement "SYNC pattern shall not be transmitted on RMMI I/F
regardless of internal or external sync", default value of this register is set as '1', thus maintaining current
behavior.
soundwire: Added vip_owner pin in wrappers and for all data lanes, earlier it was available for only data lane
0.
csi2: Case 46569908: Added support for OTH-ERR1 error injection in DPHY.
i3c: Case 46563407: Added support for CTS related scenarios to VIP.
soundwire: Added config parameter num_of_supported_sdca_intp_registers to configure the number of
supported SDCA interrupt registers in passive slave VIP instance.
csi2: Added notification event for serial ALP DPHY to indicate detection on control sync.
csi2: Added support to insert invalid data between alp control code and Hs-Trail in DPHY ALP mode.
PCIE
Gen 6: L0p DLLP fields can now be modified in DL_RX_queue_enter callback.
Gen 5: Warning added to check if Equalization Receiver Evaluation Successful is set for upstream while there
is a reject of current request for change of Preset/Coefficient during Phase 2 on course.
Gen 6: Added Gen 6 precoding negotiation.
Gen 5: Now, the receiver detection process will not depend on TxDetectRx[0] only.
Gen 5: Case 46574226: Set SOMA parameter driveRxElecIdleOnL1Exit to ensure Pipe Macro BFM

drives RxElecIdle when existing L1.Idle -> Recovery.Lock with pipe state in P2.
IDE : Added support to control K bit toggling for IDE.
IDE: Added IDE related information to PcieTransLogFile if IDE is supported.
Gen 6: When skipping Phase 2 and 3 in equalization the downstream port now sends 24 TS0.
IDE: The tool now skips IDE prefix packing and PR counter processing for TLPs that does not have correct
IDE stream ID set.
Gen4: VIP now ignores junk data coming from phy to mac on lanes that have seen TS2s with Link and Lane
num = PAD while in Configuration.Complete, indicating they will be disabled shortly.
IDE: Added new bit trInIdeTxQ in Denali TL Queue Control/Status 2 register, which is set right
before IDE_TX_queue_enter if it is clear, and is unset right after IDE_TX_queue_exit if the queue becomes
empty.
IDE: Added SOMA parameter IdePackStreamIdByAddr which when set to 1, enables TX VIP to match Stream
ID base on the Memory address for a given Mem Tlp when exiting UserQueue.
rnd: Added steps in basic user example for PCIe VIP sysApi adaptor.
Triplechek: Marked triplecheck tests TXN.06.02_06.MsgD, TXN.RX.INTA, TXN.RX.INTB, TXN.RX.INTC,
and TXN.RX.INTD as no_run if DUT reports unlimited credits for both header and data for posted requests.
Gen 3: VIP now ignores irrelevant data coming from phy to mac on lanes which has seen TS2s with Link and
Lane num = PAD while in Configuration.Complete, indicating they will be disabled shortly.
IDE: Added new opcode for user controlled K bit toggling.
Gen 4: VIP now ignores junk data coming from phy to mac on lanes which have seen TS2s with Link and Lane
num = PAD while in Configuration.Complete, indicating they will be shortly disabled.
Gen 6: Added fix to expect correct number of flits in Recovery.Idle state.
IDE: Added callbacks TL_IDE_TX_CIPHER_OP and TL_IDE_RX_CIPHER_OP.
TL_IDE_TX_CIPHER_OP at Passive Tx side is triggered one TLP at a time after IDE decryption, which is
every time model processes an IDE protected pkt with M bit set. This callback is triggered after
TL_IDE_TX_queue_exit and before pkt gets pushed to upper TL layer.
TL_IDE_TX_CIPHER_OP at Active Tx side is triggered one TLP at a time after IDE encryption, which is
every time model processes an IDE protected pkt with M bit set. This callback is triggered after
TL_transmit_queue_exit and before TL_IDLE_TX_queue_enter.
TL_IDE_RX_CIPHER_OP at Active/Passive Rx side is triggered one TLP at a time after IDE decryption,
which is every time model processes an IDE protected pkt with M bit set. This callback is triggered after
TL_IDE_RX_queue_exit and before pkt gets pushed to upper TL layer (TL_receive_queue_enter).

New in This VIPCAT Release--3.5 New in Virtual Protocols
Gen 6: Added new fields in the flit for all DLP0 and DLP1 fields.
Gen 3: With this enhancement, MAC BFM is now able to start RxMargining requests based on what is seen on
pipe message bus. The parameter marginMacBFMPartialInfoMode must be set on MAC BFM soma file to
enable this behavior. You can add to user queue messages to be written on pipe message bus. These
messages must be transmitted from MAC to PHY and must follow the format defined in the pipe specification
at "Table 8-5 Lane Margining at The Receiver Sequences".
PipePHY
Added RateScaleDown feature to support running USB at lower speed.
USB
USB2.0: Updated the model for VIP to respect IPG requirements when sending packets in USB2 test mode for
mode type 'Packet'.
eUSB: Updated the model for eUSB2 host repeater VIP to detect disconnect in SOF even when dribble bits are
received.
Triplecheck: Added TripleCheck PTM tests relevancy with !USB30 and Usb3PTMCapable.
Triplecheck: Tests are now marked irrelevant if the device (for host as dut) or passive agent (for device as
dut/hub as dut) does not have bulk stream endpoints.
Triplecheck: Model has been updated for Bulk unidirectional endpoints.
Triplecheck: Modified the test sequence for reducing the severity of checker.
Triplecheck: Reduced the severity of the expected checker in the triplecheck test.
eUSB: Updated eUSB2 TripleCheck to provide user configurable delay before issuing Resume/RemoteWake
when exiting low power state.
USB 3.2: Fixed an unexpected exit of the tool when user packed in queued in USB3 device VIP for endpoint
with active stream ID.
Triplecheck: Corrected the issue in the TripleCheck test.
USB 3.2: VIP change for interpretation of received symbols at 8BusQueue after rxDataValid signal transition
takes place from 0->1.
USB 3.2: Updated Local Loopback feature in VIP.
USB 3.2: Fixed the corner cases for lane mismatch for Gen1x2 as specified in the regression test location.
USB4
Updated the model to support reconfiguration of HIF rings.
USB4v2: DLLP TLP packet corruption is now fixed.
3.5 New in Virtual Protocols

This section lists new features in the virtual protocols.

New in This VIPCAT Release--3.6 New in Accelerated VIP
3.6 New in Accelerated VIP

AVIP Name New Features
All AVIPs Examples from the DENALI path are moved to the AVIP_ROOT path.
Old Path New Path

$DENALI/ddvapi/sv/uvm/<protocol>/SimAccel $AVIP_ROOT/<avip_name>/examples/sv_uvm/SimAccel
$DENALI/ddvapi/sv/uvm/<protocol>/examples_avip $AVIP_ROOT/<avip_name>/examples/sv_uvm
Ethernet
Added support for the Multiplexed USGMII (bfm_mux_usgmii) and Multi MAC (bfm_mac) interfaces
AVIP
Added support for the following features:
160-bit 4-lanes SerDes interfaces for 400GBASE-R
160-bit 2-lanes SerDes interfaces for 200GBASE-R
3.7 New in Assertion-Based VIP

ABVIP New Features
Name
Progressive In accordance with AMBA Progressive Terminology Update v3.0, the terminology used in ABVIP is being
Terminology updated to remove or replace offensive terminology.
included in
In AHB ABVIP source code, ‘Master’ is changed to ‘Manager’ and ‘Slave’ to ‘Subordinate’. This includes the
AHB ABVIP
change in parameter name, property name, and example name.
ABVIPs with progressive terminology are available
at <VIPCAT_INSTALL>/progressive_terminology/<protocol>/rtl/.
APB4 ABVIP Added support for APB5 user signaling. To support this feature, following parameters have been added:
APB5_USER_SIGNALING: Set this parameter to 1 to enable APB5 user signaling properties
USER_REQ_WIDTH: Sets the width of pauser signal
USER_DATA_WIDTH: Sets the width of pwuser and pruser signal
USER_RESP_WIDTH: Sets the width of pbuser signal

This section describes important customer issues and customer change requests (CCRs) for all VIP
products in the Verification IP Catalog and tells you how to solve or work around these problems.
Issues are listed in alphabetical order by product name.
Updated Known Problems and Solutions documents are published at regular intervals. Customers
can view on Cadence Online Support the most up-to-date information about the status of their
issues and CCRs.
4.1 VIRTUALBRIDGE
CCR 2196526 VM auto-shutdown feature requires the same number of ports at restart and at
the first run
The Virtual Machine auto-shutdown feature has a limitation. It requires that the number of ports
used in a design when restarting a Virtual Machine must be same as the number of ports used in
the design at the first run.
CCR 2241767 Version information file is moved into the backup folder
The issue is produced if the transactions occur in a specific order as follows:
1. Disable the hsv_system_protocol_debugger tag in the client_server_properties.xml file and
execute a test case.
2. Enable the hsv_system_protocol_debugger tag and execute the test case, then the Database
Version Information file is moved into the backup database inside the debugger.vbrd
directory.
The database version file has information related to the versions for the AVIP, Xcelium,
VirtualBridge, and so on. These details are used for displaying information related to the database.
Before enabling the hsv_system_protocol_debugger tag by setting it to 1, remove or rename the
debugger directory (debugger.vbrd) inside the vb_swork directory. After removing the debugger.vbrd

Known Problems and Solutions--4.2 XRUN
directory, a new database directory is created and the database version information file is dumped
in the correct database.
CCR 2166342 Issues in clean exit of USB device when exiting the Xcelium simulator
The USB device does not exit properly at the end of the simulation. The issue occurs when exiting
the Xcelium prompt.
Currently, no workaround is available.
4.2 XRUN
CCR 2196482 Single run command does not run the design after saving a snapshot
When using the process-based save and restart operation of the Xcelium simulator and running the
design in the emulation mode, the run command must be given twice to resume running the design
on the Palladium emulator.
1. Press Ctrl+C to get the Xcelium prompt on the server.
2. Execute the Tcl save command to save a simulation snapshot.
3. Give the run command twice to resume running the design on the emulator.
4.3 AVIP_USB4
AVIPUSB4-297 USB4 AVIP is not supported on RHEL 7 with GCC 9.3 platform
None.
4.4 AVIP-DisplayPort
AVIPDP-218 DisplayPort AVIP is not supported on RHEL 7 with GCC 9.3 platform
None.
4.5 AVIP-HDMI
AVIPHDMI-77 HDMI AVIP does not work with VXE 20.05 decoupled releases

Known Problems and Solutions--4.6 VIP-CAN
The HDMI AVIP does not work with the VXE20.05, IXCOM20.05, HDLICE 20.05 and higher
decoupled releases.
The problem occurs because support for SCE-MI pipe is not available on the decoupled releases.
The HDMI AVIP is planned to be enhanced to support the Multiple Channels GFIFO-SFIFO
technology instead of the SCE-MI pipes in a future release.
Use an older VXE release to compile and run HDMI AVIP.
AVIPHDMI-8 / CCMPR00983547 The HDMI SINK AVIP cannot process the Pixels when Pixel
Repetition is set to 6 for some of the VIPs.
None.
AVIPHDMI-7 / CCMPR01061253 HDMI AVIP examples have multiple copies of files with
similar names.
Until this is fixed (and the files are renamed), users should run make -n to check the exact file name
before integrating the AVIP in their environment.
AVIPHDMI-6 / CCMPR01089544 HDMI AVIP does not support setting Custom 3D Metadata
fields.
Use the custom Infoframe to build the complete packet, and then send it to the HDMI source.
On the sink side, the decoding should be performed by the user.
AVIPHDMI-5 / CCMPR01061165 HDMI AVIP does not log messages to the irun.log file.
When invoking irun, use the "tee" UNIX command to redirect the STDOUT and STDERR streams:
irun ... | & tee avip.log
AVIPHDMI-4 / CCMPR01073627 HDMI AVIP has a limitation of processing the Deep Color
Mode only when the Default Phase is set to 1.
No current workaround.
4.6 VIP-CAN
VIPCAN-119 / / The bit width of Data signal dut_data_to_lt port has been extended from 64 to
512
Workaround: Testbench with access to "dut_to_lt" port signal needs modification.
Modify the bit width of respective signal that is bound to dut_to_lt port signal of the VIP to 512 in the
test bench.

Known Problems and Solutions--4.7 VIP-DOCS
For 'e' users:

dut_data_to_lt signal of VIP is 'sig_can_dut_data_out_lt'
Reference - $CDN_VIP_ROOT/vips/can/cdn_can/e/cdn_can_signal_map.e
For PSUI-SV users:

dut_data_to_lt signal of VIP is 'can_dut_data_to_lt'
Reference -
$CDN_VIP_ROOT/tools/denali/ddvapi/sv/uvm/cdn_can/examples/isoExamples/soma_uvm/CanAct
iveLT.v
4.7 VIP-DOCS
VIPDOCS-874 / / Protocol Error Injection Mandatory Configuration
Workaround: To inject protocol error, the constraint ProtErrInvalidCodeKind.size() == 1 should
be written irrespective of the protocol type. Otherwise a constraint failure will occur and packet won't
be generated.
4.8 VIP-USB
VIPUSB-2 / CCMPR00869709 / ModelSim crashes in one of the example tests in package.
Workaround: None.

This chapter lists known limitations for the following VIP products and categories of products in this
VIPCAT release.Simulation VIP Limitations
The following sections are available:
Catalog-Wide Limitations
Simulation VIP Limitations
Accelerated VIP (AVIP) Limitations
Assertion-Based VIP (ABVIP) Limitations
Info
The Interconnect Workbench is available for the Linux platform only.
5.1 Catalog-Wide Limitations

VCS Memory Leak with libcdnsv.so
Licensing
Accessing Memory in a UVM or OVM SystemVerilog Environment
UVM and OVM
User Interface
Compilation with irun
SystemVerilog
Heap Memory

Limitations and Workarounds--5.1 Catalog-Wide Limitations
5.1.1 VCS Memory Leak with libcdnsv.so

VCS has a memory leak with libcdnsv.so. During long simulations, memory use increases and
performance degrades, and the simulation may even run out of memory. Synopsys has added a
switch to address this leak. If you are using libcdnsv.so with VCS, you must add this switch to the
vcs command line as shown below:
-XVpiCbAutoRelease=libcdnsv.so
If you are using SystemVerilog callbacks, use a Cadence VIP release starting December 8, 2018 or
later when using the above switch. We were prematurely freeing a simulator handle that is used to
implement SystemVerilog callbacks, and the addition of the above switch exposes that bug.
5.1.2 Licensing
Specman displays an error when there is no available Xcelium license.
This behavior is not controlled by the VIP-specific licensing parameters for queuing or
timeout.
This behavior is relevant only to some VIPs (UVCs).
A non-Xcelium customer simulation (VCS, MTI) with the Specman Virtual machine (that
is, Specman included in the VIPCAT release as opposed to Specman from an Xcelium
release) requires a VIP_UVC_3PSI_ENGINE license rather than an Xcelium license.
If queuing from multiple license servers is needed for a session to pass, at least one of the
servers has to contain a number of portfolio licenses greater than or equal to the number of
portfolio licenses required by the session.
Some deadlock scenarios are not handled.
For licensing and configuration information for this release, refer to VIP Licensing Guide and VIP
Catalog Download and Installation.
5.1.3 Accessing Memory in a UVM or OVM

SystemVerilog Environment
Accessing the denaliMemInstance or denali<Protocol>Instance class must be done after the
build() phase in UVM or after the post_new() phase in OVM.

5.1.4 UVM and OVM

The SystemVerilog VIPs have not been tested in the ML OVM mode. As a result, Cadence
cannot guarantee that all SV VIPs will work in this mode.
The following are possible issues with UVM1.0 and later:
simulated time overflow IUS error message--Was encountered when "Compiling UVCs into a
library"
Workaround: Add -defile UVM_DEFAULT_TIMEOUT=0 to the irun command.
global_stop_request() does not stop the test--Was encountered in multi-threaded simulations.
The simulation hangs after global_stop_request() is called.
Workaround: Add #1; after global_stop_request():
Printing of the topology tree takes a very long time--Was observed when the topology printout
is extremely long.
Solution: Reduce printer.knobs.depth
Sequencer's count field could no longer be used to set random sequence behavior
Note: Until UVM1.0ea, either of the following two methods could be used to declare default
sequences for a sequencer. Now, only the second can be used:
set_config_int("sequencer", "count", num);
Using this method UVM used to assume the default sequence behavior for the
sequencer would be random. This is no longer supported, as of UVM1.0.
set_config_string("sequencer", "default_sequence", "some_seq_name");
This method explicitly specifies which sequence is the default sequence; no
assumptions. This is how it should be done for UVM1.0 and later.
If count is declared, but not a default sequence, no sequence will run with UVM1.0 for this
sequencer.
Solution: Explicitly register a default_sequence to the sequencer, similar to the second method
noted above.
Tip
To mimic random sequence functionality, implement one and assign it explicitly to the
sequencer.

Tests appear as passing although nothing happened. This could be due to one of two
reasons:
+UVM_USE_OVM_RUN_SEMANTIC flag was not passed to the [nc]sim/irun command
set_config_int("sequencer", "count", num); was used in order to set a random sequence
behavior by default (no explicit declaration of any sequence as default)
ncsim crashes with the error F,INTERR: INTERNAL EXCEPTION when running with UVM1.0
Solution: Update Xcelium to the latest version.
For dependency information regarding UVM and OVM, refer to UVM and OVM .
5.1.5 User Interface

The memory or register read action for some models does not adhere to the convention we
use for memory packets and transaction packets, in which the 0th index of a data or payload
array holds the most significant byte.
In those models we fixed the register read (regInst.read) action.
All examples and documentation was modified accordingly to support this.
For example, to read 32 bits of data, use a method similar to the following:
virtual function reg [31:0] readReg(denali<Model>RegNumT addr);

denaliMemTransaction trans;
trans = new();
trans.Address = addr;
void'(regInst.read( trans ));
readReg[31:24] = trans.Data[0];
endfunction : readReg
In PureView, selecting a parent item in the Features pane has no effect on the child elements.
That is, when an item has sub-selections, setting or un-setting the parent item does not affect
the sub-items, and thus does not affect configuration.

If you are using the VIP Catalog release with VCS, you must add ${DENALI}/lib to the
LD_LIBRARY_PATH variable.
5.1.6 Compilation with irun

The irun -cdn_vip_root option does not compile VIP if HDL instantiation files having pragmas are
included.
When using cdn_vip_root to compile the e code with irun, if the HDL instantiation files (wrappers)
are included in the top testbench using `include, the VIP does not compile. That is, the libPsif.so
is not created.
The standard use model is to put the HDL file on the command line. For performance reasons, irun
scans the top of each source file on the command line, looking for pragmas like our cdn_vip_model
program. It would negatively affect performance for irun to actually parse entire files looking for this
information.
If you want to `include instantiation files, you need to manually add the necessary pragma such as
the following to the top of the file that includes the instantiation file, such as this example for enet:
// pragma cdn_vip_model -class enet
This pragma simply tells irun that it needs to compile the e for the enet model, and that is done only
once per snapshot, no matter how many enet instances (or pragmas) there are. It is not harmful to
have the pragma in more than one place, so it can remain in place in the enet instantiation file as
well.
5.1.7 SystemVerilog
5.1.7.1 IntelliGen
When using IntelliGen, specifying conditional reset_soft() under a conditional keep for each
is not supported.
5.1.7.2 3PSI
When using VIPCAT with the VCS simulator, you might encounter the following error:

*** Error: Cannot open library

Failed to open `<VIPCAT>/tools.lnx86/ucd/lib/libucdb.so' shared library
Operating System error:
<path to gcc>/gcc/*/lib/libstdc++.so.6: version `GLIBCXX_3.4.*' not found
(required by <VIPCAT>/tools.lnx86/ucd/lib/libucdb.so)
Both VIPCAT and the simulator use libstdc++ which is loaded just once. If the simulator loads the
libstdc++ before VIPCAT does, there will be no other load of the same library with the same major
version.
If the libucdb.so used for the simulation was compiled with an earlier gcc version than the one used
to compile the VIPCAT libraries, this error is issued.
To work around the issue:
<VIPCAT>/tools/lib[64bit]
When executing cdn_vip_env.[c]sh, run_vcs_sv.sh, run_mti_sv.sh, or run_nc_sv.sh with the -

setup flag enabled, the cdn_vip_setup_runme.sh or runme.sh file created will include this step.
The step noted above should resolve the issue, unless advanced environment settings are defined
to change or override the LD_LIBRARY_PATH settings. In that case:
1. Check whether you have a wrapper script for VCS that or MTI changes the LD_LIBRARY_PATH
2. Check /etc/ld.so.conf file/imports.
3. Check whether the rpath flag is set in your gcc configuration. rpath is a linker flag for
searching dynamic libraries that have precedence over the LD_LIBRARY_PATH variable.
4. Ensure that the option -noautoldlibpath is not passed to MTI (since the vsim command
default will change the LD_LIBRARY_PATH).
5.1.8 Heap Memory

Some models control the maximum heap size that a simulation process can use. In very big
simulation environments, the default Specman heap memory may not be enough, and can cause
frequent garbage collections.
To avoid this issue, increase the default size (in megabytes) of memory allocated for the machine
by setting the .denalirc hook MaxHeapSize variable with a non-zero integer. (A zero value indicates
that the default setting should be used.)
For 32 bits, the max size should not exceed 3072 MB, which is the default.

Limitations and Workarounds--5.2 Simulation VIP Limitations
You can view the actual heap memory size allocated for the simulation by issuing the following
command from the simulator:
sn show conf mem -optimal_process_size
5.2 Simulation VIP Limitations

AMBA AXI
DisplayPort
HDMI
I2C
Interconnect Validator
JTAG
LIN
MIPI PHY
MIPI SLIMbus
OCP
PCIE
SAS
USB
5.2.1 AMBA AXI

AXI will not run with the MTI simulator version 6.6c
Passive interconnect requires bursts driven out of the interconnect to be the same size as
bursts driven into the interconnect.
You might encounter a CMS reset problem with designs that run with a simulator other than
IUS. If you encounter such a problem, contact our support team for a workaround.

5.2.2 DisplayPort
The Global Time Code (GTC) feature currently only supports Source as GTC Master (Sink as
GTC Slave).
GTC does not support reference clock switching.
5.2.3 HDMI
The HDMI run_examples.sh script does not function properly on the Sun4V platform.
The HDMI UVC currently requires 64-bit Specman.
SV tests are not working on platforms other than Linux
5.2.4 I2C
To maintain backward compatibility, the I2C UVC port map has not been updated in this release,
despite being noted in the user guides.
5.2.5 Interconnect Validator

Limitations in Interconnect Validator for OCP are:
Imprecise burst not supported.
Addressing modes like XOR, DFLT1, DFLT2, UNKN not supported.
Note: Set the configuration variable called monitor_srmd_beat_info_enable to TRUE if simulation
consists of SRMD Bursts.
5.2.6 JTAG
The JTAG UVC demo does not work with ModelSim. The UVC does support ModelSim, but has a
demo limitation. Please run this demo with the Xcelium simulator.

5.2.7 LIN
The current 2.1 LIN Version does not support all the features connected to the higher-level transport
layer, as defined in last LIN 2.1 Protocol Specification document. This is because it is considered
out-of-scope when addressing functional verification at device level.
In addition, the LIN 2.1 UVC does not support:
1. Event triggered frames scheduling and collision resolution (this can be achieved within your
tests, because frame scheduling inside the UVC is managed with sequences).
2. Error response bit signalling (you can configure the frame holding this particular node's status
signal using NCF configuration
5.2.8 MIPI PHY

Note: cdn_mipi_phy is a utility UVC used by MIPI CSI2 and MIPI DSI. For more information, please
refer to the user manual for those protocols.
5.2.9 MIPI SLIMbus

The SLIMbus UVC interface uses Verilog-2000 commands that are not supported by the XL
simulator; therefore, the SLIMbus UVC cannot run on the XL simulator.
No support for Locked transport protocol
No support of elemental access for Information and Value Elements
No support of Report Absence message

5.2.10 OCP
OCP VIP cache coherent feature is implemented, but OCP VIP does not support system
intervention. OCP 3.0 cache coherence implementation provides support for self intervention
only.
The OCP3.0 Disconnect feature is implemented, but the interface bundle name ocp3 is not
supported in rtl.conf. The disconnect feature will be part of ocp2 functionality. As a
workaround, please set the interface name to ocp2
For OCP ABVIP limitations, see Assertion-Based VIP (ABVIP).
The transaction recording is not accurate
5.2.11 PCIE
Crosslink support is limited to allow BFM to be connected to a DUT that supports crosslinks.
BFM does not support performing crosslink itself.
5.2.12 SAS
SystemVerilog tests using the OIG interface for the SAS VIP and demo.sh sas -lang sv will not
work in this release. For the SV interface of SAS, please use the SAS PureSpec user
interface.
CMS implementation is limited. The vPlan is implemented for all layers, but mapped for only
the Transport layer.
The following are limitations of SAS 12Gbps
The checks are not complete for the following:
Validity of TTIU
Transmission or decoding of invalid Coefficient Requests
Features or aspects of Transmitter Training
Invalid Patter Marker Transmission and decoding is not supported.

Limitations and Workarounds--5.3 Accelerated VIP (AVIP) Limitations
5.2.13 USB
The following features from specifications are not yet supported:
SSIC’s M-PHY TestMode
USB3.0 Hub Enumeration (USB3.0 Hub is a pure repeater)
OTG3.0 Interoperability with OTG2.0
Indago Protocol Debug App does not support Hub
5.3 Accelerated VIP (AVIP) Limitations

Bug Fixes
Known Limitations
5.3.1 Bug Fixes

For a full list of defects fixed and enhancements made, see Fixed Issues in This Release
5.3.2 Known Limitations

nb_run is supported only when swapping to Palladium after AVIP reset is done.
Passive agents are not supported. Specifically, signal-level protocol checking, and collecting
coverage on signal-level activity is not supported.
Additionally, see the following protocol-specific limitations:
AMBA ACE AVIP:
The ACE data bus width is limited to 32-, 64-, 128-, 256-, 512-, or 1024-bits wide.
The AMBA 5 protocol versions, including AXI5, ACE5 and ACE5-Lite, are currently
available with the C/C++ and UVM SystemVerilog interfaces, and with the embedded
mode.

Issuing interleaved transaction responses is only supported in the ACE Embedded

Slave. It is not supported by the other ACE Slaves.
Data-before-address feature:
The ACE Master AVIP has no configuration to guarantee data-before-address
order of a burst, but this can be achieved by configuring channel delays.
Issuing out-of-order response transaction is supported in the ACE Embedded Slave. For
the other ACE Slaves, this functionality must be handled in the testbench.
AMBA AHB AVIP:
For Arm AMBA Specification (Rev 2.0), only the master component is available.
Currently, the AMBA AHB AVIP performance monitor for IVD or SVD does not support
early termination. As a result, all the bursts that are terminated early will be reported by
IVD or SVD as unmatched at the end of the run.
AMBA APB AVIP:
Slave does not support batching mode.
Slave does not have internal memory. It is your responsibility to implement a memory in
the testbench.
AMBA AXI AVIP:
The AXI data bus width is limited to 32-, 64-, 128-, 256-, 512-, or 1024-bits wide.
The AMBA 5 protocol versions, including AXI5, ACE5 and ACE5-Lite, are currently
available with the C/C++ and UVM SystemVerilog interfaces, and with the embedded
mode.
Issuing interleaved transaction responses is only supported in the AXI Embedded
Slave. It is not supported by the other AXI Slaves.
Data-before-address feature:
The AXI Master AVIP has no configuration to guarantee data-before-address order
of a burst, but this can be achieved by configuring channel delays.
Issuing out-of-order response transaction is supported in the AXI Embedded Slave. For
the other AXI Slaves, this functionality must be handled in the testbench.
AMBA CHI AVIP:
V8 mapping is not supported

The CHI B Embedded Slave does not support:

Atomic transactions
Configurable channels delay
DMT transactions
The AVIP for CHI Issue E with RNF and RNI does not support:
Transaction optimizations for permitting Forward snoops to be handled as Non-
Forward snoops
Interface behavior of multiple interfaces and of replicated channels on a single
interface
Arm architecture related to the DVM updates
The AVIP for CHI Issue E with HN2SN does not support:
Transaction optimizations for Direct Write-data Transfer and for Combined Write
and (P)CMO
Interface behavior of multiple interfaces and of replicated channels on a single
interface
ATB AVIP:
ATB data bus width is limited to 32, 64, 128, or 256.
BLE AVIP:
Currently, the HCI USB transport layer is not supported
Currently, the BR/EDR Controller mode is not supported
The C or C++ testbench interface is not supported
CAN AVIP:
Error frames generation is not supported
Bus off and Bus recovery are not supported
CCIX AVIP:
CCIX Traffic Constraints
Request Chaining and Snoop Chaining features are currently not supported
Snoop Broadcasting is currently not supported

Message Packing - Sending and receiving more than one CCIX message within a
packet is currently not supported
Sending and receiving Credited Miscellaneous messages is currently not
supported
Support available for only one-to-one Link connection per each CCIX RNF/HNF
Agent. Switches are currently not supported.
Memory Expansion
Address Width greater than 52 bits is not supported
128B cache line size
Partial write is not supported
Currently, the CCIX AVIP supports only Reactive Mode. (Relevant for the PCIe Agent)
Currently, the CCIX AVIP supports only EventBasedMode (Relevant for the CCIX
Agents)
CXL AVIP:
When data is addressed to CXL.mem registers, the memory region pointed
by MEMBAR0 is not populated
AVIP sends dummy data with the S2M_DRS response of CXL.mem
CXS AVIP:
CXS data bus width is limited to 256, 512, or 1024.
Passive agents are not supported. Specifically, signal-level protocol checking, and
collecting coverage on signal-level activity is not supported.
CSI-2 AVIP:
In the CSI-2 PPI DPHY 2.0 interface, two and three lanes in the 32 data bus width are
not supported
In the C-PHY 1.1 serial interface, currently UVM SystemVerilog examples are not
available
The embedded CSI-2 device interface is not supported for the C-PHY configurations
DBI AVIP:
The Type-A interface is not supported.
DSI AVIP:

Currently, the C-PHY interface supports only HS transmission (LP transmission is not
supported)
Currently, the C-PHY interface is available only on the device side
DisplayPort AVIP:
Currently, the AVIP for DisplayPort supports only 64-bit tools.
DisplayPort AVIP only compiles when you use GCC version 4.8 or higher.
When using the GCC version 5.0 or higher, owing to changes in the ABI library,
you must compile the code with the _GLIBCXX_USE_CXX11_ABI=0 compile-time
define to use the AVIP libraries.
Currently, the AVIP for DisplayPort supports only four lanes traffic. The DisplayPort Sink
and Source AVIPs do not support one and two lane traffic. Contact the Cadence Support
team to request support for one and two lanes.
Currently, the MST mode is supported only for Sink.
Ethernet AVIP:
The embedded use model is not intended to be used with the Ethernet AVIP.
For Half Duplex with OUSGMII (USGMII),
Half Duplex is supported only for 10M/100M ports. It is not supported with 1G
ports.
Packet bursting, frame extension, and late collision are not supported
Flow control for Half Duplex ports is not supported
HDMI AVIP:
Currently, the HDMI AVIP does not support HEAC (HDMI Ethernet and Audio Return
Channel). Contact Cadence if you have a request for a HDMI HEAC, or only for HEC or
ARC.
Coverage is not collected from the AVIP model.
I2C AVIP:
Ultra Fast-mode is not supported
Device ID feature is not supported
START byte generation in Master mode

Currently, supports the I2C packet size up to 2^16

I3C AVIP:
Secondary master is not supported in the Master mode. It is supported only as Slave.
In-Band Interrupts are not supported
Hot-Join is not supported
Currently, supports the I3C packet size up to 2^16
I2S AVIP:
Asymmetrical word select is currently not supported.
LIN AVIP:
Currently, the UVM SystemVerilog interface is not supported
LDF configuration is not supported
Error injection is not supported
Diagnostic, Event Triggered, and Sporadic frames are not supported
Transport layer is not supported
PCIe AVIP:
The PCIe 5.0 AVIP supports only the INTA signal-based interrupts. It does not support
the INTB, INTC, and INTD signal-based interrupts.
Currently, error injection is not supported.
Only one pair of TX-RX is supported while accessing PHY/MAC PIPE registers. RX2
and TX2 are not supported.
Analog related signals that are not required by PCIe AVIP controller are not supported in
the PIPE 5 implementation.
For example, TX Swing, TX Margin, Lane margining, and Re-calibration of PHY.
USB4 AVIP:
On the receiver side of the Logical Layer, RS-FEC error correction is not supported

Limitations and Workarounds--5.4 Assertion-Based VIP (ABVIP) Limitations
5.4 Assertion-Based VIP (ABVIP) Limitations
5.4.0.1 ACE5 ABVIP

H version in ACE5, ACE5-Lite, ACE5-LiteDVM ABVIP is not supported.
Workaround: None
5.4.0.2 CHI-E-SYS ABVIP

CHI-E-SYS does not support:
DMT, DCT, and DWT feature
5.4.0.3 DDR5 ABVIP

Input Clock Frequency change is not supported.
5.4.0.4 I2C ABVIP

Arbitration is supported only in I2C ABVIP master for formal verification.
I2C ABVIP monitor does not check arbitration related functionality for simulation.
Workaround: None
5.4.0.5 OCP ABVIP

The OCP ABVIP is not designed to check proper data value on valid byte lanes of the data bus. In
formal, we can ignore this particular error for now, and use the VIP to check the same in simulation.
5.4.0.6 CHI and CHI-D ABVIP

PGroupID is required to be unique.
Workaround: None

Limitations and Workarounds--5.4 Assertion-Based VIP (ABVIP) Limitations
5.4.0.7 CHI-D SYS ABVIP

DMT feature is not supported.
5.4.0.8 CHI-E ABVIP

Use a separate ABVIP module, cdn_abvip_chi_e_replicated_chnl to enable Replicated
Channel support. This feature is in beta phase, and undergoing changes. Please contact
Cadence Support before you enable this feature.
StashGroupID in Stash Transactions is required to be unique
5.4.0.9 CHI-D and CHI-E ABVIP

TgtID Remap feature is supported only when ENABLE_RN_SAM is set to 0.
5.4.0.10 SPI ABVIP

Switching the SPI from master to slave or conversely is not supported.
Workaround: None

This chapter lists fixed issues for VIP products in this VIPCAT release.
List of Defects
List of Enhancements
6.1 List of Defects (since VIPCAT release 11.30.080)

6.1.1 AMBA
VIPAMBA-5616: 2022-01-27: ahb: Case 46575945: Enhanced VIP so that it does not break
when data is not passed in c-vip.
VIPAMBA-5613: 2022-01-23: ccix: Case 46584432: Credits are now sent automatically even
after second reset.
VIPAMBA-5598: 2022-01-20: ahb: Case 46580271: Fixed the behavior of VIP in case of
single byte transfer with BE8 and unaligned address.
VIPAMBA-5597: 2022-01-10: stream: Case 46582177: Fixed Tkeep and Tstrb driving issue.
VIPAMBA-5487: 2021-11-23: ahb: Case 46568523: Fixed the issue where burst ended for
unaligned first address in case of halfword hsize and 32-bit bus width.
6.1.2 BLE
VIPBLE-599: 2022-01-12: TripleCheck: Case 46533266: Added 5.2 SIG test case scenarios
in TripleCheck.
VIPBLE-603: 2022-01-12: TripleCheck: Case 46547074: Fixed status return parameter for
event.

Fixed Issues in this Release--6.1 L ist of Defects (since VIPCAT release 11.30.080)
6.1.3 CXL
VIPCXL-1096: 2022-02-07: cxl2.0: Case 46583619: Fixed an issue that the VIP wrongly
discarded the next packet when the previous packet had any error.
VIPCXL-1088: 2022-02-04: cxl2.0: Case 46581063: Added check for MDH Slot Format Data
Header Messages valid bits. Check returns true if there is at least 1 Data Header in MDH Slot
Format for which valid bit is set. This prevents BE = 0 and SZ = 1 check in cases where MDH
Slot has all Data Headers without valid bits set.
VIPCXL-1084: 2022-02-04: cxl2.0: Case 46578725: A VIP issue was preventing proper data
transmission in CXL mode when skew injection was active. FLIT data was not distributed to
all of the TX fifos for active lanes upon entry to Configuration.LinkwidthStart. With this fix,
the VIP fills the empty TX fifos.
VIPCXL-1007: 2022-01-29: cxl2.0: Case 46562875: Fixed issue of monitor not following DUT
from Configuration.Complete to Configuration.Idle when downconfigure is repeated in
block mode in lane reversal scenario.
VIPCXL-1085: 2022-01-07: cxl2.0: Case 46579429: Removed noSyncHdrBlockType assertion
due to false triggering in lane downgrade.
VIPCXL-1075: 2021-12-20: cxl2.0: Case 46575973: Fixed model to accept ModTS2 common
capability field as a subset of ModTS1 common capability field instead of the same value.
VIPCXL-1043: 2021-11-30: cxl3.0: Case 46564134: Corrected the issue where VIP CXL.IO
incorrectly expects continuation of incomplete TLP after returning from Recovery.
VIPCXL-1045: 2021-11-23: cxl2.0: Case 46569054:Updated model to send Retried AllData
flit before starting LRSM RETRY_LLRREQ state.

6.1.4 DFI
VIPDFI-1416: 2022-01-22: DFI Monitor: Case 46579252: Fixed unexpected error
dfi_rddata_en assertion during back to back read.
VIPDFI-1440: 2022-01-16: DFI Monitor: Case 46581830: Added fix to update wakeup time in
SOMA based signal values.
VIPDFI-1437: 2022-01-03: DFI PHY: Case 46581379: Fixed init_complete response for
init_start after reset while SkipInitialization is enabled.
VIPDFI-1408: 2021-12-15: DFI PHY: Case 46576984: Fixed CS hold time issue.
VIPDFI-1371: 2021-11-29: DFI PHY: Case 46565643: Updated driving of write data on DQ
when twck2ck>0 and Wck:Ck ratio=2.
VIPDFI-1396: 2021-11-17: DFI PHY: Case 46571020: Fixed the delay calculation when dram
clock is enabled and PHY clock is disabled.
6.1.5 DisplayPort
VIPDISPLAY-2188: 2022-01-10: dp1.4a: Case 46571705: Fixed SU color array size of Cb/Cr
for YCbCr422/420 when PSR2 is enabled.
Added new UVM config object eDP_1_5 for eDp 1.5 spec version setting in UVM-config flow
VIPDISPLAY-2210: 2022-01-10: dp2.0: Case 46582348: Fixed an issue related to
inconsistency assertion check been triggered.
VIPDISPLAY-2209: 2022-01-10: dp2.0: Case 46583325: Fixed an issue where PSR entry exit
is unexpectedly checked by PR.
VIPDISPLAY-2206: 2022-01-04: dp2.0: Case 46580422: Fixed an issue in PR mode where it
is incorrectly checking PSR setup time requirement.
VIPDISPLAY-2183: 2021-12-16: dp2.0: Case 46572108: DPTX can update adjusting driving
setting value when SOMA parameter DpLinkTrnMaxLnkDataBandwidth is set during EQ phase.
VIPDISPLAY-2190: 2021-12-09: edp1.4b: Case 46573721: SpecVersion checking defect is
now fixed.
VIPDISPLAY-2170: 2021-11-19: dp2.0: Case 46568217: The source VIP now writes correct
DPCD register during LTTPR SW RX margin test.
6.1.6 DOCS
VIPDOCS-2185: 2022-01-20: PCIe: Case 46585348: An updated version of the application
note CXL.io/PCIe was delivered with the corrections.

6.1.7 HDL-DH
VIPHDLDH-2201: 2022-02-02: PCIE: Case 46564062: Reduced the severity of
PL_PM_PME_FENCE checker from error to warning.
VIPHDLDH-2154: 2021-12-20: PCIE: Case 46526153: Fixed issue of VIP not recognizing
devices in PCIe topology if BDF was changed before it reaches active state.
VIPHDLDH-2190: 2021-12-05: PCIE: Case 46556169: Fixed issue on Pipe Macro BFM in
which SKP was not being sent on SerDes interface in a scenario with both lane reversal and
upper lanes disabling.
VIPHDLDH-2191: 2021-11-12: PCIE: Case 46555903: Corrected the issue where monitor is
incorrectly transitioning from Configuration.LinkWidth.Start to Configuration.Complete
when a retimer DUT sends delayed TS2.
6.1.8 MIPI
VIPMIPI-7825: 2022-02-10: csi2: Case 46592587: Fixed an issue where checker
CSI2131_CPHY_CSI2_WRONG_NUMBER_OF_FILLER_BYTES was incorrectly failing with CPHY.
VIPMIPI-7782: 2022-02-09: csi2: Case 46588967: Added fix for t_clk_post period
transmission.
VIPMIPI-7770: 2022-02-08: csi2: Case 46587988: Fixed the issue with checker
CSI2133_DPHY_CSI2_WRONG_NUMBER_OF_FILLER_BYTES when lanes are not aligned due to lane
txreadyhs assertion at different time.
VIPMIPI-7753: 2022-02-08: csi2: Case 46586360: Updated CPHY lane distribution function to
divide data considering byte boundary instead of word.
VIPMIPI-7758: 2022-02-08: csi2: Case 46589729: Updated checker
CSI2_FATAL_ERR_CDN_MIPI_PHY607_CPHY_INVALID_T3POST_SEQ to not fail, if received POST2
symbols are not multiples of 7.
VIPMIPI-7767: 2022-02-07: csi2: Case 46587181: Fixed issue of incorrect reporting of
totalActiveLanes when errsotsynchs error is injected in CPHY.
VIPMIPI-7757: 2022-02-07: csi2: Case 46589165: Added latency of one bitclock for checker
to confirm if stopstate and rxtriggeresc change simultaneously.
VIPMIPI-7726: 2022-02-07: i3c: Case 46583879: Added fix for driving PAR0 bit after
command word as 1.
VIPMIPI-7698: 2022-01-18: csi2: Case 46584644: Corrected checker to confirm rxvalidhs
assertion interval is proper or not for reverse HS direction.

VIPMIPI-7713: 2022-01-18: csi2: Case 46585356: Removed checker

CSI2_FATAL_ERR_CDN_MIPI_PHY034_FIRST_HS_DATA_BIT_ON_CLK_LANE_FALLING_EDGE for
reverse HS, as it is not applicable.
VIPMIPI-7694: 2022-01-17: csi2: Case 46584082: Fixed false
BAD_RXACTIVEHS_DEASSERTION_DURING_TRANSACTION checker failure with CPHY fast BTA in
multilane configuration.
VIPMIPI-7701: 2022-01-13: unipro: Case 46584486: Updated all applicable M-PHY capability
attributes.
VIPMIPI-7695: 2022-01-13: dsi: Case 46584027: Fixed checker for t_hfp period in vact line.
VIPMIPI-7711: 2022-01-12: dsi: Case 46585172: Fixed an issue with data reception in CPHY
serial receiver.
VIPMIPI-7699: 2022-01-12: ufs: Case 46580808: Fixed issue that occurred when Start
Address was not getting updated.
VIPMIPI-7700: 2022-01-11: unipro: Case 46583998: PACP_GET/SET retry counter was
incremented falsely and not reset upon detecting PEER_COMMUNICATION_FAILURE condition.
This issue is now fixed.
VIPMIPI-7679: 2022-01-11: mphy: Case 46583706: When ADAPT burst starts from DUT,
DUT TX unit interval after PREPARE is 99.88 ps, slightly deviating from ideal value of 100.1
ps. Due to this, passive monitor VIP samples 4 DIF-Ns instead of 5 after PREPARE ends for
ADAPT burst. Therefore, multiple checkers were incorrectly reported by passive VIP after that.
Fixed the issue by rounding off the division.
VIPMIPI-7575: 2022-01-03: i3c: Case 46564698: Added support to send 00 instead of 0x7E.
VIPMIPI-7644: 2022-01-02: csi2: Case 46579027: All the hard coded Vc's are converted to
user configurable in Triplecheck sequences.
VIPMIPI-7596: 2021-12-24: MIIPIPHY_ACD: Case 46577069: Mapped Hs min and max data
burst coverpoints to covermodel.
VIPMIPI-7629: 2021-12-22: csi2: Case 46577661: Added support to ignore initial junk data on
serial lanes after reset for configured period of time.
VIPMIPI-7652: 2021-12-22: csi2: Case 46580384: Added fix for notification event issue where
clock lane signals are toggled unaligned to bitclock.
VIPMIPI-7653: 2021-12-22: csi2: Case 46580333: Updated
DENALI_CSI2_REG_ApplyNewForceTxStopModeValue register implementation to allow slave drive
forcetxstopstate on lane 0 only.
VIPMIPI-7565: 2021-12-22: csi2: Case 46573620: Fixed to assert rxdetecteobhs when CSI2

layer cannot keep track of packet boundary when erroneous data is received.
VIPMIPI-7632: 2021-12-21: JESD204: Case 46578262: Fixed the issue seen in the reported
data when lane-lane delay is present.
VIPMIPI-7566: 2021-12-10: i3c: Case 46575029: Updated the reason of failure for S5 error.
VIPMIPI-7597: 2021-12-09: csi2: Case 46577247: Corrected checker condition to check
rxactivehs assertion along with rxsynchs/rxskewcalhs to indicate start of HS-transaction.
VIPMIPI-7590: 2021-12-09: csi2: Case 46576621: Added checker to check direction signal is
asserted to 1, on turnrequest assertion only after stopstate is asserted.
VIPMIPI-7561: 2021-12-03: csi2: Case 46574906: The VIP now drives txdatahs on
configured txwordclkhs edge after HS-idle.
VIPMIPI-7567: 2021-12-03: dsi: Case 46575315: Added support to change clock mode using
uvm reconfigure.
VIPMIPI-7574: 2021-12-01: i3c: Case 46557368: Added warning for illegal command code
and command type combination.
VIPMIPI-7460: 2021-11-30: csi2: Case 46569400: Added support for configuration of
t_alp_hs_zero and other timing parameters to minimum and maximum value in terms of t_ui,
when set to 0 from SOMA/config.
VIPMIPI-7553: 2021-11-29: csi2: Case 46572347: Fixed errcontrol error detected during
ALP-ULP on PPI.
VIPMIPI-7552: 2021-11-28: csi2: Case 46571351: Fixed the sampling of direction signal on
bitclock.
VIPMIPI-7539: 2021-11-28: csi2: Case 46572976: Fixed failure of check
CSI2_FATAL_ERR_CDN_MIPI_CSI2352_UNEXPECTED_DATA_RCVD_AFTER_EOTP when VIP was reset
after performing bus turnaround.
VIPMIPI-7455: 2021-11-26: i3c: Case 46570865: Corrected TripleCheck test
cdntcI3cGetDeviceCharTest.
VIPMIPI-7361: 2021-11-22: mphy: Case 46567094: Added same logic as HS_BURST in

PWM_BURST for burst closure on observing long DIF-N when LINE RESET is applied.
VIPMIPI-7443: 2021-11-20: dbi: Case 46571119: Added fix for data width 8 for Type B
interface.
VIPMIPI-7438: 2021-11-19: i3c: Case 46568400: Added fix for HDR DDR mode private
ack/nack.
VIPMIPI-7442: 2021-11-12: csi2: Case 46570528: Fixed issue with checker

CSI2_FATAL_ERR_CDN_MIPI_CSI2134_CPHY_CSI2_NO_SYNC_WORD_IN_HEADER to check for skewed

CPHY lanes.
VIPMIPI-7441: 2021-11-12: csi2: Case 46569184: There will be no change in alpmode signal
when forcetxstopmode is asserted.
6.1.9 MMAV
VIPMMAV-11971: 2022-02-10: HBM3: Case 46590602: Model now uses jitter time to detect
valid start of parity beat in case of jittery clock.
VIPMMAV-11939: 2022-02-07: HBM: Case 46586196: Corrected temp value driving after
refresh interval change by writing temp_reg register.
VIPMMAV-11873: 2022-02-04: DDR5: Case 46583574: Added samplepoint solution to
support per bit hold checking where each bit's minimum requirement comes from different
tdhX parameter, that is, tdh0 .. tdh15.
VIPMMAV-11977: 2022-02-02: lpddr5: Case 46588654: Updated the model to use clock
average instead of last cycle width for tWR check.
VIPMMAV-11889: 2022-01-23: G7: Case 46584443: Updated the model to display a clock
violation message with more clarity, that is, WCK instead of CK.
VIPMMAV-11902: 2022-01-19: lpddr5: Case 46585506: Fixed the model for a false violation
of tCBTRTW timing.
VIPMMAV-11856: 2022-01-04: HBM3: Case 46580589: Updated the model to start parity
burst according to the burst number instead of physical time for read operation.
VIPMMAV-11837: 2021-12-17: lpddr5: Case 46578956: Fixed the model for incorrect tCSLCK
violation.
VIPMMAV-11828: 2021-12-17: HBM3: Case 46576431: Updated the model to bypass PDX
decoding when AWORD MISR mode is ON during initialization sequence after tINIT3.
VIPMMAV-11840: 2021-12-16: ONFI: Case 46580063: Allocated sufficient memory for DBI
pin value buffer.
VIPMMAV-11781: 2021-12-15: GDDR6: Case 46575542: Channel density can now override
in x16 mode.
VIPMMAV-11820: 2021-12-15: Hyperram: Case 46578530: Corrected number of dummy
cycles for variable latency mode.
VIPMMAV-11779: 2021-12-12: ONFI: Case 46575271: Removed unnecessary constraint, the
number of Row can be 4 irrespective of the number of LUNs per target.

VIPMMAV-11740: 2021-12-08: HBM3: Case 46574198: The tool now checks the start of
parity burst according to the burst number instead of the physical time.
VIPMMAV-11689: 2021-11-26: DDR5 DIMM: Case 46571902: While calculating control word
address during RWUPD control word wrote operation, page pointer is now being used.
VIPMMAV-11696: 2021-11-22: GDDR6: Case 46567052: Read burst schedule is now
complete after DQ preamble.
VIPMMAV-11682: 2021-11-22: dram: Case 46572122: Corrected Activate callback for Bank
and Row field values.
VIPMMAV-11656: 2021-11-18: lpddr5: Case 46569983: Updated the model to use the last
read refresh rate index while enabling a new index.
VIPMMAV-11584: 2021-11-17: HBM3: Case 46566591: The WDQS-to-CK training check is
now bypassed if DCA is not supported when clock frequency is less than fCKDCA.
VIPMMAV-11670: 2021-11-17: HBM3: Case 46568710: Corrected checkers for
initWithoutMRDS feature to allow other commands after tINIT5.
VIPMMAV-11675: 2021-11-10: HBM3: Case 46569163: Enabled refresh checks from the first
REFpb command of SID.
6.1.10 PCIe
VIPPCIE-7646: 2022-02-14: gen1/2: Case 46578629: Case 46578629: BFM corrupted TS1
Corrected steps 4, 5, and 6 to not corrupt the TS identifiers for test
LTSSM_ConfigurationLinkwidthStart_to_LoopbackActive_Slave__g1_U1.
VIPPCIE-7449: 2022-02-10: gen1/2: Case 46557939: To determine if there is a bare SKP for
monitors, the data state condition is not used because you cannot guarantee that the DUT is
in a data state until it transmits data.
VIPPCIE-7772: 2022-02-09: gen4: Case 46590285: Fixed issue of serial VIP transmitter
sending repeated bits when SOMA parameter syncBitClkToRefClk is set to 1.
VIPPCIE-6922: 2022-02-07: gen5: Case 46532383: Updated the model to ensure SDS does
not affect control SKP counter.
VIPPCIE-7761: 2022-02-01: gen6: Case 46588074: VIP no longer issues error
PL_PM_UTX_ENTER_L23 if Enter_L23 DLLP and PME_TO_Ack TLP are sent in the same flit.
VIPPCIE-7673: 2022-01-31: gen4: Case 46580404: Fixed Data Object Exchange (DOE)
related SOMA feature selection issue for PureView.
VIPPCIE-7359: 2022-01-27: triplecheck: Case 46553691:
LTSSM_L0_to_L1Entry__RC_ASPM_L10_bfm_reject_substate is not testable with PHY DUT.

VIPPCIE-7706: 2022-01-27: gen6: Case 46588073: Fixed BFM to only generate OHC-A4 for
ID-routed messages that require destination segment and/or PASID.
VIPPCIE-7485: 2022-01-27: triplecheck: Case 46572070: Added missing isTestable
condition.
VIPPCIE-7379: 2022-01-26: triplecheck: Case 46558945: Added new steps to test whether it
can hold at the detect state.
VIPPCIE-7479: 2022-01-23: gen1/2: Case 46569155: Added condition to check and confirm if
the received SKP ordered set after SKP removal results to Bare COM.
VIPPCIE-7691: 2022-01-19: gen6: Case 46586463: Fixed internal interpretation of field
LA[1:0] in OHC-A5 when transmitting Completion TLP to avoid error TL_TLP_OVF_HDR.
VIPPCIE-7478: 2022-01-18: gen5: Case 46572009: Fixed the PIPE MACRO monitor incorrectly
waiting for disabled lanes during receiver detection, causing the monitor to be stuck in the
Detect.Active state.
VIPPCIE-7609: 2022-01-13: ide: Case 46578401: IDE now discards packet instead of
pushing to upper layer at Rx/MonTx side when spec defined errors are detected.
VIPPCIE-7620: 2022-01-11: gen6: Case 46579129: Discarded NOP2 DLLPs from all flits.
VIPPCIE-7679: 2022-01-11: gen6: Case 46584935: Fixed interpretation of last byte enable
field in TLPs to be considered properly for memory transactions with missing OCH-A.
VIPPCIE-7323: 2022-01-11: triplecheck: Case 46562008: Updated triple check test
LTSSM_L0_to_Configuration_LinkWidth_Start__g3_upcfg_LN0_max with respect to serial
configuration to ensure that monitor locks on all lanes in case of changing link widths.
Also, fixed display issue with link width mismatch error to indicate the accurate value of
expected link width.
VIPPCIE-7347: 2022-01-07: triplecheck: Case 46564264: Updated function to change type of
variable from unsigned integer to unsigned integer pointer.
VIPPCIE-7613: 2022-01-04: gen6: Case 46578246: Fixed issue of incorrectly checking flit
SKP parity during TS0 sequence.
VIPPCIE-7654: 2022-01-04: ide: Case 46582004: Fixed IdePrSentCounter/IdeStreamId sv
field update functionality.
VIPPCIE-7490: 2021-12-25: gen6: Case 46575443: When entering Recovery Equalization,
the downstream component sends TS0 with EC=00 at the beginning of Phase 1.
VIPPCIE-7308: 2021-12-21: triplecheck: Case 46559449: Added condition to read the IO
Base and IO Limit register field to initiate IOWr for Type 1 Header function type.

VIPPCIE-7610: 2021-12-21: ide: Case 46577936: Enhanced VIP to not issue error
TL_TLP_PRFX_NOE2E_SUPP if tlpPreE2Esupp SOMA parameter is not set, but Device Capability
2 register is written to support E2E prefixes.
VIPPCIE-7476: 2021-12-17: ide: Case 46568982: Corrected the error message of error
TL_MF_MSGNID.
VIPPCIE-7503: 2021-12-14: gen6: Case 46576153: Enabled the transmission of Link and
Lane number in Hot Reset state in Gen 6.
VIPPCIE-7482: 2021-12-14: gen6: Case 46574079: Only downstream port can be directed to
Hot Reset by higher layer (GotoReset flag). This fix prevents an upstream check if higher layer
directs the physical layer to remain in Hot Reset. This verification causes the EP to move from
Hot Reset before the Hot Reset timeout.
VIPPCIE-7494: 2021-12-14: ide: Case 46575730: Fixed issue of VIP duplicating prefixes, if
more than one is present, when prepending IDE prefix.
VIPPCIE-7486: 2021-12-11: ide: Case 46574599: Fixed setPrefix function of
denaliPcieTlpPacket class of SystemVerilog wrapper.
VIPPCIE-7458: 2021-12-11: gen6: Case 46571429: The transition from Recovery.Idle to

HotReset in Flit Mode happens without transmitting idle data. The monitor should move to
HotReset without waiting for any data to be transmitted.
VIPPCIE-7442: 2021-12-11: ide: Case 46570421: Fixed the issue of VIP applying delay field
twice when transmitting IDE protected TLPs.
VIPPCIE-7491: 2021-12-10: gen6: Case 46575467: Using Cminus2 coefficient all the time
when the index of a local preset requested to the phy belongs to Gen 6 regardless of the
current pipe speed.
VIPPCIE-7461: 2021-12-10: ide: Case 46572206: Fixed the issue that caused VIP to drop the
transmission of packets for traffic classes that were not IDE protected.
VIPPCIE-7448: 2021-12-10: gen4: Case 46571800: Updated model to ensure that TxDeemph is
driven on all lanes at the time of driving TxCompliance to 0 in Detect.
VIPPCIE-6864: 2021-12-10: gen5: Case 46569853: Fixed the following issues in VIP MAC:
* VIP MAC no longer changes the PowerDown signal twice in the same timestamp when there
is a change from P0 state to P2 state with no reset.
* VIP MAC no longer stops responding when L1 Power State is mapped to P2 Power State
and it moves between two power states that do not have PCLK.
* VIP MAC BFM's PowerDown change logic now correctly acknowledges PhyStatus assertion
in P2 when external PCLK is driven.
VIPPCIE-7509: 2021-12-07: gen6: Case 46575464: Using Cminus2 coefficient all the time

when the index of a local preset requested to the phy belongs to Gen 6 regardless of the
current pipe speed.
VIPPCIE-7424: 2021-11-30: gen6: Case 46570043: Updated checker so that TS0 in Phase 3
considers all fields as reserved.
VIPPCIE-6902: 2021-11-29: gen3: Case 46528673: Fixed the issue of missing TX_trans_done
callbacks for posted TLPs.
VIPPCIE-7460: 2021-11-22: gen4: Case 46564763: Added Phase checks for monitor in
Loopback.Entry.Master to confirm if DUT has moved to Equalization. Incase DUT has moved
to Equalization, then monitor will do the same.
VIPPCIE-7318: 2021-11-19: gen3: Case 46562721: Fixed the issue where data structure was
being passed to the function.
VIPPCIE-7363: 2021-11-17: usb4: Case 46564465: Updated the model to go ahead with L1
aspm request considering this request is negotiated and the software PM request is received
before sending an aspm request DLLP.
VIPPCIE-7445: 2021-11-16: gen6: Case 46571355: Extended the changes for HotReset and
disabled to link speed lower than 64GTs (Gen 6).
VIPPCIE-7396: 2021-11-14: gen4: Case 46566844: Allow the active "PIPE MACRO" in P2, to
be woken up by self schedule mechanism. After being woken up, wait for
pciePlLtssmTxIdleMinExpired condition to be true before moving to RecoveryLock.
VIPPCIE-7427: 2021-11-10: gen6: Case 46570014: P2M message is send even when the
current value is same as the previous value to conform with Pipe Spec 6.0 Table 8-4.
VIPPCIE-7431: 2021-11-10: gen6: Case 46569647: PipeMsg signal is now send even when
the value is the same as the previous value.

6.1.11 USB
VIPUSB-3962: 2022-02-09: usb 3.2: Case 46591956: Added fix for Framework layer to clear
pending pipelined acknowledgement packets only for relevant endpoints.
VIPUSB-3843: 2022-02-03: usb 3.2: Case 46572561: Case 46572561: Updated fixed values
for bulk streaming LCStream in status register MOD_ST_ENDP_CURRENT_STREAM_ID.
VIPUSB-3929: 2022-02-03: usb 3.2: Case 46581827: Fixed bulk device in stream state
machine for EOB set on a retried packet.
VIPUSB-3892: 2022-01-17: usb 3.2: Case 46585443: Updated tests
cdnTcUsbTdHubPsmSshUfpE38Test, cdnTcUsbTdHubPsmSshUfpE37Test and
cdnTcUsbTdHubPsmSshUfpE24Test to handle Isochronous Timestamp Packets (ITPs) more
robustly.
VIPUSB-3854: 2021-12-12: triplecheck: Case 46575656: Modified test sequence for checking
.denalirc parameter.
VIPUSB-3845: 2021-12-10: triplecheck: Case 46569639: Fixed test sequence of the state
check for RecoveryActive while UUT transitions to the HotReset state. Also, added checking
for port status fields.
VIPUSB-3820: 2021-11-29: usb 3.2: Case 46562518: The test encounters
DENALI_USB_MSG_PHY_RX_SKP_CTRL_BLOCK_HAS_INVALID_SKPEND_POS error even after receiving
3 LFSR symbols when the SKP Ordered set is less than 24 symbols. Added fix to VIP for
setting the proper FSM state after receiving 3 LFSR symbols.
6.1.12 USB4
VIPUSB4-3221: 2022-02-08: USB4: Case 46580869: Updated the checker for transmission
rule.
VIPUSB4-3246: 2022-02-04: USB4: Case 46586597: Fixed the issue of VIP not sending
TSNOS packet in case of primary lane disabled on run time for RsFec Gen 2.
VIPUSB4-3145: 2021-12-02: USB4: Case 46566570: Fixed Next Capability pointer for router
reg space.
VIPUSB4-3151: 2021-11-17: USB4v2: Case 46571035: PCIe Encapsulation for DLLP with
TLP (>252 Bytes) has been fixed.

Fixed Issues in this Release--6.2 L ist of Enhancements (since VIPCAT release 11.30.080)
6.2 List of Enhancements (since VIPCAT release

11.30.080)
6.2.1 AMBA
VIPAMBA-5627: 2022-02-11: ahb: Case 46583708: Enhanced AHB VIP to send strobe value
at ended burst.
VIPAMBA-5664: 2022-02-03: apb: Case 46590826: Updated the model to trigger checker
CDN_APB_NONFATAL_ERR_CDN_APB025_UNMAPPED_ADDRESS for passive master agent.
VIPAMBA-5611: 2022-02-07: DTI: Added UVM sequence library for connect/disconnect

messages.
VIPAMBA-5554: 2022-02-07: chi: Added support of odd parity check for CHI-F specification.
VIPAMBA-5642: 2022-01-28: ahb: Case 46586046: Enhanced AHB VIP to support the
following data masks:
Also, Datamask values are now reflected in ended burst.

VIPAMBA-5563: 2021-12-17: chi: Case 46575288: Node IDs can be configured as
miscellaneous nodes using following register writes:
agent.regInst.writeReg(DENALI_CHI_REG_MapNodeType, DENALI_CHI_NODETYPE_Mn);
agent.regInst.writeReg(DENALI_CHI_REG_MapNodeID, #NODE_ID);
VIPAMBA-5531: 2021-12-12: ahb: Case 46571892: Updated VIP to check x and z checkers
for active VIP.
VIPAMBA-5561: 2021-12-08: lpi: Added support for Waveform debugger.
VIPAMBA-5466: 2021-11-14: apb: Case 46565516: Added register support to clear memory
when bus reset occurs and enhanced VIP for partial data consistency check support.
6.2.2 BLE
VIPBLE-600: 2022-01-12: TripleCheck: Case 46526495: Added IAL test as per BLE5.2 CTS
SIG test scenarios.

6.2.3 CXL
VIPCXL-986: 2022-02-09: cxl1.1: Case 46552682: Enhanced model to support the CXL TL CM
packet injection directly to CXL TL CM queue from the testbench.
VIPCXL-1059: 2022-02-01: cxl2.0: Case 46572471: Added ALMP flit pkt_data EI support
through Rx CB at ArbMux layer.
VIPCXL-1094: 2022-01-27: cxl2.0: Case 46583908: Added support of trans.log for CXL
TL.mem packets. As of now, CXL TL Mem message is only supported in newly added CXL
tracker log file. You can enable this by doing the following settings in .denalirc.
PcieTransLogFile denali.log
PcieTransLogTypes cxltl
VIPCXL-1068: 2021-12-15: cxl2.0: Case 46572304: Enabled dynamic SOMA reconfiguration

for SOMA parameter CommonClkSupp.
VIPCXL-1062: 2021-11-21: cxl2.0: Added checker
PCIE_TL_NONFATAL_CXL_PM_VDM_PAYLOAD_RSVD_NON_ZERO for CXL PM VDM Payload reserved field
check.
6.2.4 DFI
VIPDFI-1500: 2022-02-13: DFI-DDR5: Updated BFM for DDR5 and LP5 example for memory
storage.
VIPDFI-1402: 2021-12-27: DFI Controller: Case 46570903: Added support to drive DQS/DQ
from MC.
VIPDFI-1202: 2021-11-15: DFI Controller: Case 46538596: Added fields to support
comparison between LP5/LP5 command truth table.
6.2.5 DisplayPort
VIPDISPLAY-2202: 2022-02-02: edp1.4a: Case 46572117: Added Active Source VIP support
of sending Tps1 during PSR Exit when Link Training is bypassed.
VIPDISPLAY-2218: 2022-01-28: dp1.4a: Case 46585930: Added SOMA parameters,
DpAuxManTxPreChargeLenMin/Max, DpAuxManTxPreambleLen and DpAuxManTxSyncLen.

6.2.6 HDL-DH
VIPHDLDH-2200: 2022-01-26: PCIE: Case 46559053: Updated implementation of SerDes
polarity inversion in GEN 3.
VIPHDLDH-2189: 2021-12-06: PCIE: Case 46555617: Added FastTxProcess (bit 12) in
PCIE_REG_DEN_TLQ_CTRL_ST_2 register, with the following effect: TLP is processed as soon as
it arrives at TL (Monitor TX).
VIPHDLDH-2179: 2021-11-17: CAN: Enabled CAN bit timing configuration in UVM run time.
6.2.7 MIPI
VIPMIPI-7776: 2022-02-13: soundwire: Case 46581192: Added enhancement for sending bit
array through VIP instead of char array.
VIPMIPI-7677: 2022-02-08: csi2: Case 46583676: Updated constraint on
constraintPktNumOfPixels.
VIPMIPI-7739: 2022-02-07: i3c: Case 46587186: Modified test

cdnTcI3cIBIDutArbitrationLoseTest as per update in I3c V1.1.1.
VIPMIPI-7737: 2022-02-07: i3c: Case 46588467: Added cdnTcI3cPassiveHotJoinSeq test in

TripleCheck and support in VIP for Passive Hot Join feature.
VIPMIPI-7777: 2022-02-03: i3c: Modified TripleCheck test cdnTcI3cENDXFERCcc_SDRSeq.
VIPMIPI-7709: 2022-02-03: i3c: Case 46584359: Case 46584359: Modified test
cdnTcI3cENDXFERCcc_SDRTest. Added ENDXFER support for Basic V1_1_1.
VIPMIPI-7773: 2022-02-02: spmi: Case 46589901: Added checker

138_SDATA_IS_HIGH_AFTER_COMMAND_SEQ_END to trigger at the end of the command sequence if
SDATA interface line is not released to zero.
VIPMIPI-7728: 2022-01-31: mphy: Case 46585285: Updated the model by adding a condition
that CAPABILITY related bins get hit by reading its value.
VIPMIPI-7738: 2022-01-27: i3c: Updated the model by adding cdnTcI3cPassiveHotJoinSeq
test.
VIPMIPI-7735: 2022-01-24: i3c: Added TC environment for I3c_Basic_V1_1_1 and a test for
ENDXFER CCC.
VIPMIPI-7741: 2022-01-23: i3c: Added basic V1_1_1 support for ENDXFER and in general.
VIPMIPI-7740: 2022-01-23: i3c: Updated the model by adding Passive Hot Join feature.
VIPMIPI-7682: 2022-01-23: unipro: Case 46583457: Added registers

DENALI_UNIPRO_REG_TxUnitIntervalTolerance and
DENALI_UNIPRO_REG_RxUnitIntervalTolerance for unit interval tolerance.
VIPMIPI-7605: 2022-01-17: csi2: Case 46581418: Added support for LP11->LP00->anything

error injection in CPHY.
VIPMIPI-7691: 2022-01-11: MIIPIPHY_ACD: Added logic for word clock when data width is
64-bit.
VIPMIPI-7445: 2021-12-23: MIIPIPHY_ACD: Case 46568465: Added
cdnTcMipiphy_acdCphy_HsTransactionwithRandomTriggers_Test for sending random triggers
with Hs transactions.
VIPMIPI-7666: 2021-12-21: mphy: Added a register to enable SYNC pattern transmission on
RMMI I/F in case of external sync. Until there is no confirmation from M-PHY WG for the
statement "SYNC pattern shall not be transmitted on RMMI I/F regardless of internal or
external sync", default value of this register is set as '1', thus maintaining current behavior.
VIPMIPI-7439: 2021-12-07: soundwire: Case 46567350: Added vip_owner pin in wrappers
and for all data lanes, earlier it was available for only data lane 0.
VIPMIPI-7461: 2021-12-07: csi2: Case 46569908: Added support for OTH-ERR1 error
injection in DPHY.
VIPMIPI-7416: 2021-11-21: i3c: Case 46563407: Added support for CTS related scenarios to
VIP.
VIPMIPI-7428: 2021-11-16: soundwire: Case 46567758: Added config parameter
num_of_supported_sdca_intp_registers to configure the number of supported SDCA
interrupt registers in passive slave VIP instance.
VIPMIPI-7426: 2021-11-12: csi2: Case 46569156: Added notification event for serial ALP
DPHY to indicate detection on control sync.
VIPMIPI-7129: 2021-11-12: csi2: Case 46539137: Added support to insert invalid data
between alp control code and Hs-Trail in DPHY ALP mode.
6.2.8 MMAV
VIPMMAV-11913: 2022-02-11: lpddr5: Case 46586718: Added custom ZQ latch check
support under enableDqZInZqLatChecks SOMA feature.
VIPMMAV-11979: 2022-02-10: HBM3: Case 46590333: Updated the model to trigger an error
when dynamic configuration of timing specification is not correct.
VIPMMAV-11978: 2022-02-10: HBM3: Case 46589076: Updated the model to trigger
UVM_WARNING when configured DCA through MRS command matches the desiredWdqsDCA.

VIPMMAV-11985: 2022-02-10: lpddr5: Case 46591583: Added support for rank to rank
tWCKDQI variation validation.
VIPMMAV-11931: 2022-02-09: HBM3: Case 46587578: Updated the model to store and drive
all 8 UIs during DWORD MISR register mode.
VIPMMAV-11981: 2022-02-08: lpddr5: Case 46589666: Updated the model to validate WCK
frequency based on rank termination settings during Multi-Rank CBT training.
VIPMMAV-11919: 2022-02-04: G7: Case 46587385: WL and RL starts from the rising edge of
the second CK4 cycle as per the latest JEDEC ballots.
VIPMMAV-11980: 2022-02-03: HBM3: Case 46589205: Added feature awordMisrEvenCycles
to check for even cycles during AWORD MISR modes excluding preamble cycle.
VIPMMAV-11959: 2022-01-31: DDR4 DIMM: Case 46589768: Updated RDIMM example to
run with UVM-IEEE.
VIPMMAV-11925: 2022-01-30: HBM3: Case 46587156: Updated HBM3 model for Refresh
Counter Reset whenever refreshchecks is set to 1.
VIPMMAV-11956: 2022-01-27: DDR5: A new feature, customizeRefForEcsOp, has been
introduced which when enabled allows the host to choose the Ref command on which it
wants the DDR5SDRAM to perform ECS operation. When this feature is enabled, for each
Ref command in automatic ECS mode, a callback is sent to the host.
Two new transaction fields related to this feature have been introduced.
1) CA: Indicates the CA bus value for this command.
2) CustomRefEcs: If host wants a particular Ref command to perform ECS operation, it can set
this field to 1 and DDR5SDRAM will perform ECS operation for this Ref command. One of the
unused bits ( CA{6] or CA[7] ) of Ref command can be set to 1 for the Ref command on which
host wants DDR5SDRAM to perform ECS operation in automatic ECS mode. During callback
the CA comparison can be done on host side to set CustomRefEcs field of transaction.
VIPMMAV-11878: 2022-01-24: DDR5: Case 46584273: Updated command-to-command
spacing coverage to exclude NOP and DESELECT commands.
VIPMMAV-11895: 2022-01-23: DDR5 DIMM: Case 46585297: Added TTFT example for
DDR5 RCD model with DRAM model using RDIMM-Verilog-wrapper.
VIPMMAV-11866: 2022-01-23: DDR5: Case 46581176: Added TTFT examples to
demonstrate manual-ECS and automatic-ECS operation.
VIPMMAV-11879: 2022-01-23: DDR5 LRDIMM: Case 46584002: Updated the model to
exclude continuous burst MRR data callbacks from ddr5dimm data callbacks.
VIPMMAV-11834: 2022-01-18: DDR5 DIMM: Case 46579496: Added support for cases when
the DIMM with x4 DRAMs have components mapped to different nibble than the default 1-1

mapping with DQ Maps.

VIPMMAV-11850: 2021-12-17: HBM3: Case 46579872: Updated the HBM3 model to Bypass
Vrefa/Vred training when Mode Register Dump Set (MRDS) command is issued.
VIPMMAV-11739: 2021-12-12: HBM3: Case 46574478: Updated stable clock count
functionality.
VIPMMAV-11647: 2021-12-12: GDDR6: Case 46569410: Per bit skew between DQs is now
as expected.
VIPMMAV-11802: 2021-12-09: HBM3: Case 46577733: The tCKSRX timer and checker has
been marked as obsolete.
VIPMMAV-11686: 2021-12-09: HBM3: Case 46571584: Enabled data corruption for DPAR
signal on setup violation and sent feedback on DERR.
VIPMMAV-11791: 2021-12-06: lpddr4: Case 46575619: Added support for differential checks
error ID.
VIPMMAV-11773: 2021-12-03: HBM3: Case 46574864: Bypassed intra/inter skew violation
for DWORD MISR register mode.
VIPMMAV-11733: 2021-12-02: HBM3: Case 46571095: Updated model to disable clock
tracking when AWORD MISR mode is enabled.
VIPMMAV-11702: 2021-11-28: Case 46571362: Removed pulse width checker for sda on
detecting start after stop.
VIPMMAV-11721: 2021-11-28: flash: Case 46571097: Updated QuadIoReadModeDummyMapping
feature for SOMA part number MX25U25643G and MX25U12832F.
VIPMMAV-11678: 2021-11-22: lpddr5: Case 46572210: Added support for the custom power-
on state using chipStateAfterReset SOMA parameter.
VIPMMAV-11661: 2021-11-18: lpddr5: Case 46571057: Added support for the Ballot 1862.79.
Model now supports following timing parameters (applies when E-DVFSC Mode is enabled):
* tRFCab_enh_dvfsc
* tRFCpb_enh_dvfsc
* tRFMab_enh_dvfsc
* tpbR2pbR_enh_dvfsc
VIPMMAV-11652: 2021-11-18: lpddr5: Case 46569808: Updated with a changes to make
sure model checks for error messages severity only b/w error ids of [1- max numbers of
errors].
VIPMMAV-11667: 2021-11-18: lpddr5: Case 46571052: Changed the tOSCAL time to min.
Even though the Lpddr5 Spec timing definition of tOSCAL mentions it as max, it is a min

timing requirement for the DRAM device.

VIPMMAV-11683: 2021-11-17: HBM3: Case 46572171: Model bypasses validity checkers for
Data pins such as DQ, DBI, ECC, and SEV when inDCMTraining feature is set to 1.
VIPMMAV-11707: 2021-11-17: lpddr5: Case 46572237: Added CS pulse time information in
tXSR_DSM and tXDSM_XP violation error message.
VIPMMAV-11627: 2021-11-17: DDR5: Case 46568718: During automatic ECS mode, the
inter command timing gap from Ref to other commands is now same for both ECS operation
performing refresh command and normal refresh command.
VIPMMAV-11348: 2021-11-16: xSPI: Added support to use specific timings from SFDP dword
or SOMA.
6.2.9 PCIE
VIPPCIE-7789: 2022-02-08: gen6: L0p DLLP fields can now be modified in
DL_RX_queue_enter callback.
VIPPCIE-7622: 2022-02-05: gen5: Case 46578147: Warning added to check if Equalization

Receiver Evaluation Successful is set for upstream while there is a reject of current request for
change of Preset/Coefficient during Phase 2 on course.
VIPPCIE-7612: 2022-02-04: gen6: Case 46578856: Added Gen 6 precoding negotiation.
VIPPCIE-7510: 2022-02-04: gen5: Case 46577719: Now, the receiver detection process will
not depend on TxDetectRx[0] only.
VIPPCIE-7625: 2022-01-26: gen5: Case 46574226: Set SOMA parameter
driveRxElecIdleOnL1Exit to ensure Pipe Macro BFM drives RxElecIdle when existing L1.Idle
-> Recovery.Lock with pipe state in P2.
VIPPCIE-7419: 2022-01-10: ide: Case 46569460: Added support to control K bit toggling for
IDE.
VIPPCIE-7348: 2022-01-06: ide: Case 46563866: Added IDE related information to
PcieTransLogFile if IDE is supported.
VIPPCIE-7489: 2021-12-25: gen6: Case 46575434: When skipping Phase 2 and 3 in

equalization the downstream port now sends 24 TS0.
VIPPCIE-7506: 2021-12-21: ide: Case 46577472: The tool now skips IDE prefix packing and
PR counter processing for TLPs that does not have correct IDE stream ID set.
VIPPCIE-6967: 2021-12-19: gen4: Case 46535023: VIP now ignores junk data coming from
phy to mac on lanes that have seen TS2s with Link and Lane num = PAD while in

Configuration.Complete, indicating they will be disabled shortly.
VIPPCIE-7408: 2021-12-13: ide: Case 46568327: Added new bit trInIdeTxQ in Denali TL
Queue Control/Status 2 register, which is set right before IDE_TX_queue_enter if it is clear,
and is unset right after IDE_TX_queue_exit if the queue becomes empty.
VIPPCIE-7267: 2021-12-13: ide: Case 46558197: Added SOMA parameter
IdePackStreamIdByAddr which when set to 1, enables TX VIP to match Stream ID base on the
Memory address for a given Mem Tlp when exiting UserQueue.
VIPPCIE-6934: 2021-12-07: rnd: Added steps in basic user example for PCIe VIP sysApi
adaptor.
VIPPCIE-7180: 2021-12-06: triplecheck: Case 46547184: Marked triplecheck tests
TXN.06.02_06.MsgD, TXN.RX.INTA, TXN.RX.INTB, TXN.RX.INTC, and TXN.RX.INTD as no_run if
DUT reports unlimited credits for both header and data for posted requests.
VIPPCIE-7042: 2021-12-03: gen3: Case 46542340: VIP now ignores irrelevant data coming
from phy to mac on lanes which has seen TS2s with Link and Lane num = PAD while in
VIPPCIE-7231: 2021-12-02: ide: Case 46555680: Added new opcode for user controlled K bit
toggling.
phy to mac on lanes which have seen TS2s with Link and Lane num = PAD while in
Configuration.Complete, indicating they will be shortly disabled.

VIPPCIE-7474: 2021-11-21: gen6: Case 46573774: Added fix to expect correct number of flits
in Recovery.Idle state.
VIPPCIE-7344: 2021-11-19: ide: Case 46569790: Added callbacks TL_IDE_TX_CIPHER_OP and
TL_IDE_RX_CIPHER_OP.
TL_IDE_TX_CIPHER_OP at Passive Tx side is triggered one TLP at a time after IDE

decryption, which is every time model processes an IDE protected pkt with M bit set.
This callback is triggered after TL_IDE_TX_queue_exit and before pkt gets pushed to
upper TL layer.
TL_IDE_TX_CIPHER_OP at Active Tx side is triggered one TLP at a time after IDE
encryption, which is every time model processes an IDE protected pkt with M bit set.
This callback is triggered after TL_transmit_queue_exit and before
TL_IDLE_TX_queue_enter.
TL_IDE_RX_CIPHER_OP at Active/Passive Rx side is triggered one TLP at a time after IDE

decryption, which is every time model processes an IDE protected pkt with M bit set.
This callback is triggered after TL_IDE_RX_queue_exit and before pkt gets pushed to
upper TL layer (TL_receive_queue_enter).
VIPPCIE-7387: 2021-11-12: gen6: Added new fields in the flit for all DLP0 and DLP1 fields.
VIPPCIE-7346: 2021-11-12: gen3: Case 46564037: With this enhancement, MAC BFM is
now able to start RxMargining requests based on what is seen on pipe message bus. The
parameter marginMacBFMPartialInfoMode must be set on MAC BFM soma file to enable this
behavior. You can add to user queue messages to be written on pipe message bus. These
messages must be transmitted from MAC to PHY and must follow the format defined in the
pipe specification at Table 8-5 Lane Margining at The Receiver Sequences.
6.2.10 PIPEPHY
VIPPIPEPHY-1021: 2022-01-06: PIPEPHY: Case 46523427: Added RateScaleDown feature to
support running USB at lower speed.

6.2.11 USB
VIPUSB-3928: 2022-02-09: usb 2.0: Case 46587454: Updated the model for VIP to respect
IPG requirements when sending packets in USB2 test mode for mode type 'Packet'.
VIPUSB-3931: 2022-02-09: eUSB: Case 46587294: Updated the model for eUSB2 host
repeater VIP to detect disconnect in SOF even when dribble bits are received.
VIPUSB-3949: 2022-02-07: triplecheck: Added TripleCheck PTM tests relevancy with
!USB30 and Usb3PTMCapable.
VIPUSB-3934: 2022-02-01: triplecheck: Tests are now marked irrelevant if the device (for host
as dut) or passive agent (for device as dut/hub as dut) does not have bulk stream endpoints.
VIPUSB-3932: 2022-01-31: triplecheck: Model has been updated for Bulk unidirectional
endpoints.
VIPUSB-3866: 2022-01-10: triplecheck: Case 46575998: Modified the test sequence for
reducing the severity of checker.
VIPUSB-3886: 2022-01-06: triplecheck: Case 46579746: Reduced the severity of the
expected checker in the triplecheck test.
VIPUSB-3838: 2021-12-21: eUSB: Case 46562900: Updated eUSB2 TripleCheck to provide
user configurable delay before issuing Resume/RemoteWake when exiting low power state.
VIPUSB-3848: 2021-12-12: usb 3.2: Case 46573046: Fixed an unexpected exit of the tool
when user packed in queued in USB3 device VIP for endpoint with active stream ID.
VIPUSB-3855: 2021-12-09: triplecheck: Case 46575794: Corrected the issue in the
TripleCheck test.
VIPUSB-3847: 2021-11-29: usb 3.2: Case 46562517: VIP change for interpretation of
received symbols at 8BusQueue after rxDataValid signal transition takes place from 0->1.
VIPUSB-3291: 2021-11-24: usb 3.2: Updated Local Loopback feature in VIP.
VIPUSB-3793: 2021-11-19: usb 3.2: Case 46554774: Fixed the corner cases for lane
mismatch for Gen1x2 as specified in the regression test location.
6.2.12 USB4
VIPUSB4-3199: 2021-12-20: USB4: Case 46577004: Updated the model to support
reconfiguration of HIF rings.
VIPUSB4-3181: 2021-12-05: USB4v2: Case 46574428: DLLP TLP packet corruption is now
fixed.

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VIP Catalog Release Information

Product Version 11.3

Document Last Updated: February 15, 2022

All other trademarks are the property of their respective holders.

February 2022 3 Product Version 11.3

3.4 New in Simulation VIP 25

February 2022 4 Product Version 11.3

February 2022 5 Product Version 11.3

February 2022 6 Product Version 11.3

$DENALI An environment variable that points to $CDN_VIP_ROOT/tools/denali.

Bus Functional Verification software that emulates a given device or protocol.

February 2022 7 Product Version 11.3

Data-Driven The Data-Driven Verification API (DDVAPI) is an extension to the

Design Under Test This is the device being verified.

SOMA Specification of Model Architecture. SOMA is a Cadence-standard format

1.3 Customer Support

February 2022 8 Product Version 11.3

1.4 Training Videos

February 2022 9 Product Version 11.3

2.1 Verification IP Catalog

February 2022 10 Product Version 11.3

2.2 Introduction to Virtual Protocols

2.2.1 Introduction to Virtual Protocols for Palladium and Protium

2.2.1.1 ​Directory Structure

Release Naming Convention of <vp_root> Path Example Path Version

Official pdapp<version>/<pdapp_version>/vp pdapp21.07/21.07.000.s000/vp 21.07

Official pdapp<version>/<pdapp_version>/vp_<vipcat_version> pdapp21.07/21.07.000.s000/vp_11.30.081-s 21.07_vp_11.30.081-

Nightly pdapp<version>/<pdapp_version>/vp_<date> pdapp21.07/21.07.000.s000/vp_15_Feb_2022 21.07_vp_11.30.081-

February 2022 11 Product Version 11.3

following directory is created:

February 2022 12 Product Version 11.3

2.2.1.2 Platform Support

Platform Run compiler​ ABI11​ OS Version​ C++ C Location in <vp_root>​

2.2.1.3 ​VIPCAT Compatibility

February 2022 13 Product Version 11.3

2.2.1.4 Download Options for the VP Package

2.3 Using Save and Restore

February 2022 14 Product Version 11.3

Environment Structure Supported Denalirc Checkpoint Parameter

Questa + Verilog or SystemVerilog Testbench VIP (e core) No NA

Questa + Specman Testbench + VIP (e core) No NA

VCS ignores checkpoint variable setting.

Environment Structure Supported Denalirc Checkpoint Parameter

VCS + Verilog or SystemVerilog Testbench VIP (C core) Yes Ignored

VCS + Verilog or SystemVerilog Testbench VIP (e core) Yes Ignored

VCS + Specman Testbench + VIP (C core) Yes Ignored

VCS + Specman Testbench + VIP (e core) Yes Ignored

Do not enable the checkpoint variable.

Environment Structure Supported Denalirc Checkpoint Parameter

Xcelium + Verilog or SystemVerilog Testbench VIP (C core) Yes checkpoint 0

Xcelium + Verilog or SystemVerilog Testbench VIP (e core) Yes checkpoint 0

Xcelium + Specman Testbench + VIP (C core) Yes checkpoint 0

Xcelium + Specman Testbench + VIP (e core) Yes checkpoint 0

2.4 Verification IP Compatibility and Dependencies

2.4.1 Supported Simulators

February 2022 15 Product Version 11.3

Tested Simulators Version

XCELIUM 19.03 and later

VCS 2017.03 and later

2.2.1.1 Directory Structure

Platform Run compiler ABI11 OS Version C++ C Location in <vp_root>

2.2.1.3 VIPCAT Compatibility

3.1 New Products

3.2 Update on Licensing

3.3 New in Memory Models

3.4 New in Simulation VIP