Islamic University of Gaza Digital Communications Lab.

Faculty of Engineering Prepared by:

Electrical Department Eng. Mohammed K. Abu Foul

Experiment # (8)
FSK Demodulator

Experiment Objectives:
1. To understand the operation theory of FSK demodulator.
2. To implement the FSK detector circuit by using PLL.
3. To understand the operation theory of comparator by using operational amplifier as
voltage level converter.

Experiment theory:

In experiment 7 we use FSK modulator for long distance communication, which the volatfe
level of digital signal has been converted to frequency. Therefore, at the receiver, we have to
recover the FSK signal to digital signal, that means the frequency should be converted back to
voltage. We use phase locked loop (PLL) as FSK demodulator. PLL is a kind of automatic
tracking system, which is able to detect the input signal frequency and phase. PLL is widely
used in wireless applications, such as AM demodulator, FM demodulator, frequency selector
and so on. In the digital communications, various types of digital PLLs are developed. Digital
PLL is very useful in carrier synchronization, bit synchronization and digital demodulation.

1. Asynchronous FSK detector:

The block diagram of asynchronous FSK detector is shown in figure 8.1. In figure 8.1, we
can see that at the receiver parts, there are two low-pass filters, which their center frequencies
are ωc+ωD and ωc – ωD, respectively. By using the characteristic of the filter, we can obtain the
ωc+ωD (Digital signal represents as 1) and ωc – ωD (Digital signal represents as 0). Then
combine the digital signal after demodulation, finally, the original digital signal can be obtain at
the output terminal. Since the fixed frequency deviation of the carrier signal (ωc) is quite small,
therefore, the usage of sharp filter is its disadvantage.

Figure 8.1 Block diagram of asynchronous FSK detector.

 2. Synchronous FSK detector:
Let the received data signal VFSK(t) multiply by a local oscillation (LO) signals cos(ωc+ωD)t
or cos(ωc-ωD)t as shown in equations (8.1) and (8.3). Then we can obtain cos[2(ωc+ωD)]t,
which the digital signal frequency is represented as 1 or cos[2(ωc-ωD)]t, which the digital signal
frequency is represented as 0. After that by using the filter to remove the second order
harmonics and DC voltage, then we can obtain the original digital signal as shown in figure 8.2.

In this section, we utilize the theory of mathematic to solve the FSK demodulation as
shown in equation (8.1). The synchronous FSK detector needs two LO oscillators, which the
LO frequencies are ωc-ωD and ωc+ωD, respectively, as shown in figure 8.2. When the received
signal is Acos(ωc+ωD)t, then we get:

By using a filter to remove all the unwanted signal in equation (8.1), then the represented
output signal is 1 and we can rewritten equation (8.1) as follow:

Where:
ωc: carrier frequency.
ωD: Signal frequency.

When the received signal is Acos(ωc-ωD)t, then we get:

By using a filter to remove all the unwanted signal in equation (8.3), then the represented
output signal is 0 and we can rewritten equation (8.1) as follow:
Generally, phase locked loop (PLL) can be divided into 3 main parts, which are the phase
detector (PD), loop filter (LF) and voltage controlled oscillator (VCO). The block diagram of
PLL is shown in figure 8.3.

In figure 8.3, when the input signal frequency changes, the output signal of the phase
detector will change and so as well as the output voltage. We can use this characteristics to
design the FSK demodulator. Let the FSK signal frequencies as f1 and f2, then these signals are
inputted to the input terminal of figure 8.3. When the input signal frequency is f1, the output
voltage will be V1. When the input signal frequency is f2, the output voltage is V2. At this
moment, we have converted the frequency to voltage. If we add a comparator at the output
terminal of PLL, the reference voltage will lie between V1 and V2, then at the output terminal
of comparator, we are able to obtain the digital signal, which is the demodulated FSK signal.

Figure 8.2 Block diagram of synchronous FSK detector.

In this experiment, we implement the FSK demodulator by using LM565 PLL as shown
in figure 8.4. The operation frequency of LM565 PLL is below 500 kHz and the internal circuit
diagram is shown in figure 8.4. It includes phase detector, voltage controlled oscillator and
amplifier.
The phase detector is a double-balanced modulator type circuit and the VCO is integrated
Schmitt circuit.

Figure 8.3 Block diagram of PLL

 Figure 8.4 Circuit diagram of FSK demodulator.

Pin 1 is connected to negative voltage supply, -5 V. Pins 2 and 3 are connected to the input
signals, but normally pin 3 will connect to ground. If pins 4 and 5 are connected to frequency
multiplier, then various multiplications of frequencies can be obtained. In this experiment, we
need not use the frequency multiplier; therefore, these two pins are shorted. Pin 6 is the
reference voltage output. The internal resistor (Rx) of pin 7 and the external capacitor (C3)
comprise a loop filter. Pin 8 is connected to timing resistor (VR1). Pin 9 is connected to timing
capacitor (C2). Pin 10 the positive voltage supply +5 V of LM565. The important parameters of
LM565 PLL circuit design are as follow:

1) The free-Running Frequency of LM565

When LM565 without any input signal, the output signal of VCO is called free0running
frequency. The C2 is timing capacitor and the variable resistor VR1 is timing resistor. The free-
running frequency (fo) of VCO of the LM565 is determined by C2 and VR1. The expression is:

2) The locked Range of LM565

When the PLL is in locked condition, if the frequency of the input signal (fi) deviates from
fo, then the PLL will remain in the locked condition. When fi reaches a certain frequency,
which the PLL is not able to lock, then the difference between fi and fo is called the locked
range.

The locked range of LM565 can be expressed as:

 3) The Capture Range of LM565
The initial mode of PLL is in unlocked condition, then the frequency of the input signal (fi)
will come near to fo. When fi reaches a certain frequency, the PLL will be in locked condition.
At this moment, the difference between fi and fo is called the capture range. The captured range
of LM565 can be expressed as:

In figure 8.4, pin 7 of LM565 is connected to R3, R4, R5, C3, C4 and C5 to comprise a
low-pass filter. The objective is to remove the unwanted signal, which will cause the
comparator produce incorrect action. µA741 is the comparator and its reference voltage is
inputted at pin 6 of LM565. The output voltage of LM565 will pass through µA741 and D1 to
obtain the output voltage of digital signal of TTL level.
Experiment items:
Experiment 1: XR2206 FSK demodulator
1. Refer to the circuit diagram in figure 8.4 or figure DCS 14.1 on ETEK DCS-6000-07
module. Without adding any signal at the input terminal (FSK I/P), then by using
oscilloscope, observe on the VCO output (TP1) of LM565, adjust variable resistor VR1
so that the free-running frequency of LM565 operates at 1170 Hz.
2. At the input terminal (FSK I/P) of figure DCS14.1, input 4 V amplitude and 870 Hz
sine wave frequency. By using oscilloscope and switching to DC channel, then observe
on the output signal waveform of FSK I/P, TP1, charge and discharge test point (TP2),
low-pass loop circuit 1 (TP3), low-pass loop circuit 2 (TP4), low-pass loop circuit 3
(TP5), low-pass loop circuit 4 (TP6), reference voltage of the comparator (TP7), output
terminal of the comparator (TP8) and data signal output port (Data O/P). Finally, record
the measured results in table 8.1.
3. At the input terminal (FSK I/P) of figure DCS14.1, input 4 V amplitude and 1370 Hz
sine wave frequency. Repeat step 2 and record the measured results in table 8.2.
4. Refer to figure 7.3 with R1= 7.5 kΩ and R5= 15 kΩ or refer to figure DCS 13.1 on
ETEK DCS-6000-07 module. Let J2 and J4 be open circuit, J3 and J5 be short circuit.
5. At the data signal input terminal (Data I/P), of figure DCS13.1, input 5 V amplitude,
150 Hz TTL signal.
6. Connect the modulated FSK signal (FSK O/P) of figure DCS13.1 to the input terminal
(FSK I/P) of figure DCS14.1. By using oscilloscope, observe on the output signal
waveform of TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8 and Data O/P. Finally, record
the measured results in table 8.3.
7. According to the input signal in table 8.3, repeat step 5 to step 6 and record the
measured results in table 8.3.
Experiment 2: LM566 FSK demodulator
1. Refer to the circuit diagram in figure 7.6 or figure DCS13.2 on ETEK DCS-6000-07
module.
2. From figure DCS13.2, let the two terminal of I/P be short circuit and J1 be open circuit,
i.e. at the data signal input terminal (Data I/P), input 0 V DC voltage. By using
oscilloscope, observe on the output signal waveform of the VCO output port (TP1) of
LM566. Slightly adjust VR1 so that the frequency of TP1 is 1370 Hz. Again let the data
signal input terminal (Data I/P) be open circuit and J1 be short crcuit, i.e. input 5 V DC
voltage to the data signal input terminal (Data I/P). By using oscilloscope, observe on
the output signal waveform of the VCO output port (TP1) of LM566. Slightly adjust
VR1 so that the frequency of TP1 is 870 Hz.
3. At the data signal input terminal (Data I/P), of figure DCS13.2, input 5 V amplitude,
150 Hz TTL signal. Connect the modulated FSK signal (FSK O/P) of figure DCS13.2
to the input terminal (FSK I/P) of figure DCS14.1. By using oscilloscope, and
switching to DC channel, observe on the output signal waveform of TP1, TP2, TP3,
TP4, TP5, TP6, TP7, TP8 and Data O/P. Finally, record the measured results in table
8.4.
4. According to the input signal in table 8.4, repeat step 3 and record the measured results
in table 8.4.
Measured results:
Table 8-1 Measured results of FSK demodulator (Vin=4V)

Output signal waveforms

Carrier signal frequencies
Data I/P TP1

TP2 TP3

TP4 TP5

870 Hz

TP6 TP7

TP8 Data O/P

NOTE:
Table 8-2: Repeat table 8-1 but with carrier frequency 1370 Hz.
Table 8-3 Measured results of FSK demodulator by using 2206 IC.
(J3, J5 SC; J2, J4 OC)

Output signal waveforms

Carrier signal frequencies
Data I/P TP1

TP2 TP3

TP4 TP5
Vp=5V
150 Hz

TP6 TP7

TP8 Data O/P

NOTE:
Repeat table 8-3 with carrier frequency 200 Hz.
Table 8-4 Measured results of FSK demodulator by using LM566.

Output signal waveforms

Carrier signal frequencies
Data I/P TP1

TP2 TP3

TP4 TP5
Vp=5V
150 Hz

TP6 TP7

TP8 Data O/P

NOTE:
Repeat table 8-3 with carrier frequency 200 Hz.