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BEC306C - Computer Organization and Architecture Regulations-2022CBSE(scheme) Module – 1: Basic Structures of Computer

COMPUTER ORGANIZATION AND ARCHITETURE

Subject Code:BEC302

Module - 1

Basic Structure of Computers: Computer Types, Functional Units, Basic Operational Concepts,
Bus Structures, Performance – Processor Clock, Basic Performance Equation.

Machine Instructions and Programs: Numbers, Arithmetic Operations and Characters, IEEE
standards for Floating points Numbers, Memory Location and Addresses, Memory Operations,
Instructions and Instruction Sequencing.

Module - 2
Addressing Modes, Assembly Language, Basic Input and Output Operations, Stacks and Queues,
Subroutines, Additional Instructions.

Module - 3
Input/Output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling
and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Direct Memory
access.

Module - 4
Memory System: Basic Concepts, Semiconductor RAM Memories-Internal organization of
memory chips, Static memories, Asynchronous DRAMS, Read Only Memories, Cache Memories,
Virtual Memories, Secondary Storage.

Module - 5
Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction,
Multiple Bus Organization, Hard-wired Control, Microprogrammed Control.

Text Books:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky: Computer Organization, 5th Edition,
Tata McGraw Hill, 2002.
BEC306C- Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of
Computer

Module - 1

Basic Structure of Computers: Computer Types, Functional Units, Basic Operational Concepts,
Bus Structures, Performance – Processor Clock, Basic Performance Equation

Machine Instructions and Programs: Numbers, Arithmetic Operations and Characters, IEEE
standards for Floating points Numbers, Memory Location and Addresses, Memory Operations,
Instructions and Instruction Sequencing,

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BEC306C - Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of Computer

MODULE – 1 – BASIC STRUCTURE OF COMPUTERS

Computer Types

A computer can be defined as a fast electronic calculating machine that accepts the (data) digitized
input information process it as per the list of internally stored instructions and produces the resulting
information.
 List of instructions are called programs.
 Internal storage is called computer memory.

The different types of computers are

1. Personal computers: - This is the most common type found in homes, schools, Business
offices etc., It is the most common type of desk top computers with processing and storage
units along with various input and output devices.
2. Note book computers: - These are compact and portable versions of PC
3. Work stations: - These have high resolution input/output (I/O) graphics capability, but
with same dimensions as that of desktop computer. These are used in engineering
applications of interactive design work.
4. Enterprise systems: - These are used for business data processing in medium to large
corporations that require much more computing power and storage capacity than work
stations. Internets associated with servers have become a dominant worldwide source of
all types of information.
5. Super computers: - These are used for large scale numerical calculations required in the
applications like weather forecasting etc.,

Functional Unit of Computer:

A computer consists of five functionally independent main parts input, memory, arithmetic
logic unit (ALU), output and control unit.

INPUT ALU

MEMORY
CONTROL
OUTPUT UNIT

I/O PROCESSOR

Fig a: Functional units of computer

Input device accepts the coded information as source program i.e. high level language. This is either stored
in the memory or immediately used by the processor to perform the desired operations. The program
stored in the memory determines the processing steps. Basically the computer converts one source
program to an object program. i.e. into machine language.

Finally the results are sent to the outside world through output device. All of these actions are coordinated
by the control unit.

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BEC306C- Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of Computer

Input Unit
The source program/high level languages program/coded information/simply data is fed to a
computer through input devices keyboard is a most common type. Whenever a key is pressed, one
corresponding word or number is translated into its equivalent binary code over a cable & fed either
to memory or processor.

Examples: Joysticks, trackballs, mouse, scanners etc are other input devices.

Memory Unit
It is used to store the programs and data. It is basically to two types

1. Primary memory
2. Secondary memory

Primary memory: -
It is the one exclusively associated with the processor and operates at the electronics
speeds and programs must be stored in this memory while they are being executed.

 The memory contains a large number of semiconductors storage cells. Each is

capable of storing one bit of information.
 These are processed in a group of fixed site called word.
 To provide easy access to a word in memory, a distinct address is associated
with each word location.
 Addresses are numbers that identify memory location.
 Number of bits in each word is called word length of the computer.
 Programs must reside in the memory during execution.
 Instructions and data can be written into the memory or read out under the control
of processor.
 Memory in which any location can be reached in a short and fixed amount of time
after specifying its address is called random-access memory (RAM).
 The time required to access one word in called memory access time.
 Memory which is only readable by the user and contents of which can’t be altered is
called read only memory (ROM) it contains operating system.
 Caches are the small fast RAM units, which are coupled with the processor and are
often contained on the same IC chip to achieve high performance.
 Although primary storage is essential it tends to be expensive.

2. Secondary memory: - Is used where large amounts of data & programs have to be stored,
particularly information that is accessed infrequently.

Examples: - Magnetic disks & tapes, optical disks (i.e. CD-ROM’s), floppies etc.,

Arithmetic logic unit (ALU):-

 Most of the computer operators are executed in ALU of the processor like addition,
subtraction, division, multiplication, etc.
 The operands are brought into the ALU from memory and stored in high speed storage
elements called register. Then according to the instructions the operation is performed in
the required sequence.
 The control and the ALU are many times faster than other devices connected to a computer
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BEC306C - Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of Computer

system.
 This enables a single processor to control a number of external devices such as key boards,
displays, magnetic and optical disks, sensors and other mechanical controllers.

Output unit:-
These actually are the counterparts of input unit. Its basic function is to send the processed results to the
outside world.

Examples: Printer, speakers, monitor etc.

Control unit:-
It effectively is the nerve center that sends signals to other units and senses their states. The actual timing
signals that govern the transfer of data between input unit, processor, memory and output unit are
generated by the control unit.

Basic operational concepts

To perform a given task an appropriate program consisting of a list of instructions is stored in the
memory. Individual instructions are brought from the memory into the processor, which executes the
specified operations. Data to be stored are also stored in the memory.

Examples: - Add LOCA, R0

This instruction adds the operand at memory location LOCA, to operand in register R 0 & places the sum
into register.

This instruction requires the performance of several steps,

 First the instruction is fetched from the memory into the processor.
 The operand at LOCA is fetched and added to the contents of R0
 Finally the resulting sum is stored in the register R0

The preceding ADD instruction combines a memory access operation with an ALU Operations.

In some other type of computers, these two types of operations are performed by separate
instructions for performance reasons.
Load LOCA, R1

Add R1, R0

Transfers between the memory and the processor are started by sending the address of the memory
location to be accessed to the memory unit and issuing the appropriate control signals. The data are then
transferred to or from the memory.

The fig shows how memory & the processor can be connected. In addition to the ALU & the control
circuitry, the processor contains a number of registers used for several different purposes.

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BEC306C- Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of Computer

Fig b: Connections between the processor and the memory

The instruction register (IR):- Holds the instructions that are currently being executed. Its
output is available for the control circuits which generates the timing signals that control the
various processing elements in one execution of instruction.

The program counter (PC):-

This is another specialized register that keeps track of execution of a program. It contains the
memory address of the next instruction to be fetched and executed.

Besides IR and PC, there are n-general purpose registers R0 through Rn-1. The other two
registers which facilitate communication with memory are: -
1. MAR – (Memory Address Register):- It holds the address of the location to be accessed.
2. MDR – (Memory Data Register):- It contains the data to be written into or read out
from the address location.

Operating steps are

1. Programs reside in the memory & usually get these through the Input unit.
2. Execution of the program starts when the PC is set to point at the first instruction of
the program.
3. Contents of PC are transferred to MAR and a Read Control Signal is sent to the memory.
4. After the time required to access the memory elapses, the address word is read out of
the memory and loaded into the MDR.
5. Now contents of MDR are transferred to the IR & now the instruction is ready to be
decoded and executed.
6. If the instruction involves an operation by the ALU, it is necessary to obtain the required
operands.
7. An operand in the memory is fetched by sending its address to MAR & Initiating a read
cycle.
8. When the operand has been read from the memory to the MDR, it is transferred from MDR
to the ALU.
9. After one or two such repeated cycles, the ALU can perform the desired operation.

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BEC306C - Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of Computer

10. If the result of this operation is to be stored in the memory, the result is sent to MDR.
11. Address of location where the result is stored is sent to MAR & a write cycle is initiated.
12. The contents of PC are incremented so that PC points to the next instruction that is to
be executed.

Normal execution of a program may be preempted (temporarily interrupted) if some devicesrequire urgent
servicing, to do this one device raises an Interrupt signal.

An interrupt is a request signal from an I/O device for service by the processor. The processorprovides
the requested service by executing an appropriate interrupt service routine.

The Diversion may change the internal stage of the processor its state must be saved in the memory
location before interruption. When the interrupt-routine service is completed the state ofthe processor is
restored so that the interrupted program may continue.

Bus structure
The simplest and most common way of interconnecting various parts of the computer, to achieve a
reasonable speed of operation, a computer must be organized so that all its units can handle one full word
of data at a given time. A group of lines that serve as a connecting port for several devices is called a bus.

In addition to the lines that carry the data, the bus must have lines for address and controlpurpose.
Simplest way to interconnect is to use the single bus as shown

Fig c: Single bus structure

Since the bus can be used for only one transfer at a time, only two units can actively use the bus at
any given time. Bus control lines are used to arbitrate multiple requests for use of one bus.

Single bus structure is

 Low cost
 Very flexible for attaching peripheral devices

Multiple bus structure certainly increases the performance but also increases the costsignificantly.

All the interconnected devices are not of same speed & time leads to a bit of a problem. This is solved by
using cache registers (i.e. buffer registers). These buffers are electronic registers of small capacity when
compared to the main memory but of comparable speed.
The instructions from the processor at once are loaded into these buffers and then the complete
transfer of data at a fast rate will take place.

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BEC306C- Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of Computer

System Software
If a user wants to enter and run an application program, he/she needs a System Software. System
Software is a collection of programs that are executed as needed to perform functions such as:

 Receiving and interpreting user commands

 Entering and editing application programs and storing then as files in secondary storage
devices
 Running standard application programs such as word processors, spread sheets, gamesetc…
 Operating system - is key system software component which helps the user to exploit the
below underlying hardware with the programs.

USER PROGRAM and OS ROUTINE INTERACTION

Let’s assume computer with 1 processor, 1 disk and 1 printer and application program is in
machine code on disk. The various tasks are performed in a coordinated fashion, which is called
multitasking. t0, t1 …t5 are the instances of time and the interaction during various instances as
given below:

t0: the OS loads the program from the disk to memoryt1:

program executes
t2: program accesses disk
t3: program executes some more
t4: program accesses printer
t5: program terminates

Figure d: User program and OS routine sharing of the processor

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BEC306C - Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of Computer

Performance

The most important measure of the performance of a computer is how quickly it can execute programs.
The speed with which a computer executes program is affected by the design of its hardware. For best
performance, it is necessary to design the compiles, the machine instruction set, and the hardware in a
coordinated way.

The total time required to execute the program is elapsed time is a measure of the performance of the
entire computer system. It is affected by the speed of the processor, the disk and the printer. The time
needed to execute instruction is called the processor time.

Just as the elapsed time for the execution of a program depends on all units in a computer system, the
processor time depends on the hardware involved in the execution of individual machine instructions.
This hardware comprises the processor and the memory which are usually connected by the b us as
shown in the fig c.

Fig. e. The processor cache.

The pertinent parts of the fig. c are repeated in fig. e which includes the cache memory as part ofthe
processor unit.

Let us examine the flow of program instructions and data between the memory and the processor. At the
start of execution, all program instructions and the required data are stored in the main memory. As the
execution proceeds, instructions are fetched one by one over the bus into the processor, and a copy is
placed in the cache later if the same instruction or data item is needed a second time, it is read directly
from the cache.
The processor and relatively small cache memory can be fabricated on a single IC chip. Theinternal speed
of performing the basic steps of instruction processing on chip is very high and is considerably faster
than the speed at which the instruction and data can be fetched from the main memory. A program will
be executed faster if the movement of instructions and data between the main memory and the processor
is minimized, which is achieved by using the cache.

For example: - Suppose a number of instructions are executed repeatedly over a short period of time as
happens in a program loop. If these instructions are available in the cache, they can be fetched quickly
during the period of repeated use. The same applies to the data that are used repeatedly.

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BEC306C- Computer Organization and Architecture Regulations2022CBSE(scheme) Module – 1: Basic Structures of Computer

Processor clock: -
 Processor circuits are controlled by a timing signal called clock.
 The clock designer the regular time intervals called clock cycles.
 To execute a machine instruction the processor divides the action to be performed into a
sequence of basic steps that each step can be completed in one clock cycle.
 The length “P” of one clock cycle is an important parameter that affects the processor
performance.
Therefore the clock rate is defined a s the inverse of the length of one clock cycle.

R = 1/P

This is measured in Cycles per Second; called hertz (Hz).

Processor used in today’s personal computer and work station has a clock rates that rangefrom a
few hundred million to over a billion cycles per second.

Basic performance equation

We now focus our attention on the processor time component of the total elapsed time. Let ‘T’ be the
processor time required to execute a program that has been prepared in some high-level language.
The compiler generates a machine language object program that corresponds to the source program.
Assume that complete execution of the program requires the execution of N machine cycle language
instructions. The number N is the actual number of instruction execution and is not necessarily equal
to the number of machine cycle instructions in the object program. Some instruction may be
executed more than once, which in the case for instructions inside a program loop others may not
be executed all, depending on the input data used.

Suppose that the average number of basic steps needed to execute one machine cycle instructionis
S, where each basic step is completed in one clock cycle. If clock rate is ‘R’ cycles per second, the
program execution time is given by

NS
T
R
This is often referred to as the basic performance equation.

We must emphasize that N, S & R are not independent parameters changing one may affect another.
Introducing a new feature in the design of a processor will lead to improved performanceonly if the
overall result is to reduce the value of T.

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BEC306C- Computer Organization and Architecture Module – 1: Machine Instruction & Programs

MODULE 1 - MACHINE INSTRUCTIONS & PROGRAMS

MEMORY-LOCATIONS & ADDRESSES

 Memory consists of many millions of storage cells (flip-flops).
 Each cell can store a bit of information i.e. 0 or 1 (Figure 2.1).
 Each group of n bits is referred to as a word of information, and n is called the word
length.
 The word length can vary from 8 to 64 bits.
 A unit of 8 bits is called a byte.
 Accessing the memory to store or retrieve a single item of information (word/byte)
requires distinct addresses for each item location. (It is customary to use numbers from
0 through 2k-1 as the addresses of successive-locations in the memory).
 If 2k = no. of addressablelocations; then 2k addresses constitute the address-space of
the computer.
 For example, a 24-bit address generates an address-space of 224 locations (16 MB).

BYTE-ADDRESSABILITY
 In byte-addressable memory, successive addresses refer to successive byte locations in
thememory.
 Byte locations have addresses 0, 1, 2. . . . .
 If the word-length is 32 bits, successive words are located at addresses 0, 4, 8. . with
each word having 4 bytes.

BIG-ENDIAN & LITTLE-ENDIAN ASSIGNMENTS

There are two ways in which byte-addresses are arranged (Figure 2.3).
1. Big-Endian: Lower byte-addresses are used for the more significant bytes of the word.
2. Little-Endian: Lower byte-addresses are used for the less significant bytes of the word

In both cases, byte-addresses 0, 4, 8 are taken as the addresses of successive words in the
memory.

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BEC306C- Computer Organization and Architecture Module – 1: Machine Instruction & Programs

Consider a 32-bit integer (in hex): 0x12345678 which consists of 4 bytes: 12, 34, 56, and 78.

 Hence this integer will occupy 4 bytes in memory.

 Assume, we store it at memory address starting 1000.
 On little-endian, memory will look like
Address Value
1000 78
1001 56
1002 34
1003 12

 On big-endian, memory will look like

Address Value
1000 12
1001 34
1002 56
1003 78

WORD ALIGNMENT
Words are said to be aligned in memory if they begin at a byte-address that is a multiple of the
number of bytes in a word.

For example,
 If the word length is 16(2 bytes), aligned words begin at byte-addresses 0, 2, 4 . . . . .
 If the word length is 64(2 bytes), aligned words begin at byte-addresses 0, 8, 16 . . . . .
 Words are said to have Unaligned Addresses, if they begin at an arbitrary byte-
address.

ACCESSING NUMBERS, CHARACTERS & CHARACTERS STRINGS

 A number usually occupies one word. It can be accessed in the memory by specifying its
word address. Similarly, individual characters can be accessed by their byte-address.
 There are two ways to indicate the length of the string:
1. A special control character with the meaning "end of string" can be used as the last
character in the string.
2. A separate memory word location or register can contain a number indicating the
length ofthe string in bytes.

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BEC306C- Computer Organization and Architecture Module – 1: Machine Instruction & Programs

MEMORY OPERATIONS
Two memory operations are:
1. Load (Read/Fetch) &
2. Store (Write).
• The Load operation transfers a copy of the contents of a specific memory-location
to the processor. The memory contents remain unchanged.
• Steps for Load operation:
1) Processor sends the address of the desired location to the memory.
2) Processor issues „read‟ signal to memory to fetch the data.
3) Memory reads the data stored at that address.
4) Memory sends the read data to the processor.
• The Store operation transfers the information from the register to the specified
memory-location. This will destroy the original contents of that memory-
location.
• Steps for Store operation are:
1) Processor sends the address of the memory-location where it wants to store data.
2) Processor issues „write‟ signal to memory to store the data.
3) Content of register(MDR) is written into the specified memory-location.

INSTRUCTIONS & INSTRUCTION SEQUENCING

• A computer must have instructions capable of performing 4 types of operations:
1) Data transfers between the memory and the registers (MOV, PUSH, POP, XCHG).
2) Arithmetic and logic operations on data (ADD, SUB, MUL, DIV, AND, OR, NOT).
3) Program sequencing and control (CALL.RET, LOOP, INT).
4) I/0 transfers (IN, OUT).
REGISTER TRANSFER NOTATION (RTN)
The possible locations in which transfer of information occurs are:
1) Memory-location 2) Processor register & 3) Registers in I/O device.

Hardware Binary
Location Address Example Description
Contents of memory-location
Memory LOC, PLACE, NUM R1  [LOC] LOC are transferred into
register R1.
Add the contents of register
Processor R0, R1 ,R2 [R3]  [R1]+[R2] R1 &R2
and places their sum into R3.
I/O Contents of I/O register
Registers DATAIN, DATAOUT R1  DATAIN DATAIN are transferred into
register R1.

ASSEMBLY LANGUAGE NOTATION

To represent machine instructions and programs, assembly language format is used.

Assembly Language
Description
Format
Transfer data from memory-location LOC to register R1. The
Move LOC, R1 contents of LOC are unchanged by the execution of this
instruction, but the old contents of register R1 are overwritten.
Add the contents of registers R1 and R2, and places their sum
Add R1, R2, R3
into register R3.

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BEC306C- Computer Organization and Architecture Module – 1: Machine Instruction & Programs

BASIC INSTRUCTION TYPES

Instructions
Instruction
Syntax Example Description for Operation
Type
C<-[A]+[B]
Opcode Add the contents of memory-
Three
Source1,Source2,Des Add A,B,C locations A & B. Then, place
Address
tination the result into location C.
Add the contents of memory-
locations A & B. Then, place
the result into location B,
Two Opcode Source, Move B, C
Add A,B replacing the original
Address Destination Add A, C
contents of this location.
Operand B is both a source
and a destination.
Copy contents of memory-
Load A
Location A into accumulator.
Add contents of memory-
Opcode location B to contents of Load A Add B
One Address Add B
Source/Destination accumulator register & place Store C
sum back into accumulator.
Copy the contents of the
Store C
accumulator into location C.
Locations of all operands are
Zero Opcode [no defined implicitly. The
Push Not possible
Address Source/Destination] operands are stored in a
pushdown stack.

Access to data in the registers is much faster than to data stored in memory-locations.
Let Ri represent a general-purpose register.

The instructions:
Load A,Ri
Store Ri,A
Add A,Ri
are generalizations of the Load, Store and Add Instructions for the single-accumulator case, in
which register Ri performs the function of the accumulator.

In processors, where arithmetic operations as allowed only on operands that are in registers,
the task C<-[A] + [B] can be performed by the instruction sequence:
Move A,Ri
Move B,Rj
Add Ri,Rj
Move Rj,C

INSTRUCTION EXECUTION & STRAIGHT LINE SEQUENCING

The program is executed as follows:
 Initially, the address of the first instruction is loaded into PC (Figure 2.8). Then, the
processor control circuits use the information in the PC to fetch and execute
instructions, one at a time, in the order of increasing addresses. This is called Straight-
Line sequencing.
During the execution of each instruction, PC is incremented by 4 to point to next instruction.
There are 2 phases for Instruction Execution:
 Fetch Phase: The instruction is fetched from the memory-location and placed in the IR.

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BEC306C- Computer Organization and Architecture Module – 1: Machine Instruction & Programs

 Execute Phase: the content of IR is examined to determine which operation is to be

performed. The specified-operation is then performed by the processor.

Program Explanation
 Consider the program for adding a list of n numbers (Figure 2.9).
 The Address of the memory-locations containing the n numbers are symbolically given
as NUM1, NUM2…..NUMn.
 Separate Add instruction is used to add each number to the contents of register R0.
 After all the numbers have been added, the result is placed in memory-location SUM.

BRANCHING
Consider the task of adding a list of “n‟ numbers (Figure
2.10).
 Number of entries in the list “n‟ is stored in
memory-location N.
 Register R1 is used as a counter to determine the
number of times the loop is executed.
 Content-location N is loaded into register R1 at the
beginning of the program.
 The Loop is a straight line sequence of instructions
executed as many times as needed. The loop starts at
location LOOP and ends at the instruction Branch>0.
 During each pass,
 → address of the next list entry is determined and
 → that entry is fetched and added to R0.
 The instruction Decrement R1 reduces the contents
of R1 by 1 each time through the loop.
 Then Branch Instruction loads a new value into the
program counter. As a result, the processor fetches
and executes the instruction at this new address
called the Branch Target.
 A Conditional Branch Instruction causes a branch
only if a specified condition is satisfied. If the
condition is not satisfied, the PC is incremented in the normal way, and the next
instruction in sequential address order is fetched and executed.

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BEC306C- Computer Organization and Architecture Module – 1: Machine Instruction & Programs

CONDITION CODES
The processor keeps track of information about the results of various operations. This is
accomplished by recording the required information in individual bits, called Condition Code
Flags.
These flags are grouped together in a special processor-register called the condition code
register (or statue register).
Four commonly used flags are:
1) N (negative) set to 1 if the result is negative, otherwise cleared to 0.
2) Z (zero) set to 1 if the result is 0; otherwise, cleared to 0.
3) V (overflow) set to 1 if arithmetic overflow occurs; otherwise, cleared to 0.
4) C (carry) set to 1 if a carry-out results from the operation; otherwise cleared to 0.

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