Practical Uvm Ieee Editon TOC Changes
Practical Uvm Ieee Editon TOC Changes
Practical UVM
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Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix
5 UVM Factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.1 Need for a Factory Pattern in UVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2 UVM Factory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3 Factory Behavior for Parameterized and NonParameterized Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.4 Using the Factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.5 Replacing Components Using a Factory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.5.1 Type Overrides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.5.2 Instance Specific Overrides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.5.3 Rules for Processing Overrides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.6 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.7 New Features in IEEE 1800.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.7.1 Abstract Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.7.1.1 Step 1: Create Abstract Component Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.7.1.2 Step 2: Instance Abstract Component in your Environment . . . . . . . . . . . . . . . . . . . . . . . 92
5.7.1.3 Step 3: Create Abstract Component in build phase() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.7.1.4 Step 4: Connect Abstract Component in connect phase() . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.7.1.5 Step 5. Create the Override Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.7.1.6 Step 6: Set up Override in Top-level Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.7.2 Abstract Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6 Reporting Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1 Elements of a UVM Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.1.1 Severity Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.1.2 Verbosity Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.1.3 Handling Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.1.4 API Presented By UVM Components to Generate Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.2 Reporting Subsystem - Practical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.2.1 Controlling Reporting from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.2.2 Controlling Verbosity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.2.3 Logging Messages to a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2.4 Demoting Reports From One Level to Another . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2.5 Catching Reports and Changing Them . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2.6 Using Reporting Infrastructure with Assertions and Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3 Behavior Differences between UVM 1.2 and IEEE 1800.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.4 Exercises for Further Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
9 Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.1 Creating Callbacks in Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
9.1.1 Step 1: Create Virtual Callback Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
9.1.2 Step 2: Register the Callback Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.1.3 Step 3: Place the Callback Class Hook in Driver Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9.1.4 Step 4: Extend and Use the Callback Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.2 User Applications of Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
9.2.1 Typewide Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
9.2.2 Instance Specific Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
9.3 Order of Execution of Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
9.4 New in IEEE - get all callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
9.5 UVM Event Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.6 Debugging Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.7 Exercises for Further Exploration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
21 Factories, Multiple Register Interfaces, Reporting, Callbacks and Command Line Control using the
Wishbone Conmax Crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
21.1 Verification Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
21.1.1 Register Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
21.1.2 The Register Model for Multiple Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
21.1.3 Using a Scoreboard with Multiple Input Ports and a Simple Comparator . . . . . . . . . . . . . . . . . . . . . 355
21.1.4 Putting it All Together: The Top-level Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.1.5 The Build Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
21.1.6 Connect Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
21.1.7 Top-Level Base Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
21.1.8 Creating a Specific Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
21.1.9 Selecting a Specific Test to Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
21.2 Factory Usage for Environment Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
21.2.1 Using a Type Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
21.2.2 Using Instance Overrides to Override Specific Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
21.3 Use of Config DB to Apply Various Environment Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
21.4 Use Of a Virtual Sequencer to Direct Traffic to Wishbone Crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
21.4.1 Creating a Virtual Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
21.4.2 Connecting the Virtual Sequence to Subsequncers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
21.4.3 Creating a Virtual Sequence and Controlling Other Sequencers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Dear Reader:
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Spring 2020
The order of chapters varies significantly between the First and IEEE editions. This reorganization was based on feedback
from UVM trainers, who indicated that most new users would prefer to come up to speed on UVM and write stimulus
quickly. Hopefully, this has been addressed in the UVM Quickstart - Part 1. Readers knowing UVM and wishing to obtain
a more in-depth understanding may proceed to Parts II and III to gain in-depth knowledge. Advanced topics have been
moved to Part III from Part V of the previous edition. Part IV provides complete practical examples, just like the previous
edition. You will find some additional examples in this part as well that address topics in UVM 1800.2.
Readers have offered feedback related to editing and typographical errors in the first edition of this book. Considerable
work has been put in to eliminate as many as possible. Many paragraphs were rewritten to clarify the intent and meaning.
The book has also been reviewed by a technical writer.
If you work in a company, there is a good chance that you will be working with multiple UVM versions. When you are
especially dealing with an SOC, where you inherit multiple environments, each at a different UVM version; things usually
get a little interesting. Hence, this book attempts to serve all three different versions of the library UVM 1.1, UVM 1.2,
and IEEE 1800.2. Version specific information (where available) is marked using the following icons:
This icon is for features new to UVM 1.2 from UVM 1.1 ONLY. If you see an issue between migration from
UVM 1.1x to UVM 1.2, watch for this icon. If this feature has changed between the UVM 1.2 and IEEE
1800.2 versions, one of the other icons will also be present in the text adjacent to this icon.
Code/behavior that has changed between UVM 1.2 and IEEE 1800.2 is marked with this icon. Note that this
icon is the same one used for the Accellera to IEEE standard implementation differences.
This icon is for features of UVM deprecated between 1.2 and IEEE 1800.2 only. It does not cover deprecation
between UVM 1.2 and UVM 1.1x. See the migration guide in the previous chapter if you are attempting to
migrate to the IEEE 1800.2 version from UVM 1.2.
This icon alerts you to features new in IEEE 1800.2 and not present in UVM 1.2. Please do not confuse this
with features between UVM 1.2 and UVM 1.1x
Part 1:
This part is specifically geared to engineers wanting to pick up UVM quickly.
• Chapter 1 presents a UVM overview and helps Verilog users understand UVM testbench architecture and philosophy
and make a transition to UVM.
• Chapter 2 introduces the UVM environment.
• Chapter 3 provides you with information on creating stimulus for your DUT in UVM quickly.
Part 2:
• Chapter 4 goes over changes to uvm object and the associated core utilities. There are a number of changes in IEEE
1800.2, and you should review this chapter as UVM 1800.2 is not backward compatible with earlier versions.
• Chapter 5 goes over the additions to the UVM factory class to support abstract types and aliases. Additional examples
are added for abstract classes and factory replacement.
• Chapter 8 on the UVM component hierarchy adds examples explaining the changes in the build phase in UVM
1800.2, allowing you to speed things up.
• Chapter 6 goes over the changes to reporting in IEEE 1800.2. You may see additional failures in your regressions.
Please review this chapter as additional changes may be required on your part in your scripts.
• Chapter 9 goes over callbacks and their behavior. Callbacks have been enhanced in IEEE 1800.2.
• The Register Abstraction layer has additional examples to illustrate IEEE capability. Chapter 20 discusses unlocking
the register model.
• Chapter 13 on Phasing discusses changes with additional examples due to capabilities added in IEEE version.
• Chapter 14 discusses Advanced Stimulus Generation. The original chapter is partitioned from the earlier book to deal
solely with advanced topics. Examples now use the UVM 1800.2 style.
Advanced Topics
• Chapter 15 provides examples of how to add event callbacks to an event, a new feature introduced in IEEE version.
• Chapter 19 has descriptions of the new capabilities in the common operations. Details on how to customize your
environment using the capabilities of the IEEE version are included here.
Practical Applications:
• Chapter 21 uses a different comparison function in the scoreboard.
• Content on uvm event, uvm barrier has been relocated from Chapter 22 to Chapter 15.
Deprecated Core Utilities
Appendix A now describes the UVM 1.2 core utilities and behavior for compare/pack/print functions which have un-
dergone enhancements in IEEE 1800.2. Some of the API described in this appendix has been deprecated in the IEEE
version.