SLA7070M Series Motor Driver ICs

PRODUCT
Application Note
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28210.03
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Series SLA7070M
Motor Driver ICs
INTRODUCTION n Synchronous PWM chopping function prevents motor noise
This document describes the function and features of in Hold mode
SLA7070M series, which are unipolar 2-phase stepping motor n Sleep mode for reducing the IC input current in stand-by state
driver ICs. This document contains preliminary information on n Built-in protection circuitry against motor coil opens/shorts
the products under development. Should you have any ques- option available (NEW, patent pending)
tions, including information on options, contact your nearest
sales or representative office.
Features
n Power supply voltages, VBB : 46 V(max.), 10 to 44 V normal
operating range
n Logic supply voltages, VDD: 3.0 to 5.5 V
n Maximum output currents: 1 A, 1.5 A, 2 A, 3 A
n Built-in sequencer
n Simplified clock-in stepping control
n Both full/half-stepping, and microstepping versions;
microstepping versions (SLA7075M, -76M, -77M, -78M) are
capable of full-, half-, quarter-, eighth-, and sixteenth-step-
ping Contents
Introduction 1
n Built-in sense resistor, RSInt (NEW) Part Numbers and Options 2
n All variants are pin-compatible for enhanced design flexibility Specifications 3
Reference Voltage Setting 7
n ZIP type 23-pin molded package (SLA package) Allowable Power Dissipation 8
n Self-excitation PWM current control with fixed off-time Package Outline Drawing, SLA-23 Pin 9
Functional Block Diagram and Pin Assignments 10
For microstepping parts, off-time adjusted automatically by Application Example for Microstepping Products 12
step reference current ratio (3 levels) Truth Tables 13
Logic Input Pins 14
n Built-in synchronous rectifying circuit reduces losses at PWM
Step Sequencing 15
off (NEW) Individual Circuit Description 21
Functional Description 22
Application Information 25
Thermal Design Information 30
Characteristic Data 32
All performance characteristics given are typical values for

circuit or system baseline design only and are at the nominal
operating voltage and an ambient temperature of +25°C, unless
otherwise stated.
Sanken Power Devices

from Allegro MicroSystems
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PART NUMBERS AND OPTIONS
The following are the product variants and optional features NOTE
available in the SLA7070M series. The following abbreviations are used throughout this
document to refer to product variants:
Not all combinations of standard models and product options are
PR – Product with both Protection Circuitry and
available in high-volume production quantities. For information built-in RSInt options
on product availability, and assistance with determining the IC R – Product with the built-in RSInt option
features that are the best fit for your application, please contact
our sales office or representative.
Output Current, IOUT Blanking Time

Part Number Protection Sequencer Clock Edge
(A) (µs)
SLA7070MR RSInt
1
SLA7070MPR Protection Circuitry and RSInt
SLA7071MR RSInt
1.5
SLA7072MR RSInt Full/half Step 3.2
2
SLA7073MR RSInt
3
SLA7075MR RSInt Positive
1
SLA7076MR RSInt
1.5
SLA7076MPR Protection Circuitry and RSInt Microstep 1.7
SLA7077MR RSInt
2
SLA7078MR RSInt
3
115 Northeast Cutoff, Box 15036

2 Worcester, Massachusetts 01615-0036
Copyright © 2005 Allegro MicroSystems, Inc.
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SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS, valid at TA = 25°C, applicable to both PR and R products, unless otherwise specified
Characteristics Symbol Remarks Ratings Units
Load (Motor) Supply Voltage VM 46 V
Main Power Supply Voltage VBB 46 V
Logic Supply Voltage VDD 7 V
SLA7070M and SLA7075M 1.0 A
Output Current IOUT
Logic Input Voltage VIN –0.3 to VDD+0.3 V
REF Input Voltage VREF –0.3 to VDD+0.3 V
Sense Voltage VSInt tw < 1 µs is not considered ±2 V
Power Dissipation PD Without heat sink 4.7 W
Junction Temperature TJ 150 °C
Ambient Temperature TA –20 to 85 °C
Storage Temperature Tstg –30 to 150 °C
RECOMMENDED OPERATING RANGES, applicable to both PR and R products, unless otherwise specified
Characteristics Symbol Remarks Min Max Units
Load (Motor) Supply Voltage VM – 44 V
Main Power Supply Voltage VBB 10 44 V
Surge voltage at VDD pin should be less
Logic Supply Voltage VDD than ±0.5 V to avoid malfunctioning in 3.0 5.5 V
operation
Case Temperature TC Measured at pin 12, without heat sink – 90 °C
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ELECTRICAL CHARACTERISTICS, valid at TA = 25°C, VBB = 24 V, VDD = 5 V, applicable to both PR and R products, unless
otherwise specified
Characteristics Symbol Test Conditions Min. Typ. Max. Units
IBB Normal mode – – 15 mA
Main Power Supply Current
IBBS Sleep1 and Sleep2 modes – – 100 µA
Logic Power Current IDD – – 5 mA
MOSFET Breakdown Voltage VDSS VBB = 44 V, IDS = 1 mA – – – V
Maximum Response Frequency fclk Clock Duty Cycle = 50% 250 – – kHz
VIL – – 0.25 × VDD V
Logic Supply Voltage
VIH 0.75 × VDD – – V
IIL – ±1 – µA
Logic Supply Current
IIH – ±1 – µA
VREF See pages 6 and 7 – – – V
REF Input Voltage Output OFF, Sleep1 mode, IBBS in specification,
VREFS 2.0 – VDD V
sequencer = enable
REF Input Current IREF – ±10 – µA
VREF = 0.1 V to 0.5 V, Step reference current
SENSE Voltage VSInt VREF – 0.03 VREF VREF + 0.03 V
ratio: 100%
Sleep-Enable Recovery Time tSE VREF = 2.0 V → 1.5 V 100 – – µs
tcon Clock → Output ON – 2.0 – µs
Switching Time
tcoff Clock → Output OFF – 1.5 – µs

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STEPPING CHARACTERISTICS, applicable to both PR and R products; representative values from SLA7070M series shown
Valid at TA = 25°C, VBB = 24 V, VDD = 5 V, unless otherwise specified
Full/half step products, SLA7070M, SLA7071M, SLA7072M, and SLA7073M
Mode F – 100 – %
Step Reference Current Ratio VREF ≈ VSInt = 100 %, VREF = 0.1 to 0.5 V
Mode 8 – 70 – %
PWM Minimum On-Time ton(min) – 3.2 – µs
PWM Off-Time toff – 12 – µs
Microstepping products, SLA7075M to SLA7078M
Mode F – 100 – %
Mode E – 98.1 – %
Mode D – 95.7 – %
Mode C – 92.4 – %
Mode B – 88.2 – %
Mode A – 83.1 – %
Mode 9 – 77.3 – %
Step Reference Current Ratio Mode 8 VREF ≈ VSInt = 100 %, VREF = 0.1 to 0.5 V – 70.7 – %
Mode 7 – 63.4 – %
Mode 6 – 55.5 – %
Mode 5 – 47.1 – %
Mode 4 – 38.2 – %
Mode 3 – 29 – %
Mode 2 – 19.5 – %
Mode 1 – 9.8 – %
VMOL IMOL = 1.25 mA – – 1.25 V
Mo (Load) Output Voltage
VMOH IMOH = –1.25 mA VDD – 1.25 – – V
IMOL – – 1.25 mA
Mo (Load) Output Current
IMOH –1.25 – – mA
PWM Minimum On-Time ton(min) – 1.7 – µs
toff1 Mode 8 to Mode F – 12 – µs
PWM Off-Time toff2 Mode 4 to Mode 7 – 9 – µs
toff3 Mode 1 to Mode 3 – 7 – µs
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OUTPUT CHARACTERISTICS for both PR and R products
IOUT = 1.0 A (SLA7070M and SLA7075M)
Output On Resistance RDS(ON) IDS = 1 A – 0.7 0.85 Ω
Body Diode Forward Voltage Vf If = 1 A – 0.85 1.1 V
Output On Resistance RDS(ON) IDS = 1.5 A – 0.45 0.6 Ω
Body Diode Forward Voltage Vf If = 1.5 A – 1.0 1.25 V
BUILT-IN SENSE RESISTOR CHARACTERISTICS for PR and R products

IOUT = 1.0 A (SLA7070MPR, SLA7070MR, SLA7075MPR, and SLA7075MR)
Sense Resistor Rating* RSInt Tolerance: ±3 % 0.296 0.305 0.314 Ω
REF Input Voltage VREF Within specified current limit 0.1 – 0.3 V
*RSInt includes approximately 5 mΩ circuit resistance in addition to the resistance of the resistor itself.

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PROTECTION CIRCUIT CHARACTERISTICS*

PR products
Overcurrent Sense Voltage VOCP Motor coils shorted 0.65 0.7 0.75 V
FLAG Output Voltage VFlagL IFLAGL = 1.25 mA – – 1.25 V
VFlagH IFLAGH = –1.25 mA VDD – 1.25 – – V
FLAG Output Current IFlagL – – 1.25 mA
IFlagH –1.25 – – mA
*Protection circuits work on the condition of VSInt ≥ VOCP.
REFERENCE VOLTAGE SETTING

VREF (REF/SLEEP1 Pin)
PR and R Products
VDD
Sleep1 Set Range

VREF
2.0 V
Prohibition Zone
0.7 V VOCP PR products only
0.45 V
0.4 V
0.3 V
Motor Current Set Range
0V
1.0 A 2.0 A 1.5, 3.0 A

Devices Devices Devices
Motor Current Set Range is determined by the built-in resistor value, RSInt. For PR products, pay extra
attention to the change-over between the motor current specification range, IMO, and the Sleep1 Set Range.
VOCP falls on the "prohibition zone" threshold. If the change-over time is too slow, OCP operation would
start when VSInt > VOCP .
Allowable Power Dissipation, PD (W)
3 θj-a= 33.8℃/W
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2
0
0 10 20 30 40 50 60 70 80 90
ALLOWABLE POWER DISSIPATION
Ambient Temperature, TA (°C)
PR and R Products
4 θj-a= 26.6℃/W
Allowable Power Dissipation, PD (W)
0
0 10 20 30 40 50 60 70 80 90
Ambient Temperature, TA (°C)

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PACKAGE OUTLINE DRAWING, SLA-23 PIN
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FUNCTIONAL BLOCK DIAGRAM AND PIN ASSIGNMENTS
Full/half step products: SLA7070MPR, SLA7071MPR, SLA7072MPR, and SLA7073MPR
Ref/Sleep1
Reset
Clock
OutB
OutB
OutB
OutA
OutA
OutB
OutA
OutA
VBB
VDD
Flag
N.C.
F/R
M1
M2
M3
1 2 3 4 14 13 18 6 7 8 9 16 10 15 11 20 21 22 23
MIC Reg.
Pre- Sequencer Pre-

Driver & Driver
Sleep Circuit
Protect Protect
DAC DAC
+ Synchro +
5 Comp Comp 19
SenseA Control SenseB
- PWM PWM -
Control Control
RSInt OSC OSC RSInt
17 12
Sync Gnd
For R products, protection circuits not built-in. FLAG pin is not connected internally.
Pin No. Symbol Functions Pin No. Symbol Functions

1 13 Ref / Sleep1 Input for control current and Sleep 1 setting
OutA Output of phase A
2 14 VDD Power supply to logic
3 15 Reset Reset for internal logic
OutA Output of phase Ā
4 16 F/R Forward / reverse switch input
5 SenseA Phase A current sensing 17 Sync Synchronous PWM control switch input
6 NC No internal connection 18 Flag* Output from protection circuits monitor
7 M1 19 SenseB Phase B current sensing
8 M2 Commutation and Sleep2 setting 20
OutB Output of phase B̄
9 M3 21
10 Clock Step clock input 22
11 VBB Main power supply (for motor) OutB Output of phase B
23
12 GND Ground
*Flag pin active on PR products only; not internally connected for R products.

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Microstepping products: SLA7075MPR, SLA7076MPR, SLA7077MPR, and SLA7078MPR
Ref/Sleep1
Reset
Clock
OutB
OutB
OutB
OutA
OutA
OutB
OutA
OutA
VBB
VDD
Flag
F/R
Mo
M1
M2
M3
1 2 3 4 14 13 18 6 7 8 9 16 10 15 11 20 21 22 23
MIC Reg.
Pre- Sequencer Pre-

Driver & Driver
Sleep Circuit
Protect Protect
DAC DAC
+ Synchro +
5 Comp Comp 19
SenseA Control SenseB
- PWM PWM -
Control Control
RSInt OSC OSC RSInt
17 12
Sync Gnd
For R products, protection circuits not built-in. FLAG pin is not connected internally.
Pin No. Symbol Functions Pin No. Symbol Functions

1 13 Ref / Sleep1 Input for control current and Sleep1 setting
OutA Output of phase A
2 14 VDD Power supply to logic
3 15 Reset Reset for internal logic
OutA Output of phase Ā
4 16 F/R Forward / reverse switch input
5 SenseA Phase A current sensing 17 Sync Synchronous PWM control switch input
Output from monitor of 2-phase excitation
6 Mo 18 Flag* Output from protection circuits monitor
status
7 M1 19 SenseB Phase B current sensing
8 M2 Commutation and Sleep2 setting 20
OutB Output of phase B̄
9 M3 21
10 Clock Step clock input 22
11 VBB Main power supply (for motor) OutB Output of phase B
23
12 GND Ground
*Flag pin active on PR products only; not internally connected for R products.
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APPLICATION EXAMPLE FOR MICROSTEPPING PRODUCTS
Microstepping products: SLA7075MPR, SLA7076MPR, SLA7077MPR, and SLA7078MPR
VBB = 10~44 V VS+
+
VI+ VDD = 3.0~5.5 V CA
OutA OutA VBB OutB OutB
VDD
Sleep
r1 C1
Q1
Reset
+ Clock
CB F/R
M1 SLA 707xM
Micro- M2
computer
M3
Sync
Mo or NC
Flag
Ref/Sleep1
SenseA GND SenseB
r2 r3
C2 Single-Point
Ground
Logic Ground Power Ground
• Take precautions to avoid noise on the VDD line; noise levels • Unused logic input pins (F / R, M1, M2, M3, RESET, and
greater than 0.5 V on the VDD line may cause device malfunc- SYNC) must be pulled up / down to VDD or ground. If those
tion. Noise can be reduced by separating the Logic Ground unused pins are left open, the device malfunctions.
and the Power Ground on a PCB from the GND pin (pin 12). • Unused logic output pins (Mo, FLAG) must be kept open.
• Constants, for reference use only:
r1 = 10 kΩ CA = 100 µF / 50 V
r2 = 1 kΩ (VR) CB = 10 µF / 10 V
r3 = 10 kΩ C1 = 0.1 µF

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TRUTH TABLES
Common Input Pins circuitry, including the output MOSFETs and regulator, the
The following truth table is valid for the common input pins of sequencer / translator circuit is active. Therefore, a microcon-
both models of the SLA7070M series troller can set the step starting point for the next operation during
the Sleep1 function.
Truth Table for Common Input Pins
Applicable both series models; PR and R products Commutation / Sleep2 Function Setting The following truth
Clock table is valid for the common Mx pins of both models of the
Pin Name Low Level High Level
POS Edge SLA7070M series.
Normal
Reset Logic reset – Truth Table for Commutation / Sleep2 Function
operation
Applicable both series models; PR and R products
F/R Forward Reverse
Pin Name
M1 Full / Half Step Microstepping
Commutation / M1 M2 M3
M2
Sleep2 function L L L Full step (Mode 8 fixed) Full step (Mode 8 fixed)
M3
H L L Full step (Mode F fixed) Full step (Mode F fixed)
Normal
Ref / Sleep1 Sleep1 function – L H L Half step Half step
operation
Non-sync PWM Sync PWM H H L Half step (Mode F fixed) Half step (Mode F fixed)
Sync –
control control L L H Quarter step
H L H Eighth step
Sleep2 function
• The Reset function is asynchronous. If the input on the Reset L H H Sixteenth step
pin is High, the internal logic circuit is reset. At this point, if the H H H Sleep2 function
Ref pin stays Low, then the DMOS outputs turn on at the starting
point of excitation. Note that the Disable control is not available In the Sleep2 function, the outputs are disabled and the driver
with the Reset pin signal. supply current (IBB) is reduced. However, unlike the Sleep1
• The Sync function is active only at “2-phase excitation tim- function, the logic circuitry is put into a "standby" state and
ing." If this function is used at other than 2-phase excitation therefore the sequencer / translator is not activated, even if a step
timing, an overall balance might collapse because PWM off-time command signal occurs on the CLOCK input pin.
and set current are different in each phase A and phase B control
Monitor Output Pin
scenario. (2-phase excitation timing is a point where the step
reference current ratio of both phase A and phase B is Mode 8.) The pin used to monitor the device output is different between
these configurations:
Sleep Functions • Microstepping products: Mo (2-phase excitation timing)
The Hold mode stops motor rotation when applying current
into a motor, and the device remains in Active status. Sleep1 is • PR products: Flag (Protection circuit operation timing)
a sleep operation when logic circuits operate according to input Note that PR products with microstepping have both of the
signals. Sleep2 is a sleep operation in which the status of the monitor output pins.
logic circuits do not vary, but instead, they keep the same state as
before the sleep function is initiated. Truth Table for Monitor Outputs
Pin Name Low Level High Level
Sleep1 Function Setting Voltage at the REF / SLEEP1 pin
Mo Other than 2-phase 2-phase excitation timing
controls the PWM current and the Sleep1 function. For normal excitation timing
operation, VREF should be below 1.5 V (Low level). Applying a
FLAG Normal operation Protection circuit operation
voltage greater than 2.0 V (High level) to the REF / SLEEP1 pin
disables the outputs and puts the motor in a free state (coast). The outputs turn off at the point where the protection circuit
This function is used to minimize power consumption when the starts operating. To release the protection state, reinput the logic
device is not in use. Although it disables much of the internal supply voltage.
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LOGIC INPUT PINS
The low pass filter incorporated with the logic input pins (RE- RESET input
SET, CLOCK, F / R, M1, M2, M3, and SYNC) improves noise • RESET input pulse width
rejection. The logic inputs are CMOS input compatible, and
The Reset pulse width is equivalent to the high pulse level hold
therefore they are in high impedance state. Use the IC at a fixed
time. It should be greater than the 2 µs CLOCK input pulse
input level, either Low or High.
width.
Input Logic Timing • Reset release and CLOCK input timing
CLOCK signal. This device includes clock-in type of control that
The RESET input sets the translator / sequencer to a predefined
simplifies the interface.
Home state and turns off all of the DMOS outputs. A low pass
• Pulse characteristics filter is incorporated into the Reset circuit; therefore, a greater
A low-to-high and high-to-low transition on the CLOCK input than 5 µs delay is required between the falling edge of the RE-
sequences the translator / sequencer. Clock pulse width should SET input and the rising edge of the CLOCK input.
be set at 2 µs in both positive and negative polarities. Therefore,
F / R, M1, M2, and M3 logic change
clock response frequency becomes 250 kHz.
Logic level inputs on F / R, M1, M2, and M3 set the translator
• Set-up and hold times before and after Clock pulse
step direction (F / R) and step mode (M1, M2, and M3; refer to
With regard to the input logic of the F / R, M1, M2, and M3 pins, the Commutation Truth Table). Changes to these inputs do not
a 1 µs delay should occur both before and after the pulse edges, take effect until the rising edge of the CLOCK input. However,
as set-up and hold times. The sequencer logic circuitry might depending on the type and state of a motor, there may be errors
malfunction if the logic polarity is changed during these set-up in motor operation. A thorough evaluation on the changes of
and hold times. Refer to the figure below. sequence should be carried out.
Reset
2μs(min)
POS Edge 5μs(min) 4μs(min)
Clock 2μs(min)
2μs(min)
F/R
M1 2μs(min) 1μs(min) 1μs(min)
M2 1μs(min) 1μs(min) 2μs(min)
M3
Reset Logic Input Timing

2μs(min)
5μs(min) 8μs(min)
Clock 4μs(min)
4μs(min)
F/R
M1 1μs(min)
115 Northeast Cutoff, 1μs(min)
Box 15036
14 M2 1μs(min)Worcester,
1μs(min)Massachusetts 01615-0036 1μs(min) 1μs(min)
M3
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STEP SEQUENCING
All illustrations in this section are based on step sequencing at the POS (Positive) edge.
Full step; for both microstepping and full / half step products
M1: L, M2: L, M3: L (Mode 8)
R ESET
C LO C K …
0 1 2
FWD
CW
A 0
A
70.7
CREW
CW
70.7
B
M1: H, M2: L, M3: L (Mode F)
R ESET
C LO C K …
0 1 2
FWD
CW
A 0
A
CREW
CW
0
10
0
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Half step; for both microstepping and full / half step products
M1: L, M2: H, M3: L (Mode 8, F)
R ES ET
C LO C K …
0 1 2 3 4
FWD
CW
A 0
A
70.7
CREW
CW
0
70.7
10
0
M1: H, M2: H, M3: L (Mode F)

R ES ET
C LO C K …
0 1 2 3 4
CW
FWD
A 0
A
CREW
CW
0
10
0

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Quarter step; for microstepping products

M1: L, M2: L, M3: H
…
８
7
6
5
CW
CREW
4
3
0
2
38.2
1
70.7
CFWD
W
92.4
0
0
0
38.2
70.7
92.4
10
C LO C K
R ES ET
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Eighth step; for microstepping products
M1: H, M2: L, M3: H
…
16
15
14
13
12
11
10
A
9
CW
8
CREW
7
6
5
0
4
19.5
3
38.2
2
55.5
1
70.7
83.1
CFWD
W
92.4
0
98.1
0
0
19.5
38.2
55.5
70.7
83.1
92.4
98.1
10
C LO C K
R ES ET

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M1: L, M2: H, M3: H

C LO C K …
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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B
Sixteenth step; for microstepping products
CFWDW
A 0
A
9.8
19.5
29.0
38.2
47.1
55.5
63.4
70.7
77.3
83.1
88.2 CREW
CW
92.4
95.7
98.1
0
0
9.8
10
95.7
88.2
83.1
77.3
70.7
63.4
55.5
47.1
38.2
29.0
19.5
B
98.1
92.4
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Excitation Change Sequence
The change behavior is determined by the settings of the excitation pin (M1, M2, and M3) before and after the step signal.
Excitation Mode State Table
Internal Sequence State Step Sequencing
Direction Phase A Phase B Full Step Half Step 1/ Step 1/
4 8 Step 1/
16 Step
PWM Mode PWM Mode Mode 8 Mode F Mode 8, F Mode F
A 8 B 8 X X* X X* X X X
A 7 B 9 X
A 6 B A X X
A 5 B B X
A 4 B C X X X
Rev. A 3 B D X
A 2 B E X X
A 1 B F X
– – B F X X X X X
Ā 1 B F X
Ā 2 B E X X
Ā 3 B D X
Ā 4 B C X X X
Ā 5 B B X
Ā 6 B A X X
Ā 7 B 9 X
Ā 8 B 8 X X* X X* X X X
Ā 9 B 7 X
Ā A B 6 X X
Ā B B 5 X
Ā C B 4 X X X
Ā D B 3 X
Ā E B 2 X X
Ā F B 1 X
Ā F – – X X X X X
Ā F B̄ 1 X
Ā E B̄ 2 X X
Ā D B̄ 3 X
Ā C B̄ 4 X X X
Ā B B̄ 5 X
Ā A B̄ 6 X X
Ā 9 B̄ 7 X
Ā 8 B̄ 8 X X* X X* X X X
Ā 7 B̄ 9 X
Ā 6 B̄ A X X
Ā 5 B̄ B X
Ā 4 B̄ C X X X
Ā 3 B̄ D X
Ā 2 B̄ E X X
Ā 1 B̄ F X
– – B̄ F X X X X X
A 1 B̄ F X
A 2 B̄ E X X
A 3 B̄ D X
A 4 B̄ C X X X
A 5 B̄ B X
A 6 B̄ A X X
A 7 B̄ 9 X
A 8 B̄ 8 X X* X X* X X X
A 9 B̄ 7 X
A A B̄ 6 X X
A B B̄ 5 X
A C B̄ 4 X X X
A D B̄ 3 X
A E B̄ 2 X X
A F B̄ 1 X
A F – – X X X X X
A F B 1 X
Fwd. A E B 2 X X
A D B 3 X
A C B 4 X X X
A B B 5 X
A A B 6 X X
A 9 B 7 X
∗ Sequence state is Mode 8, but step reference current ratio is Mode F. Mode F has step reference current ratio of 100%, and PWM off-time of 12 μs.

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INDIVIDUAL CIRCUIT DESCRIPTION
Monolithic IC (MIC) • Regulator Circuit

The descriptions of the monolithic IC (MIC) elements in this The integrated regulator circuit is used in driving the output
section are applicable to both models of products: PR and R.
MOSFET gates and powering other internal linear circuits.
However, the blanking time differs among some options, and
current value in low current mode will vary according to the • Protection Circuit
minimum on-time difference. A built-in protection circuit against motor coil opens or shorts is
• Sequencer Logic available in the PR products. Protection is activated by sensing
The single CLOCK input is used for step timing. Direction is voltage on the internal RSInt resistors; therefore, an overcurrent
controlled by the F / R input. condition cannot be detected which results from the the OUT
Commutation mode is controlled by the combination of the M1, pins or SENSEx pins, or both, shorting to GND.
M2, and M3 logic levels. For details, refer to the Commutation Protection against motor coil opens is available only during
Truth Table on page 13. PWM operation; therefore, it does not work at constant voltage
• PWM Current Control driving, when the motor is rotating at high speed.
Each pair of outputs is controlled by a fixed off-time PWM Operation of the protection circuit disables all of the DMOS
current-control circuit. The internal oscillator (OSC) sets the outputs. To come out of protection mode, cycle the logic supply,
off-time. Its operation mechanism is identical to that of the
VDD.
SLA7060M family. Refer to the Functional Description section
for further details. Output MOSFET Chip
• Synchronous Operation Mode The value of the built-in output DMOS chip varies according
This function prevents occasional motor noise during Hold to which of the four different output current ratings has been
mode, which normally results from asynchronous PWM opera- selected.
tion of both motor phases. A logic high at the SYNC input sets
synchronous operation. A logic low sets asynchronous operation. Sense Resistor
The use of synchronous operation during normal stepping is not Sense resistors are incorporated in the PR and R products to
recommended because it produces less motor torque and can detect motor current. The resistance varies according to which
cause motor vibration due to staircase current. of the four different output current ratings has been selected, as
The use of synchronous operation when the motor is not in follows:
operation is allowed only in full/half step sequence timing, due
Output Current RSInt Resistance
to the difference in the current controlled and PWM off-time at (A) (Ω Typ.)
other step sequence timings.
1 0.305
• DAC (D-to-A Converter) 1.5 0.305
In microstep sequencing, the current at each step is set by the 2 0.205
value of a sense resistor (RSInt), a reference voltage (VREF), and
3 0.155
the output voltage of the DACs, controlled by the output of the
sequencer (translator). Refer to the Stepping Characteristics table Each resistance shown above includes the inherent resistance
on page 5. (approximately 5 mΩ) in the resistor itself.
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FUNCTIONAL DESCRIPTION
PWM Current Control put is enabled and current flows through the motor winding and
The description in this section is applicable to the PR and R the current-sense resistors. When the voltage across the current-
products.
sense resistor equals the DAC output voltage, VTRIP , the current-
• Blanking time
sense comparator resets the PWM latch. This turns off the driver
The actual operating waveforms on the SENSEx pins when driv-
for the fixed off-time, during which the load inductance causes
ing a motor are shown in figure 1. Immediately after PWM turns
OFF, ringing (or spike) noise on the SENSEx pins is observed the current to recirculate for the off-time period. Therefore, if the
for a few μs. Ringing noise can be generated by various causes, ringing noise on the sense resistor equals and surpasses VTRIP ,
such as capacitance between motor coils and inappropriate motor PWM turns off.
wiring.
To prevent this phenomenon, the blanking time is set to override
Each pair of outputs is controlled by a fixed off-time (7 to 12 μs,
depending on stepping mode) PWM current-control circuit that signals from the current-sense comparator for a certain period
limits the load current to a desired value, ITRIP. Initially, an out- right after PWM turns on (figure 2).
t t
Expanded Time Scale
Out
ITRIP 0
Out
5 µs/Div. 500 ns/Div.

Figure 1. Operating waveforms on the SENSEx pins during PWM chopping
A PWM Pulse Width
tON tOFF
(Fixed)
ITRIP
A
Blanking Time
Figure 2. SENSEx pins pattern during PWM control

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PWM Off Period Figure 3 shows the difference in back EMF generative system
The PWM off-time for the SLA7070M series is controlled as a between the SLA7060M series and SLA7070M series. The
fixed time by an internal oscillator. It also is switched in 3 levels SLA7060M series performs on–off operations using only the
by current proportion (see the Electrical Characteristics table). MOSFET on the PWM-on side, but the SLA7070M series also
In addition, the SLA7070M series provide a function that performs on–off operations using only the MOSFET on the
decreases losses occurring when the PWM turns off. This func- PWM-off side. To prevent simultaneous switching of the MOS-
tion dissolves back EMF stored in the motor coil at MOSFET FETs at synchronous rectification operation, the IC has a dead
turn-on, as well as at PWM turn-on (synchronous rectification time of approximately 0.5 µs. During dead time, the back EMF
operation). flows through the body diode on the MOSFET.
SLA7060M Series SLA7070M Series

VBB VBB
Ion Ioff Ion Ioff
Stepper Motor Stepper Motor
Vg Vg Vg Vg
Back EMF at Dead Time
VS RSExt VS RSInt
+V +V
PWM On PWM Off PWM On PWM On PWM Off PWM On
Dead Dead
Vg Vg Time Time
FET Gate 0 FET Gate 0

Signal Signal
t t
Vg Vg
VREF VREF
VS VS
0 0
t t
Figure 3. Synchronous rectification operation. During Dead Time,

the Back EMF flows through the body diode of the MOSFET
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Protection Functions: PR Types disabled at the time the protection circuit starts.
The PR types of the SLA7070M series include a motor coil
In order for the motor coil short-circuit protection circuit to oper-
short-circuit protection circuit and a motor coil open protection
ate, VSInt must be greater than VOCP .
circuit. They are described in this section.
• Motor Coil Short-Circuit Protection (Load Short) Circuit Overcurrent that flows without passing the sense resistor is un-
detectable. To resume the circuit after protection operates, VDD
This protection circuit, embedded in the SLA7070M series, be-
gins to operate when the device detects an increase in the voltage must be cycled.
level on the sense resistor, VSInt . • Motor Coil Open Protection
The voltage at which motor coil short-circuit protection starts Details of this functions is not disclosed yet due to our patent
its operation, VOCP, is set at approximately 0.7 V. The output is policy.
VM
Coil Short Circuit
Coil Short Circuit +V

Normal Operation Output Disable
VOCP
Stepper Motor
Vg VREF
VS
0
VS RSInt t
Figure 4. Motor coil short circuit protect circuit operation. Overcurrent that flows with-
out passing the sense resistor is undetectable. To recover the circuit after protection oper-
ates, VDD must be cycled and started up again.

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APPLICATION INFORMATION
Motor Current Ratio Setting (R1, R2, RSInt) where:

The setting calculation of motor current IOUT on SLA7070M (4)
series is determined by the ratios of external components R1, R2,
��
and RSInt (refer to the application example circuit on page 12).
The following is a formula for calculating IOUT: VM is the motor supply voltage,
�� (1) RDS(on) is the MOSFET on resistance,
��
�� IOUT is the target current level,
when VREF is within specification. If VREF is set less than 0.1 V,
variation or impedance of the wiring pattern may influence the RM is the motor winding resistance,
IC and the possibility of less accurate current sensing becomes LM is the motor winding reactance, and
high.
tOFF is the PWM off-time.
The standard voltage of current ITRIP that SLA7070M series
Even if the control current value is set at less than the lower limit
controls is partially divided by the internal DAC:
�� of the control current, there is no setting at which the IC fails to
�� (2) operate. However, control current will worsen against setting
��
current.
For RSInt value, see Sense Resistor section, page 21.
Lower Limit of Control Current Avalanche Energy

The SLA7070M series uses a self-oscillating PWM current In the unipolar topology of the SLA7070M series, a surge
control topology in which the off- time is fixed. As energy stored voltage (ringing noise) that exceeds the MOSFET capacity to
in motor coil is eliminated within fixed the PWM off-time, coil withstand might be applied to the IC. To prevent damage, the
current flows intermittently, as shown in figure 5. SLA7070M series is designed a MOSFET having sufficient ava-
Thus, average current decrease and motor torque also decrease. lanche resistance to withstand this surge voltage. Therefore, even
The point intermissive current starts flowing to the coil is con- if surge voltages occur, users will be able to use the IC without
sidered as the lower limit of the control current. The lower limit any problems. However, in cases in which the motor harness is
of control current differs by conditions of motor or other factors, long or the IC is used above its rated current or voltage, there
but it is calculated from the following formula. is a possibility that an avalanche energy could be applied that
��
� �� (3) exceeds Sanken design expectations. Thus, users must test the
� ��
� ��
�� avalanche energy applied to the IC under actual application
��
conditions.
A ITRIP(Big)
ITRIP(Small)
0
A
Figure 5. Control current lower limit model waveform. The circled area indicates interval
when the coil current generated is 0 A.
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The following procedure can be used to check the avalanche The avalanche energy, EAV, can be calculated using the following
energy in an application. The schematic in figure 6 illustrates formula:
the location for the voltage test points and circuit characteristics. �� (5)
The timing diagram illustrates the waveform characteristics
resultant. � ��
VM
� ��
V D S(A V ) By comparing the EAV calculated with the graph shown in

ID Stepper Motor figure 9, the application can be evaluated if it is safe for the IC
by being within the avalanche energy-tolerated dose range of the
MOSFET.
VD S(A V )
ID
On-Off Sequence of Power Supply (VBB and VDD)
There is no restriction of the on-off sequence of the main power
RSInt
t supply, VBB, and the logic supply, VDD.
Figure 6. Test points and characteristics (left panel) and

breakdown waveform (right). Motor Supply Voltage (VM) and Main Power Supply
Voltage (VBB)
Because the SLA7070M series has a structure that separates the
Given: control IC (MIC) and the power MOSFETs as shown in the sche-
VDS(AV) = 1 A, matics on pages 10 and 11, motor supply and main power supply
ID = 1 A, and are separated. Therefore, it is possible to drive the IC with using
different power supplies and different voltages for motor supply
t = 0.5 µs. and main power supply. However, extra caution is needed be-
cause the supply voltage ranges differ among power supplies.
20
SLA7073M and
SLA7078M
16
12
EAV [mJ ]
SLA7072M
and SLA7077M
SLA7071M and
8 SLA7076M
SLA7070M and
4 SLA7075M
0
0 25 50 75 100 125 150
Product Temperature, Tc [°C]
Figure 7. SLA7070M series iterated avalanche energy tolerated dose, EAV(max).

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Internal Logic Circuits In normal operation, generally the input signal for switching can
• Reset be sent from an external microcomputer. However, in applica-
tions where the input signal cannot be transmitted adequately
The sequencer circuit of this product is initialized after logic
due to limitations of the port, the following method can be taken
supply (VDD) is applied, and the power on reset function oper-
to use the functions.
ates. To initialize the sequencer, the output immediately after
power-on indicates that the status that the power circuits are in The schematic diagram in figure 8 shows how the IC is designed
the home state. In a case where the sequencer must be reset after so that the Sync signal can be determined by the CLOCK input
signal. When a logic high signal is received on the CLOCK pin,
motor has been operating, a reset signal must be inputted on the
the internal capacitor, C, is charged, and the Sync signal is set to
RESET pin. In a case in which external reset control is not nec-
logic low level. However, if the Clock signal cannot rise above
essary, the RESET pin is not used, and must be fixed at a logic
logic low level (such as when the circuit between the microcom-
low level on the application circuit board. puter and the IC is not adequate), the capacitor is discharged by
• CLOCK Input the internal resistor, R, and the Sync signal is set to logic high,
When the CLOCK input signal stops, excitation changes to causing the IC to shift to synchronous mode.
the motor Hold state. At this time, there is no difference if the The RC time constant in the circuit should be determined by the
CLOCK input signal is at the low level or the high level. The minimum clock frequency used. In the case of a sequence that
SLA7070M series is designed to move 1 step at a time, when a keeps the CLOCK input signal at logic high, an inverter circuit
Clock pulse edge is detected. must be added. In a case where the Clock signal is set at an
undetermined level, an edge detection circuit (figure 9) can be
• Chopping Synchronous Circuit used to prepare the signal for the CLOCK input, allowing correct
The SLA7070M series has a chopping synchronous function to processing by the circuit shown in figure 8.
protect from abnormal noises that may occasionally occur during • Output Disable (Sleep1 and Sleep2) Circuits
the motor-Hold state. This function can be operated by setting
There are two methods to set this IC at motor free-state (coast,
the SYNC terminal at high level. However, if this function is
with outputs disabled). One is to set the REF/SLEEP1 pin to
used during motor rotation, control current does not stabilize, more than 2 V (Sleep1), and the other (Sleep2) is to set the
and therefore this may cause reduction of motor torque or excitation signals (pins M1, M2, and M3). In either way, the IC
increased vibration. So, Sanken does not recommend using this will change to Sleep mode, stopping the main power supply at
function while the motor is rotating. In addition, the synchronous the same time, and decreasing circuit current. The difference
circuit should be disabled in order to control motor current prop- between the two methods is that, in the first way, the internal
erly in case it is used other than in dual excitation state (Modes 8 sequencer remains in an enabled state, and in the latter method,
and F) or single excitation Hold state. the IC enters the Hold state. Moreover, in the method using
VCC
74HC14 74HC14
Clock Sync Clock
Step
Clock
R C
Figure 8. Clock signal shutoff detection circuit, using Figure 9. Clock signal edge detection circuit, inputs
74HC14s. to example circuit shown in figure 8.
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the excitation signals (Sleep2), excitation timing remains in a • REF/SLEEP1 Pin
"standby" state, even if a signal is inputted on the CLOCK pin The REF/SLEEP1 pin provides access to the following func-
during Sleep mode. tions:
When awaking to normal operating mode (motor rotation) from • Standard voltage setting for output current level setting
disabled (Sleep1 or Sleep2) mode, set an appropriate delay time • Output enable-disable control input
from cancellation of the disable mode to the initial CLOCK These functions are further described in the Truth Tables section
input edge. In doing so, consider not only of rise time for the (page 13), and in the discussion of output disabling, above.
IC, but also of the rise time for the motor excitation current, is
important (see figure 10). The figure in the Reference Voltage Setting section (page 7),
shows the general relationship between the reference voltage,
VREF , (REF/SLEEP1 pin) setting voltage and performance.
There are, however, situations in which extra caution should be
REF/SLEEP1 or
M1, M2, and M3
exercised. These are shown in figure 11:
Range A. In this range, control current value also varies in ac-
100 µs cordance with VREF. Therefore, losses in the IC and the sense
(minimum)
resistors must be given extra consideration.
CLOCK
Range B. In this range, the voltage that switches output enable
and disable (Sleep mode) exists. At enable, the same cautions
t
apply as in range A. In addition, for some cases, there are pos-
Figure 10. Timing delay between disable cancellation
sibilities that the output status will become unstable as a result of
and the next Clock input
iteration between enable and disable.
Internal Control Current Setting Voltage
2.5
Output disable (Sleep mode)
2.0 setting voltage range
Range B
1.5
(Mode F)
Range A
[V]
1.0
Control current input voltage range
0.5
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REF/SLEEP1 Pin Voltage VREF [V]
Figure 11. Relationship between external and internal reference voltages and performance. Ensure that
the absolute maximum current level is not reached.

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• Logic Input Pins when they are left open.

If a logic input pin (CLOCK, RESET, F/R, M1, M2, M3, or • Output Pins
SYNC) is not used (fixed logic level), the pin must be tied to The Mo and FLAG output pins are designed as monitor outputs,
VDD or GND. Please do not leave them floating, because there and inside of the IC is an output inverter (see figure 12). There-
is possibility of undefined effects on IC performance fore, let these pins float if they are not used.
VDD
Static electricity
protection circuit
Mo or FLAG
Figure 12. Mo pin (SLA 7075M through SLA 7078M models

only) and FLAG pin general internal circuit layout
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THERMAL DESIGN INFORMATION
It is not practical to calculate the power dissipation of SLA7070M Based on the PD calculated using the above formulas, the ex-
series accurately, because that would require factors that are vari- pected increase in operating junction temperature, ∆TJ , of the
able during operation, such as time periods and excitation modes
during motor rotation, input frequencies and sequences, and so IC can be estimated using figure 13. This result must be added
forth. Given this situation, it is preferable to perform an approxi- to the worst case ambient temperature when operating, TA(max).
mate calculation at worst conditions. The following is a simpli- Based on the calculation, there is no problem unless TA(max) +
fied formula for calculation of power dissipation:
∆TJ > 150°C.
(6)
��
However, final confirmation must be made by measuring the IC
where:
temperature during operation and then verifying power dissipa-
PD is the power dissipation in the IC,
IOUT is the operating output current, tion and junction temperature in the corresponding graph.
RDS(on) is the on resistance of the output MOSFET, and When the IC is used with a heat sink attached, device package
RSInt is current sense resistance. thermal resistance, RθJA, is a variable used in calculating ∆Tj-a.
150
Increase in Junction Temperature
125
100
�TJ-A = 26.6 x PD
�TJ (°C)
75
�TC-A = 21.3 x PD
50
25
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Maximum Allowable Power Dissipation, PD(max) (W)
Figure 13. Temperature increase

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The value of RθJA is calculated from the following formula:

CAUTION
�θ��≈�θ��θ��θ��θ��θ�� (7)
The SLA7070M series is designed as a multichip, with sepa-
where RθFin is the thermal resistance of the heat sink. rate power elements (MOSFET), control IC (MIC), and sense
∆TJA can be calculated with using the value of RθJA: resistance. Consequently, because the control IC cannot accu-
rately detect the temperature of the power elements (which are
�� (8)
the primary sources of heat), the ICs do not provide a protection
function against overheating. For thermal protection, users must
The following procedure should be used to measure product conduct sufficient thermal evaluations to be able to ensure that
temperature in actual operation and then estimate junction tem- the junction temperature does not exceed the warranty level
perature:
(150°C).
1. Measure the ambient temperature, TA.
This thermal design information is provided for preliminary
2. With the device mounted but not operating, measure the tem- design estimations only. The thermal performance of the IC will
perature of the device case at the center (pin 12).
be significantly determined by the conditions of the application,
3. Power-on the device, and after it reaches operating tempera- in particular the state of the mounting PCB, heat sink, and the
ture, take the measurement again.
ambient air. Before operating the IC in an application, the user
4. Subtract the value found in step 2 from the value found in must experimentally determine the actual thermal performance.
step 3. This will provide a value for ∆TCA.
The maximum recommended case temperatures (at the center,
5. Refer to figure 13 and locate the value found in step 4 on the
∆TCA trace. pin 12) for the IC are:
6. Determine the corresponding power dissipation, PD. • With no external heat sink connection: 90°C
7. Substitute the values into equation 8. • With external heat sink connection: 80°C
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CHARACTERISTIC DATA
Output MOSFET On-Voltage, VDS(on)
SLA7070M/SLA7075M SLA7071M/SLA7076M
1.4 1.4
Iout=1.5A
1.2 Iout=1A 1.2
1.0 1.0
VDS(on) [V]
VDS(on) [V]
0.8 0.8
Iout=0.5A
Iout=1A
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Product Temp Tc[C] � ��
1.2 1.4
Iout=2A Iout=3A
1.0 1.2
1.0
0.8
VDS(on) [V]
Iout=2A
VDS(on) [V]
0.8
0.6
Iout=1A
0.6
0.4 Iout=1A
0.4
0.2
0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Product Temp Tc[C] Product Temp Tc[C]

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Output MOSFET Body Diodes Forward Voltage, VF
1.1 1.1
1.0 1.0
0.9 0.9
VF [V]
VF [V]
0.8 Iout=1A 0.8 Iout=1.5A
0.7 Iout=0.5A 0.7

Iout=1A
0.6 0.6
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
1.1 1.1
1.0 1.0
Iout=3A
0.9 0.9
VF [V]
VF [V]
Iout=2A
Iout=2A
0.8 0.8
Iout=1A
0.7 0.7 Iout=1A
0.6 0.6
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
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WARNING — These devices are designed to be operated at lethal voltages and energy levels. Circuit designs
that embody these components must conform with applicable safety requirements. Precautions must be
taken to prevent accidental contact with power-line potentials. Do not connect grounded test equipment.
The use of an isolation transformer is recommended during circuit development and breadboarding.
The products described herein are manufactured in Japan by Sanken

Electric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken and Allegro reserve the right to make, from time to time, such
departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its
products. Therefore, the user is cautioned to verify that the information
in this publication is current before placing any order.
When using the products described herein, the applicability and suit-
ability of such products for the intended purpose shall be reviewed at
the users responsibility.
Although Sanken undertakes to enhance the quality and reliability
of its products, the occurrence of failure and defect of semiconductor
products at a certain rate is inevitable.
Users of Sanken products are requested to take, at their own risk, pre-
ventative measures including safety design of the equipment or systems
against any possible injury, death, fires or damages to society due to
device failure or malfunction.
Sanken products listed in this publication are designed and intended
for use as components in general-purpose electronic equipment or
apparatus (home appliances, office equipment, telecommunication
equipment, measuring equipment, etc.). Their use in any application
requiring radiation hardness assurance (e.g., aerospace equipment) is
not supported.
When considering the use of Sanken products in applications where
higher reliability is required (transportation equipment and its control
systems or equipment, fire- or burglar-alarm systems, various safety
devices, etc.), contact a company sales representative to discuss and
obtain written confirmation of your specifications.
The use of Sanken products without the written consent of Sanken
in applications where extremely high reliability is required (aerospace
equipment, nuclear power-control stations, life-support systems, etc.) is
strictly prohibited.
The information included herein is believed to be accurate and reli-
able. Application and operation examples described in this publication
are given for reference only and Sanken and Allegro assume no respon-
sibility for any infringement of industrial property rights, intellectual
property rights, or any other rights of Sanken or Allegro or any third
party that may result from its use.
G1,IC-FAE

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PRODUCT

All performance characteristics given are typical values for

Sanken Power Devices

Output Current, IOUT Blanking Time

115 Northeast Cutoff, Box 15036

115 Northeast Cutoff, Box 15036

BUILT-IN SENSE RESISTOR CHARACTERISTICS for PR and R products

115 Northeast Cutoff, Box 15036

PROTECTION CIRCUIT CHARACTERISTICS*

REFERENCE VOLTAGE SETTING

Sleep1 Set Range

0.7 V VOCP PR products only

1.0 A 2.0 A 1.5, 3.0 A

Ambient Temperature, TA (°C)

115 Northeast Cutoff, Box 15036

PACKAGE OUTLINE DRAWING, SLA-23 PIN

���� ���� ��� ����

���� ���� ��� ����

����������������� ��� ����

Full/half step products: SLA7070MPR, SLA7071MPR, SLA7072MPR, and SLA7073MPR

Pre- Sequencer Pre-

Pin No. Symbol Functions Pin No. Symbol Functions

115 Northeast Cutoff, Box 15036

Microstepping products: SLA7075MPR, SLA7076MPR, SLA7077MPR, and SLA7078MPR

Pre- Sequencer Pre-

Pin No. Symbol Functions Pin No. Symbol Functions

Microstepping products: SLA7075MPR, SLA7076MPR, SLA7077MPR, and SLA7078MPR

VBB = 10~44 V VS+

115 Northeast Cutoff, Box 15036

Reset Logic Input Timing

M1: H, M2: H, M3: L (Mode F)

115 Northeast Cutoff, Box 15036

Quarter step; for microstepping products

115 Northeast Cutoff, Box 15036

M1: L, M2: H, M3: H

115 Northeast Cutoff, Box 15036

INDIVIDUAL CIRCUIT DESCRIPTION

Monolithic IC (MIC) • Regulator Circuit

5 µs/Div. 500 ns/Div.

A PWM Pulse Width

115 Northeast Cutoff, Box 15036

SLA7060M Series SLA7070M Series

Ion Ioff Ion Ioff

Stepper Motor Stepper Motor

Back EMF at Dead Time

FET Gate 0 FET Gate 0

Figure 3. Synchronous rectification operation. During Dead Time,

Coil Short Circuit +V

115 Northeast Cutoff, Box 15036

Motor Current Ratio Setting (R1, R2, RSInt) where:

Lower Limit of Control Current Avalanche Energy

V D S(A V ) By comparing the EAV calculated with the graph shown in

Figure 6. Test points and characteristics (left panel) and

Figure 7. SLA7070M series iterated avalanche energy tolerated dose, EAV(max).

115 Northeast Cutoff, Box 15036

115 Northeast Cutoff, Box 15036

• Logic Input Pins when they are left open.

Figure 12. Mo pin (SLA 7075M through SLA 7078M models

Figure 13. Temperature increase

��

��

��