BY MR.

AKETCH – A TVET TRAINER - KENYA COAST NATIONAL POLY

13/02/2019

INPUT/OUTPUT TECHNIQUES
The I/O subsystem of a computer provides an efficient mode of communication between the central
system and the outside environment. It handles all the input-output operations of the computer system.

Generic model of I/O Module

Fig. Generic model of I/O Module

The technique used to transfer data between processor and I/O devices is called I/O technique. The
techniques involved are mainly classified in two types - CPU initiated and device initiated I/O data
transfer.

Input or output devices that are connected to computer are called peripheral devices. These devices
are designed to read information into or out of the memory unit upon command from the CPU and
are considered to be the part of computer system. These devices are also called peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
There are three types of peripherals:
1. Input peripherals: Allows user input, from the outside world to the computer.
Example: Keyboard, Mouse etc.
2. Output peripherals: Allows information output, from the computer to the
outside world. Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input(from outside world to computer)
as well as, output(from computer to the outside world). Example: Touch screen
etc.
Modes of Data Transfer:
Transfer of data is required between CPU and peripherals or memory or sometimes between any
two devices or units of your computer system. To transfer a data from one unit to another one

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should be sure that both units have proper connection and at the time of data transfer the receiving
unit is not busy. This data transfer with the computer is Internal Operation.

Intel 8085 I/O Structure

The data transfer can be handled by various modes. Some of the modes use CPU as anintermediate
path, others transfer the data directly to and from the memory unit.There are three major types of
data transfer:

1. Programmed I/O (PIO):

- PIO, or Programmed Input/output, is a method of transferring data from a device to another
device, utilizing the computer processor and not the memory or DMA. Because PIO modes
utilize the computer processor, using PIO is slower than DMA.
- This is different from Direct Memory Access(DMA) which is a technique for transferring data
within the main memory and external devices without passing through the CPU.

- Here the processor executes a program that gives it direct control of the I/O operation,
including sensing device status, sending a read or write command, and transferring the data.

- When the processor issues a command to the I/O module, it must wait until the I/O
operation is complete. If the processor is faster than the I/O module, this is wasteful of
processor time.

- The overall operation of the programmed I/O can be summaries as follow:

1. The processor is executing a program and encounters an instruction relating to I/O
operation.
2. The processor then executes that instruction by issuing a command to the appropriate
I/O module.

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3. The I/O module will perform the requested action based on the I/O command issued by
the processor (READ/WRITE) and set the appropriate bits in the I/O status register.
4. The processor will periodically check the status of the I/O module until it finds that the
operation is complete.

The microprocessor is busy all the time in checking for the availability of data from the slower I/O
devices. And also it is busy checking whether I/O device is ready for the data transfer or not. In other
words in this data transfer scheme, some of the microprocessor time is wasted in waiting while an
I/O device is getting ready. To overcome this problem interrupt driven I/O data transfer introduced.

The CPU issues a command then waits for I/O operations to be complete. As the CPU is faster than
the I/O module, the problem with programmed I/O is that the CPU has to wait a long time for the I/O
module of concern to be ready for either reception or transmission of data. The CPU, while waiting,
must repeatedly check the status of the I/O module, and this process is known as Polling. As a result,
the level of the performance of the entire system is severely degraded.

The transfer of data requires three instructions:

2. Read the status register
3. Check the status of the flag bit and branch to step1 if not set or to step3 if set.
4. Read the data register.
In this technique CPU is responsible for executing data from the memory for output
and storing data in memory for executing of Programmed I/O as shown in Flowchart-:

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Programmed I/O Data Transfer scheme of 8085 microprocessor can be work on synchronous or
asynchronous mode.
The data transfer can be synchronous or asynchronous it completely depends upon the type and the
speed of the I/O devices.

Synchronous type of data transfer

The basic feature of synchronous data transmission is that the data is transmitted or received
based on a clock signal and both the transmitter and receiver are synchronized with the
common clock signal.

It is also called clock oriented transmission because all bytes of block are transmitted
constantly. In this transmission, a block of data byte is transmitted along with the
synchronization information. Usually, one or two SYNC characters are used to indicate the
start of each synchronous data stream as shown below.

At the receiver side, as soon as it matches one or two SYNC characters based on the number
of SYNC character used, the receiver starts interpreting the data. In synchronous transmission,
the transmitting device needs to send data continuously to the receiving device. However, if
data is not ready to be transmitting, the transmitter will send SYNC characters until the data

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is available.

Synchronous type of data transfer can be used when the speed of the I/O devices matches with the
speed of the 8085 microprocessor. So for synchronization established between I/O device and
microprocessor we need common clock pulse. This common clock pulse synchronizes the
microprocessor and the I/O devices.

Synchronous type of data transfer scheme because of the matching of the speed, the microprocessor
does not have to wait for the availability of the data. The microprocessor immediately sends data for
the transfer as soon as the microprocessor issues a signal.

Asynchronous data transfer

In asynchronous data transmission, the transmitter and receiver need not to be synchronized
with the common clock signals.

Here each bit of message is sent a sequence at a time, and binary information is transferred only when
it is available. When there is no information to be transferred, line remains idle.

It is also called character oriented transmission, because only one character is transmitted at
a time. Each character carries a start bits and stop bits as synchronization information.
Transmission begins with one start bit that is at logic 0 (called space), followed by the required
information byte, which is always transmitted with LSB first and finally the stop bits that is
at logic 1 (called Mark). This formatting of data is known as “Framing”.

Asynchronous data transmission is shown below with the framing information.

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The asynchronous transmission is generally used in low speed transmission less than 20 Kbps,
but synchronous transmission transmits data greater than 20Kbps.

The asynchronous data transfer method is used when the speed of the I/O devices is slower than the
speed of the microprocessor. Because of the mismatch of the speed, the internal timing of the I/O
device is independent from the microprocessor. That is why two units are said to be asynchronous to
each other.

In this technique each character consists of three points :

i. Start bit
ii. Character bit
iii. Stop bit

i. Start Bit- First bit, called start bit is always zero and used to indicate the beginning
character.
ii. Stop Bit- Last bit, called stop bit is always one and used to indicate end of
characters. Stop bit is always in the 1- state and frame the end of the characters
to signify the idle or wait state.
iii. Character Bit- Bits in between the start bit and the stop bit are known as character
bits. The character bits always follow the start bit.

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The asynchronous data transfer is normally implemented using ‘handshaking’ mode. Now question
is what is handshaking mode? In the handshaking mode some signals are exchanged between the I/O
device and microprocessor before the data transfer takes place.

By this handshaking the microprocessor has to check the status to the input/output device. Now if the
device is ready for the data transfer or not.
 First step of microprocessor is initiates the I/O device to get ready.
 Then status of the I/O device is continuously checked by the microprocessor.
 This process remain continues until the I/O device becomes ready.
 After that microprocessor sends instructions to transfer the data.

Flow chart for this mode of data transfer is shown above.

Now form this below figure, the microprocessor sends a ready signal to I/O device. When the device is
ready to accept the data, the I/O device sends an ‘ACK’ (Acknowledge) signal to microprocessor. By
sending ACK, it indicates that the I/O device has acknowledged the ‘Ready’ signal. Now finally it is
ready for the transfer of data.

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Again in below figure shows the asynchronous handshaking process to transfer the data from the I/O
device to microprocessor. In this case I/O device issues the ready signal to microprocessor indicating that
I/O device is ready to send the data to microprocessor. In response to this signal, valid data signal is sent
by the microprocessor to I/O device and then the valid data is put on the data bus for the transfer.

Baud Rate
The serial data transmission rate is also called the baud rate. The baud rate is defined as the number
of bits of data transmitted per second. Since each bit is transmitted over a duration of one interval,
Baud rate = 1/Bit Interval = Bits/Sec.

In parallel I/O, data bits are transferred when a control signal enables the interfacing device; the
transfer takes place in less than three T-states. However, in serial I/O, one bit is sent out at a time;
therefore, how long the bit stays on or off is determined by the speed at which the bits are
transmitted. Furthermore, the receiver should be set up to receive the bits at the same rate as the
transmission; otherwise, the receiver may not be able to differentiate between two consecutive 0s
and1s.

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Drawback of the Programmed I/O:

The main drawback of the Program Initiated I/O was that the CPU has to monitor the units all the times
when the program is executing. Thus the CPU stays in a program loop until the I/O unit indicates that it
is ready for data transfer. This is a time consuming process and the CPU time is wasted a lot in keeping
an eye to the executing of program.
To remove this problem an Interrupt facility and special commands are used.

Memory mapped I/O

Memory mapped I/O is a way to exchange data and instructions between a CPU and peripheral devices
attached to it. Memory mapped IO is one where the processor and the IO device share the same memory
location (memory),i.e., the processor and IO devices are mapped using the memory address.

2. Interrupt driven I/O:

An interrupt is a signal to the microprocessor from a device that requires attention.

A device controller puts an interrupt signal on the bus when it needs CPU’s attention when CPU receives
an interrupt; It saves its current state and invokes the appropriate interrupt handler using the interrupt
vector (addresses of OS routines to handle various events). When the interrupting device has been dealt
with, the CPU continues with its original task as if it had never been interrupted.
The interrupt driven I/O data transfer method is very efficient because no microprocessor time is wasted
in waiting for an I/O device to be ready. In this interrupt driven I/O data transfer method the I/O device
informs the microprocessor for the data transfer whenever the I/O device is ready. This is achieved by
interrupting the microprocessor. As we know that the interrupt is hardware facilities provided on the
microprocessor.

.
Although Interrupt relieves the CPU of having to wait for the devices, but it is still inefficient in data
transfer of large amount because the CPU has to transfer the data word by word between I/O module
and memory.

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Below are the basic operations of Interrupt:

 CPU issues read command
 I/O module gets data from peripheral whilst CPU does other work
 I/O module interrupts CPU
 CPU requests data
 I/O module transfers data

In this type of I/O, computer does not check the flag. It continues to perform its task.
• Whenever any device wants the attention, it sends the interrupt signal to the CPU.
• CPU then deviates from what it was doing, store the return address from PC and
branch to the address of the subroutine.
• There are two ways of choosing the branch address:
 Vectored Interrupt
 Non-vectored Interrupt
In vectored interrupt, the source that interrupts the CPU provides the branch information. This
information is called interrupt vectored while in non-vectored, interrupt, the branch address is assigned
to the fixed address in the memory.

Priority Interrupt:
• There are number of IO devices attached to the computer.
• They are all capable of generating the interrupt.
• When the interrupt is generated from more than one device, priority interrupt system is used
to determine which device is to be serviced first.
• Devices with high speed transfer are given higher priority and slow devices are given lower
priority.
• Establishing the priority can be done in two ways:
 Using Software
 Using Hardware
• A polling procedure is used to identify highest priority in software means.

Handshaking
I/O devices accept or release information at much slower rate than the microprocessor. Handshaking is the
method that synchronizes the I/O device with microprocessor. In the handshaking mode some signals are
exchanged between the I/O device and microprocessor before the data transfer takes place.
A printer connected to the parallel port requires handshaking.

Types of handshakes in parallel interfacing:

1. Single handshake
2. Double handshake

Single Handshake (Parallel)

• In single handshake, a peripheral device first sends a "Strobe signal" to the microprocessor to indicate
that it is ready to send data.
• The microprocessor, upon detecting the strobe signal, opens up its input port and receives the data.

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• After receiving data, it sends an "Acknowledge signal" to the peripheral to indicate that transmission
has been completed.
• A transmission session has been completed.

Double Handshake (Parallel)

• In double handshake, first the peripheral devices sends a strobe signal, the
microprocessor, sends the acknowledge signal to indicate that it is ready to receive data.
• After that data is received.
• After sending data, the peripheral sends a strobe signal to indicate data
transmission completion, due to which, the microprocessor drops its
acknowledge signal and a session has been completed.
Advantage of the Handshaking method:
• The Handshaking scheme provides degree of flexibility and reliability because the
successful completion of data transfer relies on active participation by both units.
• If any of one unit is faulty, the data transfer will not be completed. Such an error
can be detected by means of a Timeout mechanism which provides an alarm if the
data isnot completed within time.

Polling I/O
Polling is the simplest way for an I/O device to communicate with the processor. The process of
periodically checking status of the device to see if it is time for the next I/O operation is called
polling. The I/O device simply puts the information in a Status register, and the processor must come
and get the information.

Most of the time, devices will not require attention and when one does, it will have to wait until it is
next interrogated by the polling program. This is an inefficient method and much of the processors
time is wasted on unnecessary polls.

Compare this method to a teacher continually asking every student in a class, one after another, if
they need help. Obviously the more efficient method would be for a student to inform the teacher
whenever they require assistance.

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INTERRUPT

Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of
processor and get itself serviced. It is a signal send by an external device to the processor, to the
processor to perform a particular task or work.

When the Microprocessor receives an interrupt signal, it suspends the currently executing program
and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt
will most probably have its own ISR.

When a peripheral is ready for data transfer, it interrupts the processor by sending an appropriate
signal to the interrupt pin of the processor. If the processor accepts the interrupt then the processor
suspends its current activity and executes an interrupt service subroutine to complete the data transfer
between the peripheral and processor. After executing the interrupt service routine the processor
resumes its current activity. This type of data transfer scheme is called interrupt driven data transfer
scheme.

What happens when microprocessor is interrupted?

The 8085 interrupt process can be summarized as follows:
Step 1: The interrupt process should be enabled by writing the instruction EI in
the main program.
Step 2: MPU checks the INTR line during the execution of each instruction.
Step 3: If INTR line is high and interrupt is enabled, MPU completed the
current instruction, disable the interrupt and sent an acknowledge signal INTA.
Step 4: The signal INTA is used to insert a restart (RST) instruction through
external hardware.
The RST instruction transfers the program control to specific memory location.
Step 5: When microprocessor receives RST instruction, it saves the memory address of next
instruction on the stack. The program control is transferred to call location.
Step 6: The ISR perform the specific task of the interrupt. The ISR must include
EI instruction to enable the interrupt.
Step 7: At the end of ISR, the RET instruction returns the memory address from where the
program was interrupted and continues the execution.
The processor will check the interrupts always at the 2nd T-state of last machine cycle.
• If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the
peripheral.
• The vectored address of particular interrupt is stored in program counter.
• The processor executes an interrupt service routine (ISR) addressed in program counter.

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Responding to an interrupt may be immediate or delayed depending on whether the interrupt is

maskable or non-maskable and whether interrupts are being masked or not.

Interrupt Service Routine (ISR) is a small program or a routine that when executed services the
corresponding interrupting source is called as an ISR.

Interrupt Handling Procedure

The Processor will have to store the information about the current program when an interrupt signal
is recognized before executing the ISR. The processor checks for the Interrupt request signals at the
end of every instruction execution. If the interrupt is masked, then the interrupt will not be recognized
until interrupts are re-enabled. The sequence of operations that take place when an interrupt signal is
recognized is as followed. The CPU responds to an interrupt request by a transfer of control to another
program in a manner similar to a subroutine call. Save the PC (Program Counter) contents (address
of the next instruction) and supplementary information about current state (flags, registers, etc.) to
the stack. Load PC with the beginning address of an Interrupt Service Routine (ISR) and start to
execute it. Finish ISR when return instruction is executed. Return to the interrupted program, exactly
to the same point from which it left.

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Figure2.5: Transfer of control from Main memory to ISR

There are two ways of redirecting the execution to the ISR depending on whether the interrupt is
vectored or non-vectored. – Vectored: The address of the subroutine is already known to the
Microprocessor – Non Vectored: The device will have to supply the address of the subroutine to the
Microprocessor

Interrupt are classified into the following groups based on their parameter −
 Software interrupt: - These instructions are inserted at desired locations in a
program. While running a program, lf a software interrupt instruction is encountered, then
the processor executes an interrupt service routine (ISR). There are 8 software interrupts in
8085. From RST0 to RST7.
1. RST0
2. RST1
3. RST2
4. RST3
5. RST4
6. RST5
7. RST6
8. RST7
They allow the microprocessor to transfer program control from the main program to the subroutine
program. After completing the subroutine program, the program control returns back to the main
program.
We can calculate the vector address of these interrupts using the formula given below:
Vector Address = Interrupt Number * 8
For Example:
RST2: vector address=2*8 = 16
RST1: vector address=1*8 = 08
RST3: vector address=3*8 = 24

Vector address table for the software interrupts:

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Interrupt Vector Address

RST0 0000H
RST1 0008H

RST2 0010H
RST3 0018H

RST4 0020H
RST5 0028H

RST6 0030H
RST7 0038H

 Hardware interrupt
There are 5 interrupt pins in 8085 used as hardware interrupts,
1. TRAP
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. INTR
The hardware interrupts are initiated by an external device by placing an appropriate signal at the
interrupt pin of the processor. If the interrupt is accepted, then the processor executes an interrupt
service routine (ISR).

Note − INTA is not an interrupt; it is used by the microprocessor for sending acknowledgement.
TRAP has the highest priority, then RST7.5 and so on.

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TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is
enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup
memory. This interrupt transfers the control to the location 0024H.
In summarized and point form
• TRAP has the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This means that the TRAP must go high and
remain high until it is acknowledged.
• In sudden power failure, it executes a ISR and send the data from main memory to backup
memory.
• The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD
and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
• There are two ways to clear TRAP interrupt. By
1. resetting microprocessor (External signal)
2. giving a high TRAP ACKNOWLEDGE (Internal signal)
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt
is executed, the processor saves the content of the PC register into the stack and branches to 003CH
address.

In summarized and point form

- The RST 7.5 interrupt is a maskable interrupt.
- It has the second highest priority.
- It is edge sensitive. i.e. Input goes to high and no need to maintain high state until it
recognized.
- Maskable interrupt. It is disabled by,
1. DI (Disable Interrupts) instruction
2. System or processor reset or
3. after reorganization of interrupt.
- Enabled by EI (Enable Interrupts) instruction.

RST 6.5 and 5.5:

- The RST 6.5 and RST 5.5 both are level triggered i.e. Input goes to high and stay high until
it recognized.
- Maskable interrupt. It is disabled by,

1. DI, SIM (Set Interrupt Mask - used to provide interrupt services of the 8085) instruction
2. System or processor reset.
3. After reorganization of interrupt.
- Enabled by EI instruction.
- When interrupt is executed, the processor saves the content of the PC register into the stack
and branches to 002CH address that is for the case of 5.5
- When this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 0034H address that is for the case of 6.5

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- The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the
microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of each instruction.
 When the INTR signal is high, then the microprocessor completes its current instruction and sends
active low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address of the next instruction on
stack and executes the received instruction.
The INTR is different from other four interrupts. This interrupt is not automatically vectored as other
interrupts do. When INTR is requested, an external hardware connected to the data bus delivers one restart
instruction out of eight restart instruction discussed below and according to which the microprocessor is
vectored or transferred to the particular memory location.

These are 1-byte Call instructions that transfer the program execution to a specific memory location on page
00H. The RST instructions are executed in a similar way to hat of Call instructions. The address in the
Program Counter (meaning the address of the next instruction to an RST instruction) is stored on the stack
before the program execution is transferred to the RST call location. When a processor encounters a Return
instruction in the subroutine associated with the RST instruction, the program returns to the address that was
stored on the stack.

In summarized and point form

• It is disabled by,
1. DI, SIM instruction
2. System or processor reset.
3. After reorganization of interrupt.
• Enabled by EI instruction.
• Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of
ISR.
• It has lowest priority.

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• It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain high state until
it recognized.
• The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active low
interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction OPCODE on the
data bus. In the case of multi-byte instruction, additional interrupt acknowledge machine
cycles are generated by the 8085 to transfer the additional bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on stack and
execute received instruction.

Vector interrupt: - In this type of the address of the service routine is hard-wired. the CPU actually knows
the address of the Interrupt Service Routine in advance. The interrupt address is known to the processor.
The interrupting device directs the processor to the appropriate interrupt service routine. For
example: RST7.5, RST6.5, RST5.5, and TRAP.

Non-Vector interrupt: - In this type of interrupt the address of the service routine needs to be supplied
externally by the device. The interrupt address is not known to the processor so, the interrupt address needs
to be sent externally by the device to perform interrupts. For example: INTR.

Maskable interrupt (Can be delayed or Rejected) − In this type of interrupt, we can disable the interrupt
by writing some instructions into the program. For example:RST7.5, RST6.5, RST5.5.

Non-Maskable interrupt (Cannot be delayed or Rejected) − In this type of interrupt, we cannot disable
the interrupt by writing some instructions into the program. For example: TRAP.

Important to Note
Hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. In vectored interrupts, the
processor automatically branches to the specific address in response to an interrupt. But in non-
vectored interrupts the interrupted device should give the address of the interrupt service routine (ISR).

Masking is preventing the interrupt from disturbing the main program. When an interrupt is masked the
processor will not accept the interrupt signal. The interrupts can be masked by moving an appropriate data
(or code) to accumulator and then executing SIM instruction.

The status of maskable interrupts can be read into accumulator by executing RIM instruction (RIM - Read
Interrupt Mask).

All the hardware interrupts, except TRAP are disabled, when the processor is resetted. They can also be
disabled by executing Dl instruction. (Dl-Disable Interrupt).

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When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR, RST 5.5, RST 6.5 and
RST 7.5 are disabled by DI instruction and upon hardware reset).

To enable (to allow) the disabled interrupt, the processor has to execute El instruction (El-Enable Interrupt).

The 8085 Interrupt Structure is shown in figure below. In order to enable the interrupt, we use the
instructions EI and SIM. The execution of EI instruction sets the RS flip flop and makes one of the inputs
to the AND gate 1 to 4 HIGH. Hence, in order for all the interrupts (except TRAP) to work, the interrupt
system must be enabled.

The 8085 interrupt structure is shown in figure 2.5.The maskable interrupts are by default masked by the
RESET signal. So, any interrupt will not be recognized by the hardware reset. The interrupts can be enabled
by the execution of the instruction, EI – Enable interrupts. The three RST interrupts can be selectively masked
by having proper word in Accumulator and executing the SIM (Set Interrupt Mask) instruction. This is called
software masking.

All the maskable interrupts are disabled whenever an interrupt is recognized. So, it is necessary to execute
EI instruction every time the interrupts are recognized and serviced by the processor. All the maskable
interrupts can be disabled by executing an instruction DI – Disable Interrupts. This instruction will reset an
interrupt enable flip flop in the processor and the interrupts will be disabled. To enable interrupts, EI
instruction has to be executed.

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• Consider only the RST 7.5 Interrupt is to be enabled, the interrupt mask bit for RST 7.5 is set to
low, making the two inputs to AND gate 1 HIGH. Now, if there is the interrupt signal to RST 7.5
pin, it sets the D flip flop, thus making the O/P of AND gate 1 HIGH and enables RST 7.5.
• The 8085 branches to location 003CH to service routine.
• RST 6.5 and RST 5.5 can be similarly explained.
• Execution of the DI instruction clears RS flip flop and disables all the interrupts except TRAP.

The sequence of operations for an interrupt driven data transfer scheme is shown in figure below.

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Serial or Daisy Chain (vectored) Priority Interrupt

In this scheme, peripherals are linked together in a series setup. When the CPU acknowledges an input it is
sent down the line, passed from device to device, until a device that issued an interrupt request responds.
The individual devices are prioritized by their position within the chain.

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How it works
• Device with highest priority is placed first.
• Device that wants the attention send the interrupt request to the CPU.
• CPU then sends the INTACK signal which is applied to PI (priority in) of the firstdevice.
• If it had requested the attention, it places its VAD (vector address) on the bus. And itblock the
signal by placing 0 in PO(priority out)
• If not it pass the signal to next device through PO (priority out) by placing 1.
• This process is continued until appropriate device is found.
• The device whose PI is 1 and PO is 0 is the device that send the interrupt request.

Advantages of interrupt over Polling

• Interrupts are used when you need the fastest response to an event. For example, you need to
generate a series of pulses using a timer. The timer generates an interrupt when it overflows and
within 1 or 2 sec, the interrupt service routine is called to generate the pulse. If polling were used,
the delay would depend on how often the polling is done and could delay response to several
milliseconds. This is thousands times slower.

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• Interrupts are used to save power consumption. In many battery powered applications, the
microcontroller is put to sleep by stopping all the clocks and reducing power consumption to a few
micro amps. Interrupts will awaken the controller from sleep to consume power only when needed.
Applications of this are hand held devices such as TV/VCR remote controllers.
• Interrupts can be a far more efficient way to code. Interrupts are used for program debugging.

In a nutshell
8085 supports two types of interrupts. They are
1. Hardware interrupts-
 Peripheral device activates interrupt by activating the respective pin.
 In response to the interrupt request, microprocessor completes the current instruction execution
in main program and transfer program control to interrupt service routine.
 In ISR routine, required task is completed. Task may be to read data, to write data, to update the
status, to update the counter etc.
 After completing the task, the program control is transferred back to the main program. These
types of interrupts where the microprocessor pins are used to receive interrupt requests are
called hardware interrupts.
 The microprocessor 8085 has five hardware interrupts. They are TRAP, RST 7.5, RST 6.5, RST
5.5 and INTR.

2. Software interrupts-
 In case of software interrupts the cause of the interrupt is the execution of the instruction.
 The microprocessor 8085 has eight instructions. These eight instructions are RST 0 to RST 7. Such
interrupts are called as software interrupts.
 They allow the microprocessor to transfer program control from the main program to the
subroutine program i.e. predefined service routine addresses.
 Predefined service routine is also referred to as ISR.
 After completing the subroutine program, the program control returns back to the main program.

Programmable interrupt controller

A programmable interrupt controller (PIC) is a device that is used to combine several sources
of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs.
When the device has multiple interrupt outputs to assert, it asserts them in the order of their relative priority.
Common modes of a PIC include hard priorities, rotating priorities, and cascading priorities.

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The INTR pin can be used for multiple peripherals and to determine priorities among these devices when
two or more peripherals request interrupt service simultaneously, PIC is used. If there are simultaneous
requests, the priorities are determined by the encoder, it responds to the higher level input, ignoring the lower
level input.

The drawback of the scheme is that the interrupting device connected to input I7 always has the highest
priority. The PIC includes a status register and a priority comparator in addition to a priority encoder.

Today this device is replaced by a more versatile one called a programmable interrupt controller 8259A.

The 8259A is a programmable interrupt controller

The 8259A is a programmable interrupt controller specially designed to work with Intel microprocessor
8080, 8085A, 8086, 8088. The main features of 8259A programmable interrupt controller are given below:

1. It can handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on the
processor in place of one INTR (in 8085A)/INT(in 8086) pin.
2. The chip can vector an interrupt request anywhere in the memory map from 0000H to FFFFH in
8085A microprocessor. However, all the eight interrupts are spaced at an interval of either four or
eight locations. This eliminates the major drawback of 8085A interrupts in which all interrupts are
vectored to memory location on page 00H i.e., TRAP, RST7.5, RST6.5 and RST5.5 are vectored to
memory locations 0024H, 003CH, 0034H and 002CH respectively.

3. It can resolve eight levels of interrupt priorities in a variety of modes. The priorities of interrupts can
be changed under running condition. Some of the desired lower priority interrupts may be allowed to
be acknowledged during the service of higher priority
interrupts.

4. Each of the interrupt requests can be masked individually similar to RST7.5, RST6.5 and RST5.5
interrupts of 8085A.

5. The status of pending interrupts, in service interrupts, and masked interrupts can be read at any time
similar to RST interrupts of 8085A.

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6. The chip can be programmed to accept interrupt requests either as level triggered or edge triggered
interrupt request unlike your RST interrupts where some are edge triggered and some are level
triggered. However, all interrupts must be either level
triggered or edge triggered.

7. If required, nine 8259As can be cascaded in a master-slave configuration mode to handle 64 interrupt
inputs. In this case, the interrupting devices send their interrupt requests either to slave 8259A or to
master 8259A directly. The slave 8259As send their interrupt to master interrupt request inputs and
the master will send a single interrupt to microprocessor interrupt pin INTR/INT.

The pin diagram and internal block diagram of PIC is shown in figure. The pins are defined as follows:

CS (Chip Select signal): To access this chip, chip select signal CS is made low. A LOW on this pin enables
RD & WR communication between the CPU and the 8259A. This signal is made LOW by decoding the
addresses assigned to this chip. Therefore, this pin is connected to address bus through the decoder logic
circuit. Interrupt acknowledge functions to transfer the control to interrupt service subroutine are independent
of CS.

WR (Write signal): A low on this pin. When CS is low enables the 8259 A to accept command words from
CPU.
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RD (Read signal): A low on this pin when CS is low enables this 8259A to release status (pending interrupts
or in-service interrupts or masked interrupts) on to the data bus for the CPU. The status includes the contents
of IMR (interrupt mask register) or ISR (interrupt service register) or IRR (interrupt request register) or a
priority level.

D7-D0 (Data Bus): Bidirectional data bus. Control, status and interrupt vector information is transferred via
this data bus. This bus is connected to BDB of 8085A.

CAS2-CAS0 (Cascade lines): The CAS2-0 lines form a local 8259A bus to control multiple 8259As in master-
slave configuration, i.e., to identify a particular slave 8259A to be accessed for transfer of vector information.
These pins are automatically set as output pins for master 8259A and input pins for a slave 8259A once the
chips are programmed as master or slave.

SP/EN (Salve Program/Enable Buffer): This is a dual function pin. When the chip is programmed in buffered
mode, the pin can be used as an output and when not in the buffered mode it is used as an input. In non-
buffered mode it is used as an input pin to determine whether the 8259A is to be used as a master (SP/EN =
1) or as a slave (SP/EN = 0). In buffered mode, normally data bus buffers are used. These buffers need to be
enabled or disabled during transfer of vector information depending upon whether 80259A is connected
before the buffer or after the buffer. To disable/enable the data bus transceivers (buffers) when data are being
transferred from the 8259A to the CPU, this pin is made low or high.

INT (Interrupt output): This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt
the CPU, thus it is connected to the CPU’s interrupt pin (INTR). In case of master-slave configuration, the
interrupt pin of slave 8259A is connected to interrupt request input of master 8259A.

INTA (Interrupt Acknowledge): This pin is used to enable 8259A interrupt vector data on the data bus by a
sequence of interrupt acknowledge pulses issued by the CPU.

IR0-IR7 (Interrupt Request inputs): These are asynchronous interrupt request input pins. An interrupt request
is executed by raising an IR input (low to high), and holding it high until it is acknowledged. (Edge triggered
mode) or just by a high level on an interrupt request input (Level triggered mode).

A0 (A0 address line): This pin acts in conjunction with the RD , WR & CS pins. It is used by the 8259A to
send various command words from the CPU and to read the status. It is normally connected to the CPU A 0
address line. Two addresses are assigned/ reserved in the I/O address space for each 8259A in the system-
one with A0 =0 is called even address and other with A0 = 1 is called odd address.

Functional Description:
The 8259A (PIC) has eight interrupt request inputs – IR7 - IR0. The 8259A uses its INT output to interrupt
the 8085A via INTR pin.

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It receives interrupt acknowledge pulses from the 𝜇𝑝 at its INTA input. Vector address, used by the 8085A
to transfer control to the service subroutine of the interrupting device, is provided by the 8259A on the data
bus.

It is a programmable device that must be initialized by command words sent by the microprocessor. After
initialization the 8259A mode of operation can be changed by operation command words from the
microprocessor.

It contains following blocks:

 Data bus buffer: It is used to transfer data between microprocessor and internal bus.
 Control logic: It generates an INT signal. In response to an INTA signal, it releases three byte CALL
address or one byte vector number. It controls read/write control logic, cascade buffer/comparator, in
service register, priority resolver and IRR.
 Cascade buffer and comparator: In master mode, it functions as a cascaded buffer. The cascaded
buffers outputs slave identification number on cascade lines. In slave mode, it functions as a
comparator. The comparator reads slave identification number from cascade lines and compares this
number with its internal identification number. In buffered mode it generates an EN signal.
 Read/write logic: It sets the direction of data bus buffer. It controls all internal read/write operations.
It contain initialization and operation command register.

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 IRR(Interrupt Request Register) : It is used to store all pending interrupt requests. Each bit of this
register is set at the rising edge or at the high level of the corresponding interrupt request line. The
microprocessor can read contents of this register by issuing appropriate, command word.
 InSR (In-Service Register): It is used to store all interrupt levels currently being serviced. Each bit
of this register is set by priority resolver and reset by end of interrupt command word. The
microprocessor can read contents of this register by issuing appropriate command word.
 IMR (Interrupt Mask Register): It is a programmable register. It is used to mask unwanted interrupt
request, by writing command word. The microprocessor can read contents of this register without
issuing any command word.
 Priority resolver: It determines the priorities of the bit set in the IRR. To make decision, the priority
resolver looks at the ISR. If the higher priority bit in the InSR is set then it ignores the new request.
If the priority revolver finds that the new interrupt has a higher priority than the highest priority
interrupt currently being serviced and the new interrupt is not in service, then it will set appropriate
bit in the InSR and send the INT signal to the microprocessor for new interrupt request.

Multiprogramming
Multiprogramming is a rudimentary (basic) form of parallel processing in which several programs are run at
the same time on a uniprocessor. Since there is only one processor, there can be no true simultaneous
execution of different programs. Instead, the operating system executes part of one program, then part of
another, and so on. To the user it appears that all programs are executing at the same time.

If the machine has the capability of causing an interrupt after a specified time interval, then the operating
system will execute each program for a given length of time, regain control, and then execute another
program for a given length of time, and so on. In the absence of this mechanism, the operating system has
no choice but to begin to execute a program with the expectation, but not the certainty, that the program will
eventually return control to the operating system.

Job scheduling
The allocation of system resources to various tasks, known as job scheduling, is a major assignment of the
operating system. The system maintains prioritized queues of jobs waiting for CPU time and must decide
which job to take from which queue and how much time to allocate to it, so that all jobs are completed in a
fair and timely manner.

In a computer system, system resources are the components that provide its inherent capabilities and
contribute to its overall performance. System memory, cache memory, hard disk space, IRQs and DMA
channels are examples.

Job scheduling is the process of allocating system resources to many different tasks by an operating system
(OS). The system handles prioritized job queues that are waiting CPU time and it should determine which
job to be taken from which queue and the amount of time to be allocated for the job. This type of scheduling
makes sure that all jobs are carried out fairly and on time.

Job scheduling is performed using job schedulers. Job schedulers are programs that enable scheduling and,
at times, track computer "batch" jobs, or units of work like the operation of a payroll program.

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DIRECT MEMORY ACCESS (DMA)

DMA is a method that allows an input/output (I/O) device to send or receive data directly to or from the
main memory, bypassing (without passing through) the CPU to speed up memory operations. The process
is managed by a chip known as a DMA controller

It is a method of transferring data from the computer's RAM to another part of the computer without
processing it using the CPU. While most data that is input or output from a computer is processed by the
CPU, some data does not require processing, or can be processed by another device. In these situations, DMA
can save processing time and is a more efficient way to move data from the computer's memory to other
devices.

For example, a sound card may need to access data stored in the computer's RAM, but since it can process
the data itself, it may use DMA to bypass the CPU. Video cards that support DMA can also access the system
memory and process graphics without needing the CPU. Ultra DMA hard drives use DMA to transfer data
faster than previous hard drives that required the data to first be run through the CPU.

In order for devices to use direct memory access, they must be assigned to a DMA channel. Each type of port
on a computer has a set of DMA channels that can be assigned to each connected device. For example,
a PCI controller and a drive controller each have their own set of DMA channels.

Using DMA technique large amounts of data can be transferred between memory and the peripheral without
severely impacting CPU performance.

During the DMA transfer, the CPU is idle and has no control of the memory buses. A DMA controller takes
over the buses to manage the transfer directly between the I/O device(s) and main memory.

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Fig. Connection between DMA data bus and device controllers.

The CPU may be placed in an idle state in a variety of ways. One common method extensively used in
microprocessor is to disable the buses through special control signals such as:
• Bus Request (BR)
• Bus Grant (BG)
These are the two control signals in the CPU that facilitates the DMA transfer. The Bus Request (BR) input
is used by the DMA controller to request the CPU. When this input is active, the CPU terminates the
execution of the current instruction and places the address bus, data bus and read write lines into a high
Impedance state. High Impedance state means that the outputis disconnected.

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The CPU activates the Bus Grant (BG) output to inform the external DMA that the Bus Request (BR) can
now take control of the buses to conduct memory transfer without processor.

When the DMA terminates the transfer, it disables the Bus Request (BR) line. The CPU disables the Bus
Grant (BG), takes control of the buses and return to its normal operation.

DMA Transfer Modes

There are 3 different modes of DMA data transfer. They vary by how DMA controller determines when to
transfer data (but actual data transfer process remains the same in all three cases).
(a) Burst Mode
 Entire block of data is transferred in one continuous sequence.
 Once the DMA controller is granted access to the system bus by CPU, it transfers all bytes of data
in the data block before relinquishing control of system buses back to the CPU.
 This mode is useful for loading programs or data files into memory, but it keeps CPU idle for
relatively long period of time.
(b) Cycle Stealing Mode
 Cycle stealing allows the DMA controller to transfer one data word at a time, after which it must
returns control of the buses to the CPU.
 It continually issues requests using Bus Request (BR) signals, transferring one byte of data per
request, until it has transferred its entire block of data. (Steals one CPU cycle).
 The data block is not transferred as quickly as in burst mode, but the CPU is not idled for long
period of time as in burst mode.
(c) Transparent Mode
 DMA controller only transfers data when CPU is performing operations that do not use system
buses.
 The main advantage of this mode is that CPU never stops executing its program.
 The main disadvantages of this mode are

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 Hardware needed to determine when the CPU is not using the system buses can be quite complex
and relatively expensive.
 Requires highest time to transfer a block of data as compared to above two modes.

DMA Controller:
The DMA controller needs the usual circuits of an interface to communicate with the CPU and I/O device.
The DMA controller has three registers:
i. Address Register
ii. Word Count Register
iii. Control Register

Address Register: - Address Register contains an address to specify the desired location in memory.

Word Count Register: - WC holds the number of words to be transferred. The register is incremented
/decremented by one after each word transfer and internally tested for zero.

Control Register: - Control Register specifies the mode of transfer. The unit communicates with the CPU
via the data bus and control lines. The registers in the DMA are selected by the CPU through the address bus
by enabling the DS (DMA select) and RS (Register select) inputs. The RD (read) and WR (write)inputs are
bidirectional.

When the BG (Bus Grant) input is 0, the CPU can communicate with the DMA registers through the data
bus to read from or write to the DMA registers. When BG =1, the DMA can communicate directly with the
memory byspecifying an address in the address bus and activating the RD or WR control.

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The control unit communicates with the CPU via data bus and control lines.

The DMA controls/relinquishes the system bus using BR (Bus Request) and BG (Bus Grant) signals. DMA
operates read and write operations via RD (Read) and WR (Write) signals.
DMA sends request and acknowledge to I/O devices via DMA request and DMA acknowledge signals.

The registers in DMA are selected by CPU through the address bus by enabling DS (DMA Select) and RS
(Register Select) inputs. All registers in the DMA appear to the CPU as I/O interface registers.

The address register contains an address to specify the desired location in memory. It is incremented after
each word that is transferred to the memory.

The word count register holds the number of words to be transferred. It is decremented by one after each
word transfer and internally tested for zero.

The control register specifies the mode of transfer.

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DMA Transfer:
The CPU communicates with the DMA through the address and data buses as with any interface unit. The
DMA has its own address, which activates the DS and RS lines. The CPU initializes the DMA through the
data bus. Once the DMA receives the start control command, it can transfer between the peripheral and the
memory.

When BG = 0 the RD and WR are input lines allowing the CPU to communicate with the internal DMA
registers.

When BG=1, the RD and WR are output lines from the DMA controller to the random access memory to
specify the read or write operation of data.

INTERFACING DEVICES
Interface: A boundary across which two independent systems meet and act on or communicate with each
other.

It is a common boundary where direct contact between two different devices occurs, and where information
is exchanged.

In computer technology, the following types of interfaces can be defined:

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1. User interface - the keyboard, mouse, menus of a computer system. The user interface allows
the user to communicate with the operating system.
2. Software interface - the languages and codes that the applications use to communicate with
each other and with the hardware.
3. Hardware interface - the wires, plugs and sockets that hardware devices use to communicate
with each other. For example, a printer typically connects to a computer via a USB interface.
Therefore, the USB port on the computer is considered the hardware interface.

Input Output Interface provides a method for transferring information between internal storage and external
I/O devices. Peripherals connected to a computer need special communication links for interfacing themwith
the central processing unit.

The purpose of communication link is to resolve the differences that exist between the central computer
and each peripheral.
The Major Differences are:
1. Peripherals are electrometrical and electromagnetic devices and CPU and memory are electronic
devices. Therefore, a conversion of signal values may be needed.
2. The data transfer rate of peripherals is usually slower than the transfer rate of CPU and consequently,
a synchronization mechanism (Data transfer method in which signals are sent and received in spurts
and not in a continuous stream) may be needed.
3. Data codes and formats in the peripherals differ from the word format in the CPU and memory.
4. The operating modes of peripherals are different from each other and must be controlled so as not to
disturb the operation of other peripherals connected to the CPU.

To resolve these differences, computer systems include special hardware components between the CPU and
Peripherals to supervise and synchronize all input and out transfers. These components are called Interface
Units because they interface between the processor bus and the peripheral devices.

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What happens during data Transfer

For data transfer from input device to processor the following operations are performed.
 The input device will load the data to the port.
 When the port receives a data, it sends message to the processor to read the
data.
 The processor will read the data from the port.
 After a data have been read by the processor the input device will load the next
data into the port.
For data transfer from processor to output device the following operations are performed.
 The processor will load the data to the port.
 The port will send a message to the output device to read the data.
 The output device will read the data from the port.
 After the data have been read by the output device the processor can load the next data
to the port.

8085 Interfacing Pins

Following is the list of 8085 pins used for interfacing with other devices −
 A15 - A8 (Higher Address Bus)
 AD7 - AD0(Lower Address/Data Bus)
 ALE
 RD
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 WR
 READY

Ways in whichmicroprocessor Communicates with the outside World

There are two ways of communication in which the microprocessor can connect with the outside world.
 Serial Communication Interface
 Parallel Communication interface

Serial Communication Interface

In Serial Communication, transfer of data is bit by bit using a single line or wire. For two way
communication between the transmitter and receiver, we need just two wires for successful serial data
transfer.

In this type of communication, the interface gets a single byte of data from the microprocessor and sends it
bit by bit to the other system serially and vice-a-versa.

Since serial communication needs less circuitry and wires, the cost of implementing is less. As a result, using
serial communication in complex circuitry might be more practical than parallel communication.

But the only concern with serial data transfers is speed. Since the data transfer occurs over a single line, the
speed of transfer in serial communication is less than that of parallel communication. Nowadays, the speed
of serial data transfer is not a concern as advancements in technology have led to faster transfer speeds.

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Parallel Communication Interface

In parallel data transfer, all the bits are transferred from the source to destination at once.
This is possible because parallel data transfer uses multiple lanes or wires between the transmitter and
receiver in order to transfer the data.

Parallel Data Transfer methods are faster and expensive as they need more hardware and a lot of wires.
Olden day’s printers are the best example for external parallel communication. Other examples are RAM,
PCI, etc.

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With the progress in integrated circuit technology, the digital IC’s are becoming smaller and faster and as a
result the transfer rates in Parallel Communication with multiple lanes have reached a bottle neck.

Method of Parallel Data Transfer

1. Simple Input & Output
In the simple input and output parallel data transfer method, microprocessor assumes that peripheral
devices are always present and ready to communicate with the microprocessor.

For example, consider the simple display device such as LED is always there and ready, so microprocessor
can send data to it at any time.
2. Simple Strobe Input & Output
In many applications, valid data is present on an external device only at a certain time, so it must be read in
at that time.

For example, consider the keyboard. When a key is pressed, keyboard sends out the ASCII Code for the
pressed key on eight parallel data lines, and then sends out a strobe signal (STB) on another line to indicate
that valid data is present to transmit.

3. Single Handshake with Input & Output

In this method, the peripheral sends some parallel data and then sends the STB signals to the
microprocessor. The microprocessor detects the STB signal on a polled or interrupt basis and read in the
byte of data. Then microprocessor sends an acknowledge signal (ACK) to the peripheral device to indicate
that the data has been read and that the peripheral can send the next byte of data.

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4. Double Handshake with Input & Output

For data transfer where even more coordination is required between the sending system and receiving
system, a double handshake is used.

First of the entire data sending device asserts STB signal low to ask, “Are you ready?” The receiving
system raises its ACK line high to indicate that it is ready. The sending device (Computer/Peripheral)
then sends the bytes of data and raises its STB signal high to say, “Here is some valid data for you”. After
receiving the data, the receiving system low its ACK signal to indicate that it has received the data and
waiting for next byte of data.

In Summery

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UART
UART stands for Universal Asynchronous Receiver Transmitter and is a serial communication device that
performs parallel – to – serial data conversion at the transmitter side and serial – to – parallel data conversion
at the receiver side. It is universal because the parameters like transfer speed, data speed, etc. are
configurable.

The hardware for UART can be a circuit integrated on the microcontroller or a dedicated IC.

It is one of the most simple and most commonly used Serial Communication techniques. Today, UART is
being used in many applications like GPS Receivers, Bluetooth Modules, GSM and GPRS Modems, Wireless
Communication Systems, RFID based applications etc.

Almost all microcontrollers have dedicated UART hardware built in to their architecture. The main reason
for integrating the UART hardware in to microcontrollers is that it is a serial communication and requires
only two wires for communication.

As mentioned in the introduction section, UART is a piece of hardware that acts as a bridge between the
processor and the serial communication protocol or port. The following image shows this interface briefly.
The serial communication can be anything like USB, RS – 232, etc.

The letter ‘A’ in UART stands for Asynchronous i.e. there is no clock signal to synchronize or validate the
data transmitted from transmitter and received by the receiver (Asynchronous Serial Communication).

This is in contrast to Synchronous Serial Communication, which uses a clock signal that is shared between
the transmitter and receiver in order to “Synchronize” the data between them.

If there is no clock (or any other timing signal) between the transmitter and receiver, then how does the
receiver know when to read the data?

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In UART, the transmitter and receiver must agree on timing parameters beforehand. Also, UART uses
special bits at the beginning and ending of each data word to synchronize the transmitter and receiver.

In UART based Serial Communication, the transmitter and receiver communicate in the following manner.
The UART on the sender device i.e. the transmitting UART receives parallel data from the CPU
(microprocessor or microcontroller) and converts it in to serial data.

This serial data is transmitted to the UART on the receiver device i.e. receiving UART. The receiving
UART, upon receiving the serial data, converts it back to parallel data and gives it to the CPU.

The pin on the transmitting UART, which transmits the serial data is called TX and the pin on the receiving
UART, which receives the serial data is called RX.

Since the UART involves parallel – to – serial and serial – to – parallel data conversion, shift registers are an
essential part of the UART hardware (two shift registers to be specific: Transmitter Shift Register and
Receiver Shift Register).

How UART Works

In UART Serial Communication, the data is transmitted asynchronously i.e. there is no clock or other timing
signal involved between the sender and receiver. Instead of clock signal, UART uses some special bits called
Start and Stop bits.
These bits are added to the actual data packet at the beginning and end respectively. These additional bits
allow the receiving UART to identify the actual data.

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The image above shows a typical UART connection. The transmitting UART receives data from the
controlling device through the data bus. The controlling device can be anything like a CPU of a
microprocessor or a microcontroller, memory unit like a RAM or ROM, etc. The data received by the
transmitting UART from the data bus is parallel data.

To this data, the UART adds Start, Parity and Stop bits in order to convert it into a data packet. The data
packet is then converted from parallel to serial with the help of shift register and is transmitted bit by bit
from the TX pin.

The receiving UART receives this serial data at the RX pin and detects the actual data by identifying the start
and stop bits. Parity bit is used to check the integrity of the data.

Up on separating the start, parity and stop bits from the data packet, the data is converted to parallel data with
the help of shift register. This parallel data is sent to the controller at the receiving end through a data bus.

Structure of Data Packet or Frame

The data in UART serial communication is organized in to blocks called Packets or Frames. The structure
of a typical UART Data Packet or the standard framing of the data is shown in the following image.

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Let us see about each piece of the frame.

Start Bit: Start bit is a synchronization bit that is added before the actual data. Start bit marks the
beginning of the data packet. Usually, an idle data line i.e. when the data transmission line is not
transmitting any data, it is held at a high voltage level (1).

In order to start the data transfer, the transmitting UART pulls the data line from high voltage level to low
voltage level (from 1 to 0). The receiving UART detects this change from high to low on the data line and
begins reading the actual data. Usually, there is only one start bit.

Stop Bit: The Stop Bit, as the name suggests, marks the end of the data packet. It is usually two bits long
but often only on bit is used. In order to end the transmission, the UART maintains the data line at high
voltage (1).

Parity Bit: Parity allows the receiver to check whether the received data is correct or not. Parity is a low –
level error checking system and comes in two varieties: Even Parity and Odd Parity. Parity bit is optional
and it is actually not that widely used.

Data Bits: Data bits are the actual data being transmitted from sender to receiver. The length of the data
frame can be anywhere between 5 and 9 (9 bits if parity is not used and only 8 bits if parity is used).
Usually, the LSB is the first bit of data to be transmitted (unless otherwise specified).

Rules of UART
As mentioned earlier, there is no clock signal in UART and the transmitter and receiver must agree on
some rules of serial communication for error free transfer of data. The rules include:
 Synchronization Bits (Start and Stop bits)
 Parity Bit
 Data Bits and
 Baud Rate
We have seen about synchronization bits, parity bit and data bits. Another important parameter is the Baud
Rate.
Baud Rate: The speed at which the data is transmitted is mentioned using Baud Rate. Both the transmitting
UART and Receiving UART must agree on the Baud Rate for a successful data transmission.
Baud Rate is measured in bits per second. Some of the standard baud rates are 4800 bps, 9600 bps, 19200
bps, 115200 bps etc. Out of these 9600 bps baud rate is the most commonly used one.
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Let us see an example data frame where two blocks of data i.e. 00101101 and 11010011 must be
transmitted. The format of the frame is 9600 8N1 i.e. 9600 bps with 8 bits of data, no parity and 1 stop bit.
In this example, we haven’t used the parity bit.

Advantages of UART
 Requires only two wires for full duplex data transmission (apart from the power lines).
 No need for clock or any other timing signal.
 Parity bit ensures basic error checking is integrated in to the data packet frame.
Disadvantages of UART
 Size of the data in the frame is limited.
 Speed for data transfer is less compared to parallel communication.
 Transmitter and receiver must agree to the rules of transmission and appropriate baud rate must be
selected.

8155 – A MULTIPURPOSE PROGRAMMABLE INTERFACE

This is a typical Programmable Input/output (PIO) device designed to be compatible with 8085.
It used to interface a I/O device to the microprocessor

It consists
256 bytes of Read/Write memory
Three I/O ports
Port A
Port B
Port C
A 14-bit timer

Block Diagram – 8155

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Command Register 20H

Port A 21H
Port B 22H
Port C 23H
Timer low byte 24H
Timer high byte 25H

AD0-7
These 8 lines acts as base address lines and data lines
When it is used as address lines, both ALE and CE lines must be active.

IO/M
Informs the PIO which of its facilities is being used or address logic 1 means that the I/O operation
is taking place whereas logic 0 means a memory operation is taking place.

RD and WR lines
They are used o inform the PIO whether is it is being read from or written into by the microprocessor.

Reset Line
This line is connected to the reset line of the CPU of the microprocessor so that whenever the CPU
is reset, the content of the command register is in the PIO also reset automatically.

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Time In
This line is connected from the CPU clock line to the PIO such that each clock pulse on this line
causes the value stored in the timing register to be decremented. When this value reaches zero an
appropriate signal or pulse (square saw tooth) appears on the timer out of the PIO and this pulse or
signal is used either to start or stop the timing of the system

The command Register

This is used to store a binary word which establishes the operating mode of the various facilities of
the PIO.

The Timer
This is a 4 bit down counter that counts the timer in pulses and provides either a square wave or pulse
at its time out terminal when the timer count is reached.

IEEE-488 Bus Interface

The IEEE - 488 standards defines a byte-serial, 8-bit parallel, asynchronous type instrument
interface. It is a document that describes the rules, specifications, timing relationships, physical
characteristics etc of an interfacing technique that allows digital instruments and devices to be
interconnected. It is a hardware (wires, connectors etc) that is used to implement the standard.

Sixteen signals line comprise the complete IEEE – 488 bus structure as shown below.

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Since, it is not guaranteed by the standard that instruments will send information coded in
this suggested manner, two IEEE – 488 interconnected instruments may always be able to talk toeach other,
but they may not always be able to understand each other.

MEMORY ORGANIZATION
- Memory is an integral part of any computer system.
- It is a storage device that stores programs and data that are required to perform a specific task and also
stores results of computations. The memory unit stores the binary information in the form of bits.
- The memory is divided into large number of small parts. Each part is called a cell. Each location or
cell has a unique address which varies from zero to memory size minus one. For example if computer
has 64k words, then this memory unit has64 * 210 = 65536 (or simply64 * 1024 = 65536) memory
location. The address of these locations varies from 0 to 65535.
- 1024 is the maximum number of computer memory addresses that can be referenced with ten binary
switches.
- The memory is classified into:
i. Main(or Primary) Memory
ii. Auxiliary (or Secondary) Memory
- Main memory communicates directly with the CPU
- Auxiliary (or Secondary) Memory provides the back-up storage.
- The computer memory is classified according to the key characteristics.
i. Location
 CPU
 Internal Memory (Main Memory)
 External Memory (Auxiliary Memory)
ii. Access Method
 Sequential access
 Direct Access
 Random Access

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iii. Performance
 Access time
 Cycle time
 Transfer rate
iv. Physical Type
 Semiconductor
 Magnetic surface
v. Physical Characteristic
 Volatile/Non-volatile
 Erasable/Non-erasable
vi. Capacity
 Word size
 Number of words
vii. Unit of Transfer
 Word
 Block

Memory Hierarchy
- The total memory capacity of a computer can be visualized by hierarchy of components. The memory
hierarchy system consists of all storage devices contained in a computer system from the slow Auxiliary
Memory to fast Main Memory and to smaller Cache memory. The hierarchy consists of the total
memory system of any computer.
- At the top of this hierarchy, there is CPU registers, which is accessed at full CPU speed. These are local
memory to CPU as CPU requires it. Next come cache memory, main memory, magnetic memory and
magnetic/Optical memory in that order.

Fig: Memory Hierarchy

- Another way of viewing the memory hierarchy in any computer system is illustrated below. The main
memory is at the central place as it can communicate directly with the CPU and through I/O processor
with the auxiliary devices. Cache memory is placed in between the CPU and the main memory.

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- Cache usually stores the program segments currently being executed in the CPU and temporary data
frequently asked by CPU in the present calculations.
- I/O processor manages the data transfer between auxiliary memory and main memory.

Fig: Memory connection in computer system

Main Memory
- The memory unit that communicates directly with the CPU is called main memory.
- It is relatively large and fast memory basically used to store programs and data during computer
operation.
- It is made up of Integrated chips
Characteristics of Main Memory
 These are semiconductor memories.
 Usually volatile memory.
 Data is lost in case power is switched off.
 It is the working memory of the computer.
 Faster than secondary memories.
 A computer cannot run without the primary memory.
- It is classified into two categories:
i. RAM (Random access memory)
ii. ROM (Read only memory)

1. RAM (Random access memory)

- A RAM constitutes the internal memory of the CPU for storing data, program and program result. It is
read/write memory. It is called random access memory (RAM).
- For a memory to be a random access means that any address can be accessed at any time, i.e. any
location can be accessed in random manner without going through any other memory location.
- RAM is volatile, i.e. data stored in it is lost when we switch off the computer or if there is a power
failure. Hence, a backup uninterruptible power system (UPS) is often used with computers.
- RAM is small, both in terms of its physical size and in the amount of data it can hold.
- RAM is of two main classifications:
i. Static RAM (SRAM)
ii. Dynamic RAM (DRAM)

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1.1 Static RAM (SRAM)

- The word static indicates that the memory retains its contents as long as power remains applied.
However, data is lost when the power gets down due to volatile nature.
- SRAM is made up of array of flip-flops, where each flip-flop maintains a single bit of data within a
single location (ormemory address).
- It is a type of semi-conductor memory and does not require any external refresh circuitry in order to
keep their data intact.
- SRAM chips use a matrix of 6-transistors and no capacitors. Transistors do not require power to
prevent leakage, so SRAM need not have to be refreshed on a regular basis.
- Static RAM is used as cache memory needs to be very fast and small.
- It has access time in the range of 10 t0 30 nanoseconds and hence allows for very fast access.
- It is expensive
- Two SRAM cells dominate CMOS industry
i. 6T Cell
- Here all CMOS transistors
- They better noise immunity
ii. 4T Cell
- This replaces PMOS with high resistance (~1GΩ) resistors. P-type metal-
oxide-semiconductor logic uses p-channel metal-oxide-semiconductor field
effect transistors (MOSFETs) to implement logic gates and other digital
circuits. PMOS transistors operate by creating an inversion layer in an n-type
transistor body.
- It is slightly smaller than 6T cell
- requires an extra high-resistance process layer

SRAM Operation
Consider the SRAM circuit given in Fig: CMOS SRAM cell below

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READ Operation
Consider a data read operation, shown in Figure CMOS SRAM cell, assuming that logic '0' is stored
in the cell. The transistors M2 and M5 are turned off, while the transistors M1 and M6 operate in linear
mode. Thus internal node voltages are V1 = 0 and V2 = VDD before the cell access transistors are
turned on. The active transistors at the beginning of data read operation are shown in Figure below.

After the pass transistors M3 and M4 are turned on by the row selection circuitry, the voltage CBb of
will not change any significant variation since no current flows through M4. On the other hand M1
and M3 will conduct a nonzero current and the voltage level of CB will begin to drop slightly. The
node voltage V1 will increase from its initial value of '0'V. The node voltage V1 may exceed the
threshold voltage of M2 during this process, forcing an unintended change of the stored state.
Therefore voltage must not exceed the threshold voltage of M2, so the transistor M2 remains turned
off during read phase.

WRITE Operation
Consider the write '0' operation assuming that logic '1' is stored in the SRAM cell initially. The Figure
below shows the voltage levels in the CMOS SRAM cell at the beginning of the data write operation.
The transistors M1 and M6 are turned off, while M2 and M5 are operating in the linear mode. Thus
the internal node voltage V1 = VDD and V2 = 0 before the access transistors are turned on. The column

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voltage Vb is forced to '0' by the write circuitry. Once M3 and M4 are turned on, we expect the nodal
voltage V2 to remain below the threshold voltage of M1. The voltage at node 2 would not be sufficient
to turn on M1.

1.2 Dynamic RAM (DRAM)

- DRAM, unlike SRAM, must be continually refreshed in order for it to maintain the data. This is done
by placing the memory on a refresh circuit that rewrites the data several hundred times per second.
DRAM is used for most system memory because it is cheap and small.
- All DRAMs are made up of memory cells. These cells are composed of one capacitor and one
transistor.
- It is the most common type of memory in use
- All PCs use DRAM for their main system memory instead of SRAM.
- DRAMs have much higher capacity
- They are much cheaper than SRAM
- They are slower than SRAM because of the overhead of the refresh circuitry.
- A typical 1-bit DRAM cell is shown in Fig: DRAM Cell

The CS capacitor stores the charge for the cell. Transistor M1 gives the R/W access to the cell. CB is
the capacitance of the bit line per unit length. Memory cells are etched onto a silicon wafer in an array
of columns (bit lines) and rows (word lines). The intersection of a bit line and word line constitutes
the address of the memory cell. DRAM works by sending a charge through the appropriate column
(CAS) to activate the transistor at each bit in the column. When writing, the row lines contain the state
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the capacitor should take on. When reading, the sense amplifier determines the level of charge in the
capacitor. If it is more than 50%, it reads it as "1”; otherwise it reads it as "0". The counter tracks the
refresh sequence based on which rows have been accessed in what order. The length of time necessary
to do all this is so short that it is expressed in nanoseconds (billionths of a second). e.g. a memory chip
rating of 70ns means that it takes 70 nanoseconds to completely read and recharge each cell. The
capacitor in a dynamic RAM memory cell is like a leaky bucket. Dynamic RAM has to be dynamically
refreshed all of the time or it forgets what it is holding. This refreshing takes time and slows down the
memory.

SDRAM (Synchronous DRAM) is a form of DRAM that is synchronized with the clock of the CPU’s
system bus, sometimes called the front-side bus (FSB). As an example, if the system bus operates at
167Mhz over an 8-byte (64-bit) data bus , then an SDRAM module could transfer 167 x 8 ~ 1.3GB/sec.

DDR SDRAM (Double-Data Rate SDRAM) is an optimization of SDRAM that allows data to be
transferred on both the rising edge and falling edge of a clock signal, effectively doubling the amount
of data that can be transferred in a period of time. For example a PC-3200 DDR-SDRAM module
operating at 200Mhz can transfer 200 x 8 x 2 ~ 3.2GB/sec over an 8-byte (64-bit) data bus. DDR3
continues the trend, doubling the minimum read or write unit to 8 consecutive words.

NVRAM: Non-Volatile RAM, retains its data, even when turned off. Example: Flash memory.

2. ROM (Random Access Memory)

- ROM stands for Read Only Memory. The memory from which we can only read but cannot write on
it.
- This type of memory is non-volatile. The information is stored permanently in such memories during
manufacture. A ROM, stores such instruction as are required to start computer when electricity is first
turned on, this operation is referred to as bootstrap.
- It stores BIOS. BIOS (basic input/output system) is the program a personal computer's microprocessor
uses to get the computer system started after you turn it on. The BIOS is the code that tells the processor
how to access the resources upon powering up the system.
- ROM chip are not only used in the computer but also in other electronic items like washing machine
and microwave oven.
There are different types of ROM
2.1 MROM (Masked ROM)
The very first ROMs were hard-wired devices that contained a pre-programmed set of data or
instructions. These kinds of ROMs are known as masked ROMs. It is inexpensive ROM.
2.2 PROM (Programmable Read Only Memory)
PROM is read-only memory. Data is written into a ROM at the time of manufacture but can be
modified only once by a user. The user enters the desired contents using a PROM programmer. Inside
the PROM chip there are small fuses which are burnt open during programming. It can be
programmed only once and is not erasable.
2.3 EPROM (Erasable and Programmable Read Only Memory)
The EPROM can be erased by exposing it to ultra-violet light for duration of upto 40 minutes.
Usually, an EPROM eraser achieves this function. During programming an electrical charge is
trapped in an insulated gate region. The charge is retained for more than ten years because the charge
has no leakage path. For erasing this charge, ultra-violet light is passed through a quartz crystal

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window (lid). This exposure to ultra-violet light dissipates the charge. During normal use the quartz
lid is sealed with a sticker. It allows the programmer to erase the content and reprogram it.
2.4 EEPROM (Electrically Erasable and Programmable Read Only Memory)
The EEPROM is programmed and erased electrically. It can be erased and reprogrammed about ten
thousand times. Both erasing and programming take about 4 to 10 ms (millisecond). In EEPROM,
any location can be selectively erased and programmed. EEPROMs can be erased one byte at a time,
rather than erasing the entire chip. Hence, the process of re-programming is flexible but slow.

2.4.1 FLASH memory is a cheaper form of EEPROM where updates (erase-writes) can only be
performed on blocks of memory, not on individual bytes. Flash memories are found in USB sticks,
flash cards and typically range in size from 1GB to 32GB. The number of erase/write cycles to a
block is typically several hundred thousand before the block can no longer be written.

Serial Access Memory

- Sequential access means the system must search the storage device from the beginning of the memory
address until it finds the required piece of data.
- Memory device which supports such access is called a Sequential Access Memory or Serial Access
Memory. Magnetic tape is an example of serial access memory.

Direct Access Memory

- Direct access memory or Random Access Memory, refers to conditions in which a system can go
directly to the information that the user wants.
- Memory device which supports such access is called a Direct Access Memory. Magnetic disks, optical
disks are examples of direct access memory.
Cache Memory
- Cache memory is a very high speed semiconductor memory which can speed up CPU.
- It acts as a buffer between the CPU and main memory.
- The cache memory is employed in computer systems to compensate the speed difference between the
main memory access time and processor logic.

Processor Cache Memory Main Memory

Fig: Cache placement

- It is used to hold those parts of data and program which are most frequently used by CPU. The parts
of data and programs are transferred from disk to cache memory by operating system, from where CPU
can access them.
Advantages
 Cache memory is faster than main memory.
 It consumes less access time as compared to main memory.
 It stores the program that can be executed within a short period of time.
 It stores data for temporary use.
Disadvantages
 Cache memory has limited capacity.
 It is very expensive.
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Associative memory
- When a word is written on an associative memory, no address is given. The memory is capable of
finding an empty location to store the word. When a word is to be read from an associative memory,
the content of the word or part of the word is specified. The memory locates all words which match
the specified content and marks them for reading.
- An associative memory is more expensive than a random access memory because each cell must have
storage capability as well as logic circuits for matching its contents with external arguments. Thus ,
associated memories are used in applications where the search time is very critical and must be very
short.
Virtual Memory
- Virtual Memory is a storage allocation scheme in which secondary memory can be addressed as though
it were part of main memory. The addresses a program may use to reference memory are distinguished
from the addresses the memory system uses to identify physical storage sites, and program generated
addresses are translated automatically to the corresponding machine addresses.
- This extra memory is actually called virtual memory and it is a section of a hard disk that's set up to
emulate the computer's RAM.

- The main visible advantage of this scheme is that programs can be larger than physical memory. Virtual
memory serves two purposes. First, it allows us to extend the use of physical memory by using disk.
Second, it allows us to have memory protection, because each virtual address is translated to a physical
address.

Main Memory Organization

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- Main memory can be considered to be organized as a matrix of bits.

- Each row represents a memory location, the number of bits in which is often the word size of the
architecture, although it can be a word multiple (e.g. two words) or a partial word (e.g. half word).
For simplicity we will assume that data within main memory can only be read or written a single row
(memory location) at a time
- Each row also has a natural number called its address which is used for selecting the row:

- Main-memories generally store and recall rows, which are multi-byte in length (e.g. 16-bit word = 2
bytes, 32-bit word = 4 bytes). Most architectures, however, make main memory byte-addressable
rather than word addressable. In such architectures the CPU and/or the main memory hardware is
capable of reading/writing any individual byte.
- Here is an example of a main memory with 16-bit memory locations. Note how the memory locations
(rows) have even addresses.
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Memory Modules, Memory Chips

- Physically RAM comes on small memory modules (little green printed circuit-boards about the size
of a finger).
- A typical memory module holds 512MB to 2GB. The computer’s motherboard will have slots to hold
2, 4 maybe 8 memory modules. Each memory module is itself comprised of several memory chips.
For example here are 3 ways of forming a 256x8 bit memory module.

Fig: Memory Chips

- In the first case, main memory is built with a single memory chip. In the second, we use two memory
chips, one gives us the most significant 4 bits, the other, the least significant 4 bits. In the third we use
8 memory chips, each chip gives us 1 bit - to read an 8 bit memory word, we would have to access all
8 memory chips simultaneously and concatenate the bits. On PCs, memory modules are known as
DIMMs (dual inline memory modules) and support 64-bit transfers. Previous generation of modules
were called SIMMs (single inline memory modules) which supported 32-bit data transfers.

RAM and ROM Chips

- A RAM chip is best suited for communication with the CPU if it has one or more control lines to
select the chip only when needed. It has bidirectional data bus that allows the transfer of data either

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from the memory to CPU during a read operation or from CPU to memory during a write operation.
This bidirectional bus can be constructed using three-state buffer has three possible states:
i. Logic 1
ii. Logic 0
iii. High impedance
- The high impedance states behave like an open circuit, means the output does not carry any signal.
- It leads to very high resistance and hence no current flows.

Fig: Block diagram

- The figure above shows the block diagram of a RAM chip. The capacity of memory is 128 words of
eight bits per word. This requires a 7-bit address and 8 bit bidirectional data bus.
- RD and WR are read and write inputs that specify the memory operations during read and write
respectively.
- Two chip select (CS) controls inputs are for enabling chip only when it is selected by the
microprocessor. The operation of the RAM chip will be according to the function table show below.
The unit is in operation only when CS1 = 1 and CS2 =0. The bar on top of second chip selects indicates
that the input is enabled when it is equal to 0.

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