9-3

A Wide-band CMOS Low-Noise Amplifier for TV

Tuner Applications
Youchun Liao, Zhangwen Tang* and Hao Min
ASIC & System State Key Laboratory, Fudan University
NO. 825 Zhangheng Rd., Shanghai, 201203 China

Abstract- In this paper, a wide-band CMOS low-noise ampli-

fier (LNA) is presented, in which the thermal noise of the input
MOSFET is canceled exploiting a noise-canceling technique.
The LNA is designed under input/output impedance matching
condition. And its noise figure (NF) and linearity analysis are
investigated particularly. The LNA chip is implemented in a 0.25-
,um 1P5M RF CMOS process. Measurement results show that in
50-860 MHz, the gain is about 13.4 dB, the NF is from 2.4 dB to
3.5 dB, and the input-referred third-order intercept point (IIP3)
is 3.3 dBm. The chip consumes 30 mW at 2.5-V power supply
and the core size is only 0.15mmxO.18mm.
Q
I. INTRODUCTION
The system-on-a-chip (SOC) RF TV tuners have been Fig. 1. A double-conversion TV tuner architecture.
widely researched during the last decade. As the first active
module in TV tuners, the low-noise amplifier (LNA) needs to
possess sufficient gain, low noise figure (NF), high linearity performances coincide with the simulation results, and can
and good input/output impedance matching within 50-860 meet the TV tuner applications.
MHz frequency range. The traditional inductively degenerated This paper is organized as follows. In Section II, a double-
common-source LNA [1] achieves good input impedance conversion TV tuner is introduced, and the LNA specifica-
matching and low noise figure via setting the on-chip spiral tions are given. Section III calculates the voltage gain, noise
inductor and the gate-source capacitor of input MOSFET to figure and IP3 of a noise-canceling LNA under input/output
resonate at the required frequency. However, it does not suit impedance matching, and gives an actual circuit design. Mea-
for the tuner applications because the bandwidth is restricted surement results are presented and compared in Section IV.
by the LC resonator. Finally, the conclusions are given in Section V.
The resistance feedback common-source topology with a
II. THE LNA SPECIFICATIONS FOR TV TUNER SYSTEM
noise-canceling technique [2] can achieve low noise figure
and flat gain within the required bandwidth. And the chip A double-conversion low-IF TV tuner architecture is shown
size is greatly reduced because it does not need any inductor. in Fig. 1 [3]. The RF signal received by the antenna is firstly
However, the circuit analysis and parameters calculation in filtered by a band-pass filter (BPF) to acquire 50-860 MHz TV
[2] ignored the load impedance, which is always required in signal. Then, a LNA is used to amplify the weak signal and
many practical applications and measurements. In this paper, suppress the noise contribution from the following modules.
the voltage gain and noise figure are calculated under both Finally, the all-channel signals are converted to 40 MHz IF
input and output impedance matching conditions, i.e., RS = signals (I and Q) by a double-conversion process, which can
Ri = 50 Q = RO = RL. Furthermore, the third-order intercept reject the image signal and release the design demands of the
point (IP3) calculation is proposed in this paper to give more local oscillator (LO).
in-depth comprehension for the interrelationship of all these Normally the LNA performance determines the quality
parameters. Calculation results show that the gain, NF and of a TV tuner system. Its gain determines the input signal
IP3 are all depending on the feedback resistance only, and amplitude of the following mixer and the noise restraint
benefited from a large feedback resistance, except for more capability of the tuner system. The noise figure characterizes
power dissipations. Chip measurement shows that the LNA the degeneration of the system signal-to-noise ratio (SNR)
because the noise in the LNA directly adds to the system. And
This work was supported in part by the Shanghai Science & Technology the linearity characterizes the distortion of the input signal.
Committee (No. 037062019) and the Shanghai Applied Material Funds (No.
0425), China. System simulation shows that the TV tuner in Fig. 1
* Corresponding author. Email: zwtang@fudan.edu.cn. demands good input/output 50 Q impedance matching charac-

0-7803-9735-5/06/$20.00 ©2006 IEEE 259

 Substituted with their expressions under the noise-canceling
condition, (4) can be calculated as
NF = 1+ RF + -(2Rs + RF)/4 + RL
NF
1 ++ a(RFRs)2Rs 2

v0 1+F 4R RFRF) (5)

:RL where -y is a parameter greater than 1 for submicron MOSFET.

B. Linearity Analysis
Considering only the first-order deviation of the transcon-
ductance from the square law and weakly nonlinear condition,
Fig. 2. Topology of a LNA exploiting noise-canceling technique. the drain current of M1 and M2 can be given by
lidl91,1
dl VA
= 9l, lVA + 91,2VA2 + 91,3VA3 (6)
teristics, gain greater than 12 dB, NF less than 4 dB and I td2
id2 92,1 VA + 92,2VA2 + 92,3VA3
= 921VA

greater than 3 dBm within 50-860 MHz frequency range. = n (91,1VA + 91,2VA + 91,3VA) (7)
III. PARAMETER ANALYSIS AND CIRCUIT DESIGN where gi,j means the jthorder distortion of the transcon-
ductance of MOSFET Mi (for i = 1, 2 and j = 1, 2, 3), and
A. Noise-canceling Under Input/output Impedance Matchi n = 92,j/g1,j 1 + RF/Rs. The voltage of node B can be
calculated by small-signal analysis as
The LNA exploiting a noise-canceling technique [2]
shown in Fig. 2. The primary purpose of this circuit is VB (1 -gl,1RF)VA -91,2RFVA 91,3RFVA (8)
eliminate the noise contribution of M1 channel thermal-n
tn,Mi, which is a dominating noise source. It flowing throi Then the input IP3 of the first stage is
RF and RS causes two instantaneous noise voltages at no
B and A with the same phase. Then the voltage of ni AIp3,f5
4 1 -1-l,1RF 9
91,,l3RF (9)
A is amplified by a common-source stage M2 and node 3 91,3RF
is followed by a source-follow stage M3. Consequently, Here, the first term is the non-linearity contribution of
thermal noise of M1 could be counteracted at the output the common-source topology M1 and the latter is that of
to the opposite voltage gain sign of M2 and M3. the feedback resistor RF. Normally 91,3 < 0 when M1 is
The input and output impedances can be calculated as R in saturation region, therefore the IP3 of the first stage is
1/gmi and RO = 1/9m3, respectively. And the load impeda decreased due to RF.
is RL = RS = 50 Q. Then the impedance matching condit The third-order distortion of M3 can be ignored owing to
is the over-driven voltage of M3 is quite large (VGS3 > IV).
gml= 9m3 1= RS Therefore, the voltage at the output can be written as

Considering the influence of load impedance RL, the no VO - [(ngli,Rs + gl,1RF -1)VA + g1,2(nRs + RF)VA
canceling condition is +g1,3(nRs + RF)V 3 /2 (10)
9m2 = (1 + RF/RS)/RS (2) And the input IP3 of the total circuit is

where RF is the feedback resistor. Thus, under the impedaLnce AP3,total /4 ngl,Rs + gl,1RF 1
matching and noise-canceling condition, the voltage gain frrom '\3 g1,3(nRs + RF)
node A to output is 1
4 9i,l (1 1)
Av= V0'VA -RFIRS (3) 3 91,3 91,3(RS + 2RF)

According to [4] , the noise figure (or noise factor) can be From (3), (5) and (11), it can be seen that Av, NF and IP3
represented as are only depended on the feedback resistor RF. High gain, low
noise figure and high linearity can be achieved simultaneously
NF = 1+ n,ml +Vn,RF + Vn,M2M3+Vn,RL (4)
when RF is large enough. However, a large RF needs a large
A2. 4kTRS 9m2 to meet the noise-canceling condition (2), and this would
lead much greater power consumption. The relationships of
where V2M,MI Vn,RF7 Vn,M2,M3 and V,RL are the noise contribu- Av, NF, IIP3, Idd (total current) versus the feedback resistor
tions at the output of M1, RF, M2-M3 and RL, respectively. RF are shown in Fig. 3.

260
 I-
E

0
a
-

200 300 400 (a) (b)

Feedback resistor RF (Q)
Fig. 5. Photograph of (a) Chip (b) PCB.
Fig. 3. Relationship of Av, NF, IIP, Idd vs. RF.
on.
I-AJ

lO1 -S21-

-~ 0
cn
a1)
S22
-10-
S1 1
0- -20
cn I
-30 F 812

- 4()X
-1v
0 200 400 600 800 1000
Frequency(MHz)
Fig. 6. Measured S-parameters.

of M2 can be calculated from the noise-canceling condition

(2), which is 9m2 = 9m3(l + RF/RS) = 0.18 S. However,
Fig. 4. Schematic of the designed noise-canceling LNA. for the power dissipation restriction, 9m2 is actually chosen to
be 0.08 S in this design. Consequently, the voltage gain will
decrease and the NF will deteriorate due to the deviation of
C. LNA Design the noise-canceling condition.
Figure 4 is the schematic of a noise-canceling LNA. A
PMOS M1B is exploited to increase the transconductance of IV. CHIP IMPLEMENTATION AND MEASUREMENT
input stage via a current-reuse technique. And a capacitor Ci The chip is implemented in a 0.25-,um RF CMOS process.
is used to reduce the influence of power supply fluctuating Figure 5 is the photograph of the chip and test PCB. The core
and to filter out the noise from current-mirror M4-M5. The size is only 0.15mmx0.18mm. And it draws 12 mA from a
second stage is AC-coupled to the first stage via a high-pass 2.5-V power supply. The ground Vss is connected via four
topology C2-R2. A cascode transistor M2B is used to increase bonding-wires to reduce the parasitic inductance.
the inverse isolation (S12). Its DC bias voltage is provided by The measured S-parameters are shown in Fig. 6. In the
the branch M6-M8. And C3 is used to filter out the noise from frequency range of 50 MHz-1 GHz, the S21 (voltage gain) is
this branch. M3 and M2B are deep n-well NMOS devices, about 13.4 dB with a 3-dB bandwidth of 1 MHz-1.3 GHz,
whose substrates are connected to each source to eliminate the input matching S,, is from -16 dB to -9 dB, the output
body effect. matching S22 is below -10 dB, and the inverse isolation S12
It is easy to obtain the devices parameters from the previous is less than -19 dB.
analysis. The transconductances of M1 and M3 are determined The simulated and measured NF are shown in Fig. 7. The
by the impedance matching condition (1), which is YmlA + measured NF is less than 3.5 dB from 50 MHz to 1 GHz, with
gmlB = 9m3 = 0.02 S. The feedback resistor RF is chosen to a minimum NF of 2.4 dB at 350 MHz. The NF increases at
be 400 Q considering the trade-offs between the gain, noise low frequency because of the MOSFET flick noise, and degen-
figure, linearity and power consumption. The transconductance erates at high frequency due to the input parasitic capacitances

261
 U-
z
3

92..5
3F E

co
0

Q
0
2
.5 --- -----------------------------------------3
s m l to |- -
.5. ulation
sim
measurement

0 200 400 600 800 1000 -30 -25 -20 -15 -10 -5 0 5
Frequency(MHz) Input power(dBm)

Fig. 7. Simulated and measured NF. Fig. 8. Simulated and measured IIP3.

TABLE I
SUMMARY OF MEASUREMENT RESULTS AND PERFORMANCE COMPARISON
[2] [5] [6] [7] This Work
Process 0.25,um CMOS 0.5,um CMOS 0.18,um CMOS 0.18,um CMOS 0.25,um CMOS
Frequency 150-2000 MHz 50-700 MHz 54-880 MHz 470-860 MHz 50-860 MHz
Sii (dB) -8 N/A -10 N/A 9

S21 (dB) 13.7 14.8 10-22 10 13.4

SI2(dB) -36 -41 N/A N/A -19
S22(dB) -12 N/A N/A N/A -10
NF(dB) 1.8-2.2 2.3-3.3 4.2-6 5.7 2.4-3.5
1dBCP(dBm) 9 N/A N/A N/A -6.7
lIP3(dBm) 0 -4.7 4.3-5 @1ldB 10 3.3
Power 14mA x 2.5V 3.3mA x 3V 23mA x 1.8V 2.9mA x 1.8V 12mA x 2.5V
Chip size(mm2) 0.3x0.25 1.0x 1.2 1.19x0.59 N/A 0.15x0.18

which cause the noise-canceling condition deviating. TV tuner applications.

The third-order intercept point is measured with a two-tone
ACKNOWLEDGMENT
test at 500 MHz and 502 MHz, as shown in Fig. 8. The
measured IIP3 is 3.3 dBm and varies slightly with the two- The authors would like to thank Fuxiao Li, Baowen Qiao,
tone frequencies. The input-referred IdB compression point Zhenyu Zhu, Yuhong Ye, and Haiyang Hu for their help in
(IdBCP) measures to be -6.7 dBm at 500 MHz. chip package and measurement, and thank Yan He, Lei Lu,
Zhenyu Yang, and Liming Jin for many helpful discussions.
Table I gives the measurement results compared with re-
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