STPM 10
STPM 10
STPM 10
Contents
1 Schematic diagram.......................................................................... 6
2 Pin configuration ............................................................................. 7
3 Electrical ratings ............................................................................. 9
4 Electrical characteristics .............................................................. 10
5 Terminology ................................................................................... 13
5.1 Measurement error.......................................................................... 13
5.2 ADC offset error .............................................................................. 13
5.3 Gain error ........................................................................................ 13
5.4 Power supply DC and AC rejection ................................................. 13
5.5 Conventions .................................................................................... 13
6 Typical performance characteristics ........................................... 14
7 Theory of operation ....................................................................... 17
7.1 General operation description ......................................................... 17
7.2 Analog inputs .................................................................................. 17
7.3 ΣΔ A/D converters ........................................................................... 18
7.4 Zero-crossing detection ................................................................... 19
7.5 Period and line voltage measurement ............................................. 19
7.6 Power supply................................................................................... 21
7.7 Load monitoring .............................................................................. 21
7.8 Error detection................................................................................. 22
7.9 Tamper detection module ............................................................... 22
7.9.1 Detail operational description ........................................................... 23
7.10 Phase compensation ....................................................................... 23
7.11 Clock generator ............................................................................... 24
7.11.1 RC start-up procedure ...................................................................... 24
7.12 Resetting the STPM10 .................................................................... 25
7.13 Using the STPM10 in microcontroller-based meters ....................... 25
7.14 Energy-to-frequency conversion ..................................................... 25
7.15 Status bit ......................................................................................... 26
7.16 Programming the STPM10 .............................................................. 27
7.16.1 Data records ..................................................................................... 27
7.17 Configuration bits ............................................................................ 28
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin description .............................................................................................................................. 7
Table 3: Absolute maximum ratings ........................................................................................................... 9
Table 4: Thermal data ................................................................................................................................. 9
Table 5: Absolute maximum ratings ......................................................................................................... 10
Table 6: Gain of voltage and current channels ......................................................................................... 17
Table 7: Configuration of current sensors................................................................................................. 18
Table 8: No-load detection thresholds ...................................................................................................... 22
Table 9: LED pin configuration ................................................................................................................. 26
Table 10: Status bit description ................................................................................................................ 26
Table 11: Configuration bit map................................................................................................................ 28
Table 12: Mode signal description ............................................................................................................ 31
Table 13: Working point settings .............................................................................................................. 40
Table 14: Device constants ...................................................................................................................... 40
Table 15: Resistor divider ratio ................................................................................................................. 42
Table 16: Current channel typical components ........................................................................................ 42
Table 17: TSSOP20 package mechanical data ........................................................................................ 45
Table 18: Document revision history ........................................................................................................ 46
List of figures
Figure 1: Block diagram .............................................................................................................................. 6
Figure 2: Pin connections (top view) ........................................................................................................... 7
Figure 3: Supply current vs. supply voltage, TA = 25 °C (f = 4.194 MHz, 8.192 MHz) ........................... 14
Figure 4: RC oscillator frequency vs. VCC, R = 12 kΩ, TA = 25 °C ........................................................ 14
Figure 5: RC oscillator: frequency jitter vs. temperature .......................................................................... 14
Figure 6: Analog voltage regulator: line - load regulation ......................................................................... 14
Figure 7: Digital voltage regulator: line - load regulation .......................................................................... 15
Figure 8: Voltage channel linearity at different VCC voltages .................................................................. 15
Figure 9: Power supply AC rejection vs. VCC .......................................................................................... 15
Figure 10: Power supply DC rejection vs. VCC ........................................................................................ 15
Figure 11: Error over dynamic range gain dependence ........................................................................... 16
Figure 12: Primary current channel linearity at different VCC .................................................................. 16
Figure 13: Gain response of ΔΣ A/D converters ....................................................................................... 16
Figure 14: First-order ΣΔ A/D converter ................................................................................................... 19
Figure 15: ZCR signal ............................................................................................................................... 19
Figure 16: LIN and BFR signals ................................................................................................................ 20
Figure 17: Band-gap temperature variation .............................................................................................. 21
Figure 18: Timings of tamper module - primary channel selected ........................................................... 23
Figure 19: Timings of tamper module - secondary channel selected ....................................................... 23
Figure 20: Different oscillator circuits with (a) quartz, (b) internal oscillator, (c) external source ............. 24
Figure 21: STPM10 data record map ....................................................................................................... 28
Figure 22: Timing to provide remote reset request ................................................................................... 32
Figure 23: Data record reconstruction ...................................................................................................... 33
Figure 24: Timing for data record reading ................................................................................................ 34
Figure 25: Timing for writing configuration and mode bits ........................................................................ 35
Figure 26: Active energy computation diagram ........................................................................................ 37
Figure 27: STPM10 reference schematic with one current transformer and one shunt ........................... 43
Figure 28: TSSOP20 package outline ...................................................................................................... 44
1 Schematic diagram
Figure 1: Block diagram
2 Pin configuration
Figure 2: Pin connections (top view)
Notes:
(1)A: analog, D: digital, P: power.
3 Electrical ratings
Table 3: Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC input voltage -0.3 to 6 V
IPIN Current on any pin (sink/source) ± 150 mA
Input voltage at digital pins (SCS, ZCR, WDG, SYN,
VID -0.3 to VCC + 0.3 V
SDA, SCL, LED)
VIA Input voltage at analog pins (IIP1, IIN1, IIP2, IIN2, VIP, VIN) -0.7 to 0.7 V
ESD Human body model (all pins) ±3.5 kV
TOP Operating ambient temperature -40 to 85 C
TJ Junction temperature -40 to 150 °C
TSTG Storage temperature range -55 to 150 °C
Absolute maximum ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied.
Notes:
(1)This value is based on a single-layer PCB, JEDEC standard test board.
4 Electrical characteristics
VCC = 5 V, TA = 25 °C, 100 nF to 1 μF between VDDA and VSS, 100 nF to 1 μF between VDDD
and VSS, 100 nF to 1 μF between VCC and VSS unless otherwise specified.
Table 5: Absolute maximum ratings
Symbol Parameter Test conditions Min. Typ. Max. Unit
Energy measurement accuracy
Effective Limited by digital
fBW 4 800 Hz
bandwidth filtering (-3 dB)
Accuracy of Over 1 to 1000 of
eAW 0.1 %
active power dynamic range
Accuracy of Over 1 to 1000 of
eRW 0.1 %
reactive power dynamic range
Accuracy of Over 1 to 500 of
eSW 0.1 %
apparent power dynamic range
Signal-to-noise Over the entire
SNR 52 db
ratio bandwidth
Voltage signal:
200 mVrms/50 Hz
Current signal: 10
Power supply
PSRRDC mVrms/50 Hz 0.2 %
DC rejection
fCLK= 4.194 MHz
VCC=3.3 V ±10%,
5 V±10%
Voltage signal:
200 mVrms/50 Hz
Current signal: 10
mVrms/50 Hz
Power supply
PSRRAC fCLK= 4.194 MHz 0.1 %
AC rejection
VCC = 3.3 V+0.2
Vrms1@100 Hz
VCC = 5.0 V+0.2
Vrms1@100 Hz
General section
Operating
VCC 3.165 5.5 V
supply voltage
Supply current 4 MHz, VCC = 5 V 3 4
ICC Configuration mA
registers cleared 8 MHz, VCC = 5 V 5 6
Power-on-reset
POR 2.5 V
on VCC
Analog supply
VDDA 2.85 3.00 3.15 V
voltage
Digital supply
VDDD 1.725 1.80 1.875 V
voltage
5 Terminology
5.1 Measurement error
The error associated with the energy measurement made by the STPM10 is defined as:
percentage error = [STPM10 (reading) - true energy] / true energy.
5.5 Conventions
The lowest analog and digital power supply voltage is called VSS, which represents system
ground (GND). All voltage specifications for digital input/output pins are referred to GND.
Positive currents flow into a pin. Sinking current refers to the current flowing into the pin,
and thus it is positive. Sourcing current means that the current is flowing out of the pin, so it
is negative. Timing specifications of signals treated by the digital control part are relative to
CLKOUT. This signal is provided by the 4.194 MHz nominal-frequency crystal oscillator or
from the internal RC oscillator. An external source of 4.194 MHz or 8.192 MHz can also be
used. Timing specifications of signals from the SPI interface are relative to the SCL, and
there is no direct relationship between the clock (SCL) of the SPI interface and the clock of
the DSP block. A positive logic convention is used in all equations.
Figure 5: RC oscillator: frequency jitter vs. Figure 6: Analog voltage regulator: line - load
temperature regulation
Figure 9: Power supply AC rejection vs. VCC Figure 10: Power supply DC rejection vs. VCC
7 Theory of operation
The gain register is included in the device configuration register with the address name
PST. The table below shows the gain configuration according to the register values:
If the device is used in configuration PST = 1, TMP = 1 (primary channel with CT,
secondary channel with Shunt), the shunt Ks must always be equal to one fourth
of the current transformer Ks.
Both the voltage and current channels implement an active offset correction architecture
which provides the benefit of avoiding any offset compensation. The analog voltage and
current signals are processed by the ΣΔ analog-to-digital converters, which feed the
hardwired DSP. The DSP implements an automatic digital offset cancellation that makes it
possible to avoid any manual offset calibration on the analog inputs.
If the number of pulses counted between two trailing edges of LIN is lower than 213, the
base frequency exceeds the limit (this means it is higher than f CLK/215). In this case, the
error must be repeated three consecutive times in order to set the BFR error flag. For
example, with a 4.194304 MHz oscillator frequency and MDIV bit clear (or 8.192 MHz with
MDIV set), fCLK/4 is 1.048576 MHz. If the line frequency is 30 Hz, the counted f CLK/4 pulses
between two LIN trailing edges are 34952, more than 215 (32768 pulses). The BFR low
frequency limit is as follows:
fCLK/217 = 4194304/131072 = 32 Hz
With the same clock frequency, if the line frequency is 130 Hz, the f CLK/4 pulses between
two LIN trailing edges are 8066, less than 213 (8192). The BFR high frequency limit is
then:
fCLK/215 = 4194304/32768 = 128 Hz
The BFR flag is also set if the register value of the RMS voltage drops below 64. BFR is
cleared when the register value goes above 128. The BFR, then, also gives information
about the presence of the line voltage within the meter. When the BFR error is set, the
computation of power is zero unless the FRS bit is set. In fact, the effect of the BFR bit can
be overridden by setting FRS configuration bit.
When the secondary channel is selected to be integrated by the final energy integrator, the
MUX and INH signals change according to the figure below.
Figure 19: Timings of tamper module - secondary channel selected
This means that energy of four periods from secondary channel followed by energy of four
periods from primary channel is sampled within the tamper module. From these two
samples, called B and A respectively, the criteria of tamper is calculated and the channel
with higher current is selected, resulting in a new tamper state. If four consecutive new
results of criteria happen, i.e. after elapsed 5.12 s at 50 Hz, the meter enters into tamper
state. Thus, the channel with the higher current is selected for the energy calculation. If
samples of power A and B had different signs, the tamper would be on all the time but, the
channel with bigger power would be still selected for the final integration of energy. If a
tamper status has been detected, the multiplex ratio is 56:8 if the primary channel energy is
greater than the secondary one, otherwise it is 8:56. The detected tamper condition is
stored in the BIT status bit. If BIT = 0 tamper is not detected, if BIT = 1 a tamper condition
has been detected. In standalone mode the BIT flag is also available in the SDATD pin.
The clock generator is powered from an analog supply and is responsible for two tasks.
The first is to retard the turn-on of some function blocks after POR in order to help smooth
the start of the external power supply circuitry by keeping off all major loads. The second
task of the clock generator is to provide all necessary clocks for the analog and digital
parts. During this task, the MDIV configuration bit is used to inform the device about the
nominal frequency value of CLKOUT. Two nominal frequency ranges are expected to be
from 4.000 MHz to 4.194 MHz (MDIV = 0) or from 8.000 MHz to 8.192 MHz (MDIV = 1).
Notes:
(1)These bits represent the MSB of the decimal value indicated in the description column
As indicated above, the STPM10 includes 56 CFG bits. The CFG bits are not retained
when the STPM10 supply is not available and they are cleared when a POR occurs, but
they are not cleared when a remote reset command (RRR) is sent through SPI. Normally,
some of these bits must be loaded during power-up of the application. From the
microcontroller, it could also reload the configuration and calibration values after power-on
restart.
CSEL: in normal operation, if the anti-tamper module is not activated, the STPM10 selects
channel 1 as the source of current information. For debug or calibration purposes it is
possible to select channel 2 as the source of the current channel signal when the tamper
module is disabled. This is done by setting the CSEL mode bit.
Pre-charge: this command swaps the sequence of data records read, allowing the reading
of the last four data records first, and the first four second. The reading sequence is 5, 6, 7,
8, 1, 2, 3, 4. Unlike the other mode signals, the pre-charge command is not retained inside
the STPM10, but should be sent each time before the reading of the data records.
BANK: it is used to activate RC oscillator (as indicated in Section 7.11.1: "RC start-up
procedure").
7.22.1 Interfacing the standard 3-wire SPI with the STPM10 SPI
Due to the fact that a 2-wire SPI is implemented in the STPM10, it is clear that sending any
command from a standard 3-wire SPI requires a 3-wire to 2-wire interface, which should
produce a proper signal on SDA from host signals SDI, SDO and SYN. The need for a
single-gate 3-state buffer could be avoided through an emulation of SPI just to send some
commands. On a microcontroller this can happen by performing the following steps:
At this point four signals are available. By combining (pairing) them by means of two
multiplying stages, two results are obtained
From the above results, Q1(t) is proportional to 1/ω, while Q2(t) is proportional to ω. The
correct reactive power would result from the following formula:
Equation 16:
1 1 𝑉𝐼
𝑄 = ⋅ 𝑄1 (𝑡) ⋅ ω + 𝑄2 (t) ⋅ = 𝑠𝑖𝑛𝜑
2 𝜔 2
Since the above computation needs a significant additional circuitry, the reactive power in
the STPM10 is calculated using only the Q1(t) multiplied by ω, which means:
Equation 17:
1 𝑉𝐼
𝑄3 (𝑡) = ⋅ 𝑄1 (𝑡) ⋅ ω = ⋅ (𝑠𝑖𝑛𝜑 − sin(2𝜔𝑡 + 𝜑))
2 2
The DSP performs the integration of the computed powers into energies. These integrators
are implemented as up/down counters and they can roll over. 20-bit output buses of the
counters are assigned as the most significant part of the energy data records. An
application reads the counters at least every second, to avoid missing any rollover.
The typical STPM10 parameters and constants are also known (see table below).
Table 14: Device constants
Parameter Value Tolerance
Internal reference voltage VBG 1.23 V ± 2%
Internal calculation frequency fM 223 Hz ± 50 ppm
Amplification of voltage ADC AV 4 ± 1%
Amplification of current ADC AI 8, 16, 24, 32 ± 2%
Gain of differentiator GDIF 0.6135
Gain of integrator GINT 0.815
Gain of decimation filter GDF 1.004
RMS voltage record length BV 211
RMS current record length BI 216
Constant DUD 217
As shown in the table above, analog parameters only are the object of calibration because
they introduce a certain error. Voltage ADC amplification AV is constant, while AI is chosen
according to the sensors used. The calibration algorithm first calculates the voltage divider
ratio and, as a final result, the correction parameters, called KV and KI, which applied to the
STPM10 voltage and current measures compensate the small tolerances of the analog
components that affect energy calculation. Since KV and KI calibration parameters are the
decimal representation of the corresponding configuration bytes CHV and CHP or CHS
(respectively, the voltage channel, primary current channel and secondary current channel
calibration bytes), at the end of calibration, CHV and CHP or CHS (according to the current
channel under calibration, primary or secondary, respectively) the bit values are obtained.
In the following procedure CHV, CHP and CHS are indicated as CV and CI. Through hard-
wired formulas, KV and KI tune measured values varying from 0.75 to 1, in 256 steps,
according to the value of CV and CI (from 0 to 255).
To obtain the greatest correction dynamic, initially calibrators are set in the middle of the
range, thus obtaining a calibration range of 12.5% per voltage or current channel:
8 Application design
The choice of the external components in the transduction section of the application is a
crucial point in the application design, affecting the precision and the resolution of the
whole system. Among the several considerations, a compromise has to be found between
the following needs:
1. Maximize the signal to noise ratio in the voltage channel
2. Choose the current-to-voltage conversion ratio KS and the voltage divider ratio in a way
that calibration can be achieved (please refer to AN2299)
3. Choose KS to take advantage of the whole current dynamic range according to desired
maximum current and resolution. To maximize the signal to noise ratio of the current
channel the voltage divider resistors ratio should be as close as possible to those shown in
the table below
Table 15: Resistor divider ratio
Function Component Parameter Value Unit
R to R ratio VRMS = 230 V 1650
Line voltage interface Resistor divider V/V
R to R ratio VRMS = 110 V 830
Next figure below shows a reference schematic for an application with the following
properties:
Typical values for the current sensors sensitivity, also used in the reference schematic
below, are shown in the table below.
P = 64000 imp/kWh
INOM = 5 A
IMAX. = 60 A
Table 16: Current channel typical components
Function Component Parameter Value Unit
Current shunt 0.425
Line current interface Current transformer Current-to-voltage conversion ratio KS 1.7 mV/A
Rogowsky coil 0.13
If the device is used in configuration PST = 1, TMP = 1 (primary channel with CT,
secondary channel with shunt), the shunt KS must always be equal to one fourth
of the current transformer KS.
Additional considerations on the application design, suggestions for noise and crosstalk
reduction can be found in the AN2317.
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
10 Revision history
Table 18: Document revision history
Date Revision Changes
31-Aug-2010 1 Initial release.
Modified: Table 5 on page 9, 7.9: Tamper detection
module on page 22.
25-Nov-2010 2
Added: 7.11.1: RC startup procedure on page 25 and
8: Application design on page 46.
09-Jun-2011 3 Updated Table 5.
29-Jan-2013 4 Updated Table 9.
Updated IL parameter in Table 5: "Absolute maximum
08-Feb-2017 5
ratings".
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