Silicon

https://doi.org/10.1007/s12633-021-00957-0

ORIGINAL PAPER

Improved DC Performances of Gate-all-around Si-Nanotube Tunnel

FETs Using Gate-Source Overlap
Avtar Singh 1 & Chandan Kumar Pandey 2

Received: 7 December 2020 / Accepted: 8 January 2021

# Springer Nature B.V. 2021

Abstract
In this work, a novel structure of Gate-all-Around Si-Nanotube Tunnel FET (GAA Si-NTTFET) has been proposed to improve
its electrical characteristics by overlapping a portion of source with its gate terminal. Using 3-D TCAD simulation, it has been
found that the on-state current and subthreshold swing of GAA Si-NTTFET can be significantly improved with an optimum
length of gate-source overlapping (GSO) i.e. 27-nm only, thus not limiting the scalability of source region. Furthermore, GSO has
also caused a reduction in the turn-on voltage of GAA Si-NTTFET which may help to scaling the supply voltages. Moreover, due
to reduction in the lateral electric field at source-channel interface caused by GSO, the off-state current has been observed to be
smaller as compared to the conventional GAA Si-NTTFET which eventually reduces the stand-by power dissipation.
Additionally, the ambipolar current has also been found to be reduced in the proposed structure which makes it more suitable
for its application in the digital circuits.

Keywords Silicon nano tube tunnel FET . Gate on source overlap . Line tunnelling . Tunnelling barrier width

1 Introduction Impact ionization MOS (IIMOS) although exhibits ultra-

narrower SS, but not suitable for low power application be-
For higher integration capability and better drive capability, cause of their large breakdown voltage [6]. Many researchers
the CMOS technology node has been scaled down incessant- worldwide proposed several better architectures for reducing
ly. While decreasing the channel length up to nanometer’s the breakdown voltage of IIMOS. But due to hot carrier injec-
regime, some serious problems come into the existence like tions, reliability issues are the matter of major concern [7].
increment in the leakage current, short channel effects and Negative capacitance FET (NCFET) was also demonstrated by
limitation on minimum subthreshold swing (SS) to 60 mV/ incorporating the ferroelectric material within the transistor for
decade [1–3].However the physical size of the devices are better SS. But the hysteresis found in the characteristics of
reduced very fast but the supply voltage for scaled devices NCFET made it unsuitable for the digital circuits’ applications [8].
could not get scaled at the equivalent pace because of the By comparing all of the current devices, Tunnel field effect
inability to reduce the SS below the Boltzmann limit transistor (TFET) gained a lot of popularity due to the
(60 mV/dec) at room temperature. To overcome this narrower sub-threshold swing (less than 60 mV/decade) as
Boltzmann tyranny, new devices with different conduction compared to the MOSFET counterpart [8–10]. Generally cur-
mechanism like band to band tunneling (BTBT) and impact rent conduction in the conventional TFET is mainly based on
ionization have been suggested [4, 5]. the point tunneling mechanism occurred at source-channel
interface in which the electric field induced by gate voltage
is perpendicular to the tunneling direction, due to which the
* Avtar Singh tunneling of charge carriers takes place in a minimal area near
avtar.ju@gmail.com the source channel junction. In this tunneling the direction of
the tunneling is with along the channel. If the tunneling direc-
1
Department of Electronics and Communication Engineering, Adama tion is same as the gate electric field then it is termed as the
Science and Technology University, Adama, Ethiopia line tunneling. In this mechanism, the tunneling distance is
2
School of Electronics Engineering, VIT-AP University, comparatively less as compared to point tunneling due to
Amravati, Andhra Pradesh, India which the ON current increases in this tunneling method [11].

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 Silicon

It is observed that when the gate length of Tunnel FETs is

reduced then the controllability around the channel by gate
terminal is gradually unfastened because the leakage of charge
sharing increases at drain/source junction [12, 13, 14, 15]. For
better optimized results, now a day’s researchers across the
world are more centric on the Three-dimensional structures,
such as FINFET, and GAA in which the electrostatic control-
lability of gate over the channel is more as compared to 2D
structures. Among all such structures, the gate all around
structure (GAA) offers comparatively less Off-current be-
cause the gate surrounds the channel from all the direction
[16].
Recently, some group of researchers have studied about the
(a)
impact of gate-on-source overlapping on various electrical
characteristics of Tunnel FETs [11, 17, 18]. Homogeneous
gate-on-source TFET was proposed by Kaoet al.[17]and it
was observed that a suitable pocket thickness of GoSo
TFETs is 5-nm. In their work, they obtained ION/IOFF ratio
to be 105, and found a subthreshold swing of 100 mV/decade.
Further, Dubey et.al, [18] reported a hetero-junction GoSo
Tunnel FET and obtained ION/IOFF ratio of 3.72 × 107
and 14.07 mV/decade as SS. Ashita et al. utilized the
line tunneling mechanism and proposed a Go-SCOP
TFET which reported the ION/IOFF ratio of 109approxi-
mately and SS of 48 mV/dec. In their work, they also (b)
observed 0.4μS/μm as trans-conductance (g m )and
1.19 GHz as the cutoff frequency value [11].
In this paper we used the advance version of GAA structure
which is silicon nanotube-based FET. This is the tubular de- Fig. 1 a 3D structure b vertical cross-section of GSO Si-NTTFET
vice in which gate controls the channel from both ways inside
the channel as well as outside the channel due to which the device parameters of the device are taken as: diameter of the
leakage current is observed to be minimal [19–23, 24]. tube is 10 nm and the drain voltage of the device is 0.7 V.
Further, we proposed the gate-source overlapped structure 4.7 eV is taken as the gate work function for both the gates.
termed as gate-Source overlapped silicon nanotube FET struc- The source is p-type doped (1x1019cm−3) and drain is N-type
ture (GSO-Si-NTTFET). This is the novel device structure of doped (5x1018cm−3). The channel is kept at intrinsic value.
GAA NTTFET and is reported for the first time. In this work, While simulation, abrupt doping profile is taken into consid-
we performed the electrical characterization of the GSO-Si- eration. Gate dielectric (SiO2) film thickness is 1 nm. The
NTTFET. This structure shows the better results compared to parameters used for the GSO-SiNTTFET simulation are listed
the conventional Silicon nanotube tunnel FET. in Table 1. GSO-SiNTTFET employs gate-over channel-
In Section 2, the device description and simulation source interface and beyond that. The gate electrode and the
methods and models are discussed. Next, Section-3 discusses
the result discussion, and finally, Section-4 presents the con- Table 1 Device Specifications
clusion of this work.
Parameter Value

Channel Length (Lg) 45 nm

2 Device Description and Simulation GSO overlap(Lov) 27 nm
Tube diameter (Outer) 10 nm
Figure 1a shows the 3D structure of gate-source overlapped Gate Work function 4.7 eV
silicon nanotube tunnel FET (GSO-Si-NTFET) and Fig. 1b Gate oxide thickness 1 nm
shows the vertical cross-section of the same structure. This Channel region doping 1017 cm−3
is the tubular structure made up with silicon. There are two Source region doping 1x1019cm−3 (P type)
gates for controlling the flow of charge carriers i.e., inside the Drain region Doping 5x1018cm−3 (N type)
tube and outside the tube. Each gate is of 45 nm length. The

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Silicon

gate dielectric are overlapped over the source. The perfor- the conventional SiNTTFET by varying the overlapped length
mance of the conventional tunnel FET is compared with between gate and source. The parameters of the device are
GSO structures of gate source overlap length (Lov) lengths taken as Tsi(silicon body thickens) = 5 nm,
of 7 nm,27 nm and 52 nm.
The 3D simulations are executed in the SILVACO ATLAS
3D device simulator. SRH, CVT and Lombardi mobility sim-
ulation model are weighed to measure the changes in mobility.
For quantum effects local density model is activated. For the
numerical iterations the Newton method is used. To capture
the vertical and lateral tunneling effects in the GSO-
SiNTTFET, nonlocal to local, KANE model is adopted [25].
Kane model can be written as:
!
A:F r E1:5
g
GBTBT ¼ 0:5 exp −B
Eg F:

Where F is the Electric field and Eg is the dependent

bandgap. The constant A, B and r are considered as 3.5 ×
1021 eVm1/2/cm−s − V2, 2.25x107V/cm − eV3/2 and 2.5, re-
spectively. The step by step fabrication of the silicon nanotube
FET is listed in the patent filed by the Tekelib et al. [26].For the
mandatory affirmation of the simulated transfer characteristics,
TCAD simulated device structure is equated with the experimen-
tal outcomes of Silicon Nanotube FET proclaimed in [20]. We
calibrated the Id-Vg characteristics as shown in Fig. 2 as a cor-
rective measure to imitate the experimental results of [20].

3 Results and Discussion

In this section, the impact of GSO on various DC performance

parameters of Si-NTTFET has been demonstrated in details.
To optimize the length of GSO, the performance parameters
of our proposed structure have been compared with those of

Fig. 3 Comparison of (a) transfer characteristics and (b) energy band

Fig. 2 Experimental [20](symbols) and simulated (solid lines) Id-Vg diagram of the proposed structure with conventional GAA NTTFET (c)
characteristics for Silicon Nano tube FET at linear(Vds = 0.05 V) and Comparison of lateral electric field of the proposed structure with
saturation (Vds = 1 V) conventional GAA NTFET

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 Silicon

3.1 Impact of GSO on ON-State Behavior figure that the tunneling barrier width at source-channel (S-
C) interface is thinner in the proposed device than that of the
The GSO used in the proposed device has been found reduc- conventional SiNTTFET.
ing the tunneling barrier width at source-channel (S-C) inter- It mainly happens due to the lowering of energy band of source
face which eventually causes a significant increment into the underneath gate-source overlapped region, as shown in Fig. 3b.
on-state current. The cutline has been set at the center of the proposed device to
Figure 3a compares the transfer characteristics of the proposed plot the energy band profile in the lateral direction. The reduction
GSO-SiNTTFET with that of conventional SiNTTFET. It can be in tunneling barrier width at S-C interface stimulate as greater
observed from the plot that the on-state current(ION) is signifi- number of electrons tunneling through the input interface, thus
cantly increased when length of GSO is increased. The optimum increasing the on-state current in GSO-SiNTTFET.
value of GSO is obtained to be 27nm which will be discussed The enhancement in BTBT generation rate of charge carriers
further in this section. The impact of GSO on IONcan be further is mainly due to the fact that the overlapping of source with gate
analyzed with the help of lateral energy band diagram, electric induces an electric field in the vertical direction which triggers
field in the lateral and vertical directions, band-to-band tunneling the line tunneling of charge carriers and consequently, the on-
(BTBT) rate of charge carriers in source region and at S-C inter- state current is increased due to enhancement in the number of
face of GSO-SiNTTFET biased at (Vgs = 1.2V). charge carriers tunneling through S-C interface.
Fig.3b compares the lateral energy band diagram of the Figure 3c shows the vertical electric field profile in
proposed GSO-SiNTTFET with that of the conventional SiNTTFET with and without GSO for the cutline taken at 1-
SiNTTFET at ON-state (Vgs = 1.2V). It is evident from the nm from S-C interface in the vertical direction. It is clearly

Fig. 4 a lateral electric field in GSO-SiNTTFET for three different values Fig. 5 a Energy band profile of the proposed structure for different values
of Lov at OFF-state. b lateral energy band in GSO-SiNTTFET for three of Lov at ambipolar state. b Lateral electric field in the proposed structure
different values of Lov at OFF-state for different values of Lov at ambipolar state

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Silicon

evident from the plot that the strength of vertical electric field in movement of charge carriers between source and drain termi-
the source region is higher in the proposed device as compared nals when applied gate bias is 0V.
with that of conventional SiNTTFET which is found enhancing Fig. 4a compares the strength of lateral electric field in
the BTBT generation rate of charge carriers. Unlike gate-on- GSO-SiNTTFET for three different values of Lovat Vgs =
source-only (GoSo) TFET in which tunneling happens only in 0V. It is clearly evident from the plot that the minimum value
vertical direction, BTBT occurs in both lateral and vertical direc- of lateral electric field is attained for Lov = 27nm at both
tion for GSO configuration adopted for our proposed device, and source-channel and channel-drain (C-D) interfaces while it is
as a result of that an acceptable on-state current is achieved at found to be maximum for Lov = 0nm i.e., SiNTTFET without
comparatively smaller gate bias than that of the GoSo configu- GSO. The reduced strength of lateral electric field eventually
ration. The impact of vertical electric field induced by GSO in the reduces the rate of charge carriers moving between source and
proposed device can be further analyzed by plotting the thinning drain regions, thus minimizing the subthreshold leakage cur-
rate of tunneling barrier width at S-C interface with varying Lov rent in the proposed device.
which has been discussed further in this section as shown in For more comprehensive analysis, the lateral energy band
Fig. 6c. It can be observed from the figure that the tunneling profile in the proposed device has been plotted for Lovranging
barrier width attains a minimum value for Lov = 27nm and is from 0 to 27nm at gate bias of 0V. It can be observed from
not shown to be significantly changed when Lov is increased Fig. 4b that the barrier width at S-C interface happens to be
beyond this optimum value of 12nm. wider for the optimum value of Lovi.e., 27 nm, which ultimate-
ly decreased the movement of charge carriers during off-state
3.2 Impact of GSO on OFF-State and Ambipolar of the device operation. In case of the zero-gate bias (i.e.off-
Behavior state), this broadening of the barrier width mainly happens due
to elevation of the energy band in source region caused by
Another advantage of the proposed GSO-SiNTTFET over the overlapping with gate terminal, as shown in Fig. 4b.At Vgs =
conventional SiNTTFET is that the subthreshold leakage cur- 0V, the energy band structure in source of the proposed device
rent is found to be smaller in SiNTTFET when a portion of is elevated due to the work-function difference between gate
source is overlapped with gate, and it can be observed from metal and semiconductor material used for source.
Fig. 3a. A smaller value of off-state current in GSO- Just like the low on-state current compared to MOSFETs,
SiNTTFETis mainly attributed due to the reduction inthe another major roadblock for Tunnel FET devices is the

Fig. 6 a Transfer characteristics

of GSO Si-NTTFET for varying
Lov. b Lateral energy band profile
in GSO Si-NTTFET for varying
Lov at ON-state. c-d Barrier width
and vertical electric field in GSO
Si-NTTFET for varying Lov at
ON-state

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 Silicon

ambipolar conduction which raises the concern while going for significantly reduced with increasing Lov and attains a mini-
application in digital circuits.It can be clearly seen from Fig. 3a mum value for an optimum value of Lov = 27nm.
that the ambipolar current (Iamb) is less in the proposed device as Further analysis of the impact of varying Lov on tunneling
compared to the conventional Si-NTTFET at gate bias of −0.5V. barrier width in GSO-SiNTTFET can be done with the help of
It mainly happens because of the energy band raising in vertical electric fields in the source region and S-C interface
source region of the proposed device (as shown in Fig. 5a during on-state (Vgs = 1.2V). The lateral electric field in the
caused by GSO which is due to the gate biasing in source proposed device is shown in Fig. 6d with Lov ranging from 0
region as well. As a consequence of this, the overlapping to 52nm. The plot clearly suggests that strength of the electric
between valance band of the source and conduction band of field increases in overlapped source region and at S-C
the channel gets reduced, thus decreasing the BTBT generate
rate of charge carriers at S-C interface which eventually re-
duces the ambipolar current, as shown in Fig. 3a. To investi-
gate the impact of GSO onIamb in more details, the lateral
electric field profile has been compared for Si-NTTFET with
and without GSO. It can be observed from Fig. 5b that
strength of the lateral electric field is less under the influence
of overlapping between gate and source which in turn reduces
the BTBT generation rate of charge carriers.
The reduction in electric field intensity is mainly attributed
due to the widening of tunneling barrier width at S-C inter-
face, as observed in Fig. 5a.

3.3 Device Optimization

To achieve the improved device performances, such as

high ION, steep SS, and low IOFF, the length of over-
lapping between gate and source (Lov) has been opti-
mized in this section.
Figure 6a shows a family of curves representing ID −
Vgcharacteristics of the proposed GSO-SiNTTFET for Lov
varying from0 to 52nm. The value of ION is found to be in-
creasing with an increment in Lovand no significant change
in ION is noticed forLov > 27nm. The enhancement in ION is
mainly due to thinning of the barrier width at S-C interface
which becomes nearly independent from SGO when Lov is
increased beyond27nm. ION becomes saturated at 2.4 ×
10−5A/μm (at Vgs = 1.2V) for Lov = 27nmbecause there is no
interaction of the overlapping edge with S-C interface. The
saturation of ION be further realized from lateral energy band
profile in the proposed device with varyingLov, as shown in
Fig. 6b. When gate terminal is biased at positive voltage,
energy band in source region is pulled down due to the poten-
tial drop across gate-source interface and this lowering of the
energy band in overlapped-source region is found extending
further in the source with increasing length of GSO (Lov). It is
clearly evident from the figure that the tunneling barrier width
at S-C interface is reduced with lowering of energy band in
source region and is not being affected with this band lower-
ing for Lov > 27nm. The same has been shown in Fig. 6c in
which the impact of varying Lov on tunneling barrier width at Fig. 7 a On-state and off-state current in GSO Si-NTTFT for varying Lov.
S-C interface has been investigated for gate bias of 1.2V.It can b Current switching ration in the proposed GSO Si-NTTFT for different
be clearly observed from the figure that the barrier width is Lov c Subthreshold slope of GSO Si-NTTFET for varying Lov

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Silicon

interface as well due to lowering of energy band underneath Funding No funding required.
overlapped surface caused by gate voltage. When Lov is in-
Data Availability This is the simulated work and the old papers on the
creased beyond27nm, it can be observed that there is no sig-
same topic is only the required materials and the simulation performed on
nificant increment in the magnitude at S-C interface. the TAD tool.
Moreover,Fig. 7a compares the magnitude of off-state cur-
rent along with on-state current for various values ofLov. It can Compliance with Ethical Standards
be realized from the plot that off-state current is significantly
reduced with increasing length of overlapping and does not This is the new work and submitted to any journal first time. The manu-
change further when Lov is increased beyond27nm. script is prapred as the ethical standard.
The plot suggests that even on-state current is not signifi-
cantly changed for Lov > 27nm so it can be considered as an Conflict of Interest This is the novel work. There is no anytype of
conflict ogf interest.
optimum value for the same. Furthermore, the current
switching ratio(ION/IOFF) for varying Lovis shown in Fig. Consent to Participate Yes
7bfrom which it can be seen that ION/IOFFincreasing with an
increment in overlapping length nearly becomes saturated Consent for Publication Yes
when Lov is increased up to 27nm.
Next, the impact of overlapping length on SS is investigat-
ed and shown in Fig. 7c. It can be interpreted from this graph References
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