Received February 28, 2019, accepted March 21, 2019, date of publication March 28, 2019, date of current

version April 13, 2019.

Digital Object Identifier 10.1109/ACCESS.2019.2907976

A Carry Lookahead Adder Based on Hybrid

CMOS-Memristor Logic Circuit
GONGZHI LIU, LIJING ZHENG, GUANGYI WANG , YIRAN SHEN , AND YAN LIANG
Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou 310018, China
Corresponding author: Guangyi Wang (wanggyi@163.com)
This work was supported by the National Natural Science Foundation of China under Grant 61771176 and Grant 61801154.

ABSTRACT Memristor-based digital logic circuits open new pathways for exploring advanced com-
puting architectures, which provide a promising alternative to conventional IC technology. In several
memristor-based logic design methods, the memristor ratioed logic (MRL) is compatible with traditional
CMOS technology. Two kinds of carry-lookahead adders (CLA) based on the hybrid CMOS-memristor
structure are proposed, within which one is based on MRL logic, and the other is an improved one that is
implemented by MRL universal gate (MRLUG). The proposed CLAs are verified by theoretical analyses
and simulations, showing that the proposed design method requires fewer memristors and CMOSs than the
IMP-based or CMOS-based CLAs, which means smaller circuit size and lower power consumption.

INDEX TERMS Memristor, logic circuit, CLA.

I. INTRODUCTION new pathway for exploring advanced computing architectures

According to Moore’s law, it is anticipated that the number of as a promising alternative to traditional logic circuits.
transistors on a chip doubles every 2 years [1]. However, tra- Thus, several memristor-based logical circuit design meth-
ditional CMOS technology is facing a variety of challenges, ods have been put forward. In 2010, the paper published by
in which limitations of the CMOS technology require look- HP laboratories first mentioned that a simple circuit con-
ing for other technologies to overcome these limitations [2]. sisting of memristors and resistors can realize the material
The memristor, a new nanoscale memory component, is a implication logic operation (IMP), and then combining with
powerful competitor for the next generation of computational the FALSE operation to make up a computationally complete
framework [3]. logic unit and realize the operation of any Boolean logic
A memristor is a 2-terminal circuit element defined by function [3]. Fig. 1(a) is a basic schematic of IMP operation,
the relationship between flux ϕ and charge q [4]. In 2008, comprised by two memristors P and Q, and a load resistor
the first practical memristor implementation was announced Rg . Fig. 1(b) is the truth table of IMP operation. The material
by the research group of Stanley Williams at the HP Labs, implication is considered to be a truth function in logic, and
which aroused intense interests in academia and industry the p IMP q can be expressed as ‘‘p → q’’ in a logical
immediately [5]. The memristor is physically a two-terminal expression. However, the main drawback of the IMP logic
device, whose main features are non-volatility and nanoscale lies in performing lengthy sequences. For example, it takes
size, making the memristor capable of computing and stor- 3 steps to implement the logic NAND gate. In addition,
ing simultaneously. The unique characteristics of memristor the memristanc values are used to represent the logic states.
make it have good application prospects in analog cir- Therefore, additional peripheral circuits are needed for read-
cuits [6], neural networks [7], [8], logic circuits [9], [10], and ing and writing operations, which increases the complexity of
memories [11]. the circuit design.
Memristors provide a non-conventional computation In view of the complexity of the memristor-based IMP
framework which combines logic operation and storage in logic, a design method similar to the IMP logic circuit is
the memory itself [12]. Memristor-based logic circuits open a proposed, that is, the memristor-aided logic (MAGIC) [13],
which also relies on a sequencer to realize the logic function.
Fig. 2 is an AND gate based on MAGIC method. Being
The associate editor coordinating the review of this manuscript and
consistent with the IMP logic circuit, MAGIC’s logic states
approving it for publication was Ho Ching Iu. are also represented by the memristances, where the high

2169-3536 2019 IEEE. Translations and content mining are permitted for academic research only.
VOLUME 7, 2019 Personal use is also permitted, but republication/redistribution requires IEEE permission. 43691
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
 G. Liu et al.: CLA Based on Hybrid CMOS-Memristor Logic Circuit

CLA and other CLAs has been conducted and discussed.

As for the organization of this paper, Section II introduces
the model of the memristor. Section III is the carry-lookahead
adder which is composed of MRL logic. Section IV is the
improved carry-lookahead adder. Section V is the conclusion.

II. THE MEMRISTOR MODEL

Operations of the memristor-based logic circuits rely on
the switching dynamics of threshold-type voltage-controlled
bipolar memristor. The i-v relation of the memristor model is
FIGURE 1. Circuit implementation of the IMP operation and its truth given by [19]:
table.
(
a1 x (t) sin (bv (t)) , v (t) ≥ 0
i (t) = (1)
a2 x (t) sin (bv (t)) , v (t) < 0

where v(t) and i(t) are the voltage and current across the mem-
ristor; x ∈[0,1]is the internal state variable of the memristor;
a1 , a2 and b are constants greater than zero. The internal state
variable satisfies:
dx
FIGURE 2. Logic AND gate realization using MAGIC. = g(v)f (x) (2)
dt
where g(v) gives different thresholds for memristor, and it is
resistance ROFF and low resistance RON are considered as given by
logical ‘‘0’’ and logical ‘‘1’’, respectively. The input and 
v(t)
Ap (e − e ),
 Vp v(t) > Vp
output of the logic gate are the memristances. Compared
with the method of IMP logic circuit, the MAGIC circuit is g(v) = −An (e −v(t) − eVn ), v(t) < Vn (3)

0, −Vn ≤ v(t) ≤ Vp

simpler and more stable. Different Boolean logic operations
can be realized through the series-parallel arrangement of the
When the internal variable respectively reaches the bound-
memristor.
aries xp and xn of the memristor, there will be a boundary
MAGIC-based logic gate includes two sequential stages.
effect described in [20]. In order to make the memristor
The first stage is to initialize the output memristor to the
switch smoothly at the boundaries, the function f (x) of Eq. (2)
specified memristance. The second stage is to apply voltage
is given by
V0 at the gateway. If the voltage (or current) across the
output memristor exceeds the threshold voltage (or current),
(
e−αp (x−xp ) ωp (x, xp ), x ≥ xp
the logic state of the output memristor will change, otherwise f (x) = (4)
1, x < xp
the state of the memristor will remain unchanged. Thereby (
the logic operation can be obtained correctly. e−αn (x+xn −1) ωn (x, xn ), x ≤ 1 − xn
Whether it is IMP logic or MAGIC, the logic gates require f (x) = (5)
1, x > 1 − xn
a series of sequences to operate the logic function, and the
state variables are all defined by the memristanc values. They where ωp and ωn are two window functions, which are
are incompatible with the traditional CMOS-based circuits, defined as
and the extra conversion circuits are needed for converting xp − x
the memristances to the voltage levels. This implies that the ωp (x, xp ) = +1 (6)
1 − xp
complexity of the circuits is increased. x
The memristor ratioed logic (MRL) gate design method ωn (x, xn ) = (7)
1 − xn
suggests that any logic function can be achieved by using
memristor and traditional CMOS buffers [14]. The logic Fig. 3 is the i-v characteristic curve of the memristor.
states are voltage levels, which are compatible with current The memristor contains different threshold voltages, and the
CMOS technologies. There are several computational build- voltages of different polarities correspond to the different
ing blocks have been proposed in the last few years, such as threshold voltages. When the applied voltage exceeds the
multiplier [15], ripple carry adder [16], full adder [17] and positive threshold voltage, the memristance will transfer from
oscillator [18]. the HRS (High Resistance State) to the LRS (Low Resistance
This paper proposes a carry-lookahead adder (CLA) based State). Similarly, when the applied voltage exceeds the neg-
on MRL, and then an improved carry-lookahead adder is put ative threshold voltage, it will change the memristance from
forward. A performance comparison between the improved the LRS to the HRS.

43692 VOLUME 7, 2019

G. Liu et al.: CLA Based on Hybrid CMOS-Memristor Logic Circuit

III. MRL LOGIC TABLE 1. Truth table of AND gate.

From the hysteretic current-voltage loop shown in Fig. 3,
it can be seen that the memristance varies according to the
direction of current. Fig. 4 (a) is the symbol of the memristor,
in which the black side represents the negative polarity of the
memristor. When the current flows from A to B, the mem-
ristance increases to ROFF ; while the current flows from B
to A, the memristance decreases to RON [14]. By using the
switching property of the memristor, the AND gate and OR
gate can be built, as shown in Fig. 4(b) and Fig. 4(c) [14]. Fig. 5 shows four different cases for the input of the AND
gate. Input voltages are V1 and V2 , Vcc represents logic
‘‘1’’, and 0 V represents logic ‘‘0’’. For Fig. 5 (a) and (b),
V1 = V2 = 1 and V1 = V2 = 0, and the circuits have no
current passing from MR1 to MR2 , so the outputs remain the
same as the inputs. For Fig. 5(a), the input voltages are Vcc
(logic ‘‘1’’), and then the output voltage is Vcc (logic ‘‘1’’) as
well; for Fig. 5(b), the input voltages are ground (logic ‘‘0’’),
and then the output voltage is ground (logic ‘‘0’’) as well.

FIGURE 3. The i-v characteristic curve of the memristor.

FIGURE 4. Memristor symbol and logic AND and OR gates.

Taking the AND logic gate as an example, the computing

process is analyzed. The logic AND gate is composed of FIGURE 5. MRL-based logic AND computation.
two memristors in series. The input terminal is connected to
the positive polarity terminal of the two memristors, and the In Fig. 5 (c), V1 = 1 and V2 = 0, and the circuit
output terminal is the common node of the memristor. The has a current passing from MR1 to MR2 , which makes the
output voltage of the AND gate is determined by the voltage resistance of memristor MR1 increase to ROFF , and that of
divider of the two memristive devices. the memristor MR2 decrease to RON . Assume that ROFF >>
The basic memristor-based logic AND gate, as shown RON , the output voltage is evaluated by the principle of
in Fig. 4 (b), consists of two memristors connected in series voltage divider:
with opposite polarity, of which the output node is the com-
RON
mon node of the two memristors. The truth table of AND gate Vout = Vcc ≈ 0 (8)
is shown as Table 1. Logic OR gate is similar to the AND ROFF + RON
gate, as shown in Fig. 4 (c), which consists of two memristors In Fig. 5 (d), V1 = 0 and V2 = 1, and the circuit has a cur-
connected in series with identical polarity. rent passing from MR2 to MR1 , which makes the resistance of

VOLUME 7, 2019 43693

 G. Liu et al.: CLA Based on Hybrid CMOS-Memristor Logic Circuit

memristor MR2 increase to ROFF , and that of memristor MR1

decrease to RON . Assume that ROFF >> RON , the output
voltage is evaluated by the principle of voltage divider:
RON
Vout = Vcc ≈ 0 (9)
ROFF + RON
Combined with traditional CMOS buffers, other logic
gate circuits can be obtained. For example, a combination
of AND (OR) gate and a CMOS buffer can construct a
NAND (NOR) logic gate. Other more complex combina-
tional logic circuits, such as the commonly used XOR gates,
can also be built. Unlike the implication logic circuits and
MAGIC logic circuits, the logic states of the MRL are the
voltage levels, which is the same as the traditional logic cir-
cuits. Hence, it has a good compatibility with the traditional
logic circuits.

IV. THE CARRY LOOK-AHEAD ADDER BASED ON MRL

In order to increase the operation speed of the multi-bit adder
and reduce the transmission delays caused by the propagation
of carry signal, a traditional carry adder is proposed [21].
In this paper, a 4-bit carry-lookahead adder (CLA) based
on MRL is presented, and its circuit structure is shown
in Fig. 6. The carry-lookahead adder defines two functions,
i.e., the carry generate function Gi and the carry propagate
function Pi :
(
Gi = Ai Bi
(10)
Pi = (Ai + Bi )
Thus, the carry output function of the carry-lookahead
adder is:
Co = Ai Bi + (Ai + Bi )CIi = Gi + Pi CIi (11)
FIGURE 6. The carry-lookahead adder based on MRL logic.
According to the truth table of the 4-bit adder, the output
sum function of the i-bit full adder can be deduced as:
Si = Ai ⊕ Bi ⊕ Ci (12)
According to the carry output function and the output
sum function, the MRL gate circuit is used to build a
carry-lookahead adder. The XOR gate in the circuit is a
combinational logic gate consisting of AND gate and OR
gate. In addition, the multiple input AND or OR gates are
the extension of 2 input AND or OR gates.

V. IMPROVED CARRY-LOOKAHEAD ADDER

By using a suitable combination of MRL gates and a CMOS FIGURE 7. The structure diagram of the ULG and Symbol of the ULG.

inverter, a new hybrid CMOS-memristor logic gate circuit,

i.e., a universal logic gate (ULG) is presented in [9].
The circuit structure and its simplified circuit symbol are the same time: AND, OR and XOR. By comparison, one
shown in Fig. 7. The main feature of this structure is that the MRL-based XOR gate needs 6 memristors, while the number
output of logic AND gate is connected to the input of the of memristors used in the improved CLA is reduced by two.
inverter, the output of logic OR gate is connected to the source Thereby the area and power consumption of the integrated
of the PMOS, and the output of the inverter happens to form circuit design is reduced.
an XOR gate. As shown in Fig. 6, the dotted line block X of the
The universal logic gate (ULG) uses only 4 memristors MRL-based CLA which contains one AND gate, one OR
and 2 CMOSFET transistors to achieve 3 logic functions at gate, and one XOR gate, can be replaced by only one ULG.

43694 VOLUME 7, 2019

G. Liu et al.: CLA Based on Hybrid CMOS-Memristor Logic Circuit

FIGURE 8. Simulation results of ULG.

FIGURE 10. The simulation results of 4-bit carry-lookahead adder.

Using the ULGstructure to redesign the carry-lookahead

adder can greatly reduce the number of memristors, simpli-
fying the complexity of the circuit design, and thus reduce the
power consumption of the circuit.
The performance comparisons of the improved CLA,
the MRL-based CLA and the IMP-based CLA reported
in [22] are shown in Table 2.

TABLE 2. Comparisons of the proposed CLA with the one reported in [22].

The IMP-based CLA takes memristance values as logic

state variables to represent the inputs and outputs, in which
the high memresistance ROFF and low memresistance RON
are considered as logic ‘‘0’’ and ‘‘1’’ respectively, and the
FIGURE 9. Improved carry-lookahead adder.
final results of the operation remain in the memristors. Unlike
the MRL-based CLA proposed in this paper, the IMP-based
CLA requires an additional reading/writing circuit to read
Furthermore, the dotted line block Y of the CLA can also be the results stored in the memristors, and needs to initialize
replaced by an ULG. Hence, an improved MRL-based CLA the memristor to ensure logic operation. The additional read-
circuit with ULGs is obtained, as shown in Fig. 9. ing/writing circuit and initialization circuit are made up of
The improved carry-lookahead adder is simulated by memristors, CMOSs and other circuit elements, so more chip
LTSPICE. The memristor used in the circuit is based on a area and more power consumption of the IMP-based logic
memristor model proposed in [19]. Parameters of the model circuit will be consumed.
are: Vp = 0.16V, Vn = 0.15V, Ap = 4000, An = 4000, However, the proposed MRL-based CLAs take the volt-
xp = 0.3, xn = 0.5, αp = 1, a1 = 0.17,a2 = 0.17, age as logic variable, where high voltage and low voltage
b = 0.05, x0 = 0.11. Here ci is from the lowest bit carry, represent logic variables ‘‘1’’ and ‘‘0’’ respectively, which
and the waveforms of b3 − b0 are consistent with those of is compatible with traditional CMOS circuits. Furthermore,
a3 -a0 . The simulation results are shown in Fig. 10, where the MRL-based CLAs do not require the initialization of the
V (s3 )-V (s0 ) are the output sum from the highest bit to the memristors and the reading/writing circuit.
lowest bit, and V (c0 ) is the highest bit carry. The sum On the other hand, the number of memristors used in the
of the carry-lookahead adder and the carry waveforms are proposed CLA is less than that used in IMP-based CLA [22].
consistent with expectations. The size of the memristor is about 3 nm, while the size

VOLUME 7, 2019 43695

 G. Liu et al.: CLA Based on Hybrid CMOS-Memristor Logic Circuit

of the CMOS is 180 nm. In the logic circuit of the MRL [9] M. Teimoori, A. Ahmadi, S. Alirezaee, and M. Ahmadi, ‘‘A novel hybrid
design, a MOSFET can completely accommodate multiple CMOS-memristor logic circuit using Memristor Ratioed Logic,’’ in Proc.
IEEE Can. Conf. Elect. Comput. Eng., Mar. 2016, pp. 1–4.
memristors in technology, so the chip area overhead of the [10] M. Teimoory, A. Amirsoleimani, A. Ahmadi, and M. Ahmadi, ‘‘A hybrid
MRL-based circuit is quite smaller than that of CMOS-based memristor-CMOS multiplier design based on memristive universal logic
circuit. The number of memristors and CMOSs used in the gates,’’ in Proc. IEEE 60th Int. Midwest Symp. Circuits Syst., Aug. 2017,
pp. 1422–1425.
improved CLA is further reduced than the MRL-based CLA, [11] J. K. Eshraghian et al., ‘‘Maximization of crossbar array memory using
so the chip area of the improved CLA is the smallest com- fundamental memristor theory,’’ IEEE Trans. Circuits Syst., II, Exp. Briefs,
pared with the other two CLAs, as shown in Table 2. vol. 64, no. 12, pp. 1402–1406, Dec. 2017.
[12] J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and
R. S. Williams, ‘‘‘Memristive’ switches enable ‘stateful’ logic opera-
VI. CONCLUSION tions via material implication,’’ Nature, vol. 464, no. 7290, pp. 873–876,
This paper proposes two 4-bit carry-lookahead adders based Apr. 2010.
[13] S. Kvatinsky et al., ‘‘MAGIC—Memristor-aided logic,’’ IEEE Trans. Cir-
on MRL logic, which is compatible with the traditional cuits Syst., II, Exp. Briefs, vol. 61, no. 11, pp. 895–899, Nov. 2014.
CMOS technology. On this basis, an improved CLA is [14] S. Kvatinsky, N. Wald, G. Satat, A. Kolodny, U. C. Weiser, and
designed by using ULGs, which decreases the number of the E. G. Friedman, ‘‘MRL—Memristor ratioed logic,’’ in Proc. 13th Int.
Workshop Cellular Nanosc. Netw. Appl., Oct. 2012, vol. 8456, no. 24,
memristors and CMOSs significantly, and reduces the power pp. 1–6.
consumption and the chip area. LTSPICE is used to simulate [15] A. Kanapyanov and O. Krestinskaya. (May 2018). ‘‘Analog multiplier
the designed circuits, and the results are consistent with the design with CMOS-memristor circuits.’’ [Online]. Available: https://
arxiv.org/abs/1805.07680
expectation. Furthermore, the design can be extended to a [16] P. L. Thangkhiew, R. Gharpinde, P. V. Chowdhary, K. Datta, and
multi-bit carry-lookahead adder. I. Sengupta, ‘‘Area efficient implementation of ripple carry adder using
memristor crossbar arrays,’’ in Proc. 11th Int. Design Test Symp. (IDT),
Dec. 2016, pp. 142–147.
REFERENCES [17] A. Karimi and A. Rezai, ‘‘Novel design for a memristor-based full adder
[1] A. Karimi, A. Rezai, and M. M. Hajhashemkhani, ‘‘A novel design using a new IMPLY logic approach,’’ J. Comput. Electron., vol. 17, no. 3,
for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage pp. 1303–1314, 2018.
power,’’ Integration, vol. 60, pp. 160–166, Jan. 2018. [18] H. Bao, N. Wang, H. Wu, Z. Song, and B. Bao, ‘‘Bi-stability in an improved
[2] H. Rashidi, A. Rezai, and S. Soltany, ‘‘High-performance multiplexer memristor-based third-order Wien-bridge oscillator,’’ IETE Tech. Rev.,
architecture for quantum-dot cellular automata,’’ J. Comput. Electron., vol. 36, no. 2, pp. 109–116, Jan. 2018.
vol. 15, no. 3, pp. 968–981, Sep. 2016. [19] C. Yakopcic, T. M. Taha, G. Subramanyam, R. E. Pino, and S. Rogers,
[3] I. Vourkas and G. C. Sirakoulis, ‘‘Emerging memristor-based logic circuit ‘‘A memristor device model,’’ IEEE Electron Device Lett., vol. 32, no. 10,
design approaches: A review,’’ IEEE Circuits Syst. Mag., vol. 16, no. 3, pp. 1436–1438, Oct. 2011.
pp. 15–30, 3rd Quart., 2016. [20] Z. Biolek, D. Biolek, and V. Biolkova, ‘‘SPICE model of memristor with
[4] L. O. Chua, ‘‘Memristor-the missing circuit element,’’ IEEE Trans. Circuit nonlinear dopant drift,’’ Radioengineering, vol. 18, no. 2, pp. 210–214,
Theory, vol. 18, no. 5, pp. 507–519, Sep. 1971. Jun. 2009.
[5] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, [21] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs,
‘‘The missing memristor found,’’ Nature, vol. 453, pp. 80–83, May 2008. 2nd ed. 2010.
[6] Y. V. Pershin and M. Di Ventra, ‘‘Practical approach to programmable [22] A. H. Shaltoot and A. H. Madian, ‘‘Memristor based carry lookahead
analog circuits with memristors,’’ IEEE Trans. Circuits Syst. I, Reg. Papers, adder architectures,’’ in Proc. IEEE 55th Int. Midwest Symp. Circuits Syst.,
vol. 57, no. 8, pp. 1857–1864, Aug. 2010. Sep. Aug. 2012, pp. 298–301.
[7] M. Hu, H. Li, Y. Chen, Q. Wu, G. S. Rose, and R. W. Linderman, ‘‘Mem-
ristor crossbar-based neuromorphic computing system: A case study,’’
IEEE Trans. Neural Netw. Learn. Syst., vol. 25, no. 10, pp. 1864–1878,
Oct. 2014.
[8] Y. Zhang, X. Wang, and E. G. Friedman, ‘‘Memristor-based circuit design Authors’ photographs and biographies not available at the time of
for multilayer neural networks,’’ IEEE Trans. Circuits Syst. I, Reg. Papers, publication.
vol. 65, no. 2, pp. 677–686, Feb. 2018.

43696 VOLUME 7, 2019