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    DSD Report Format Leela

    Uploaded by

    Rupendra RK

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    © All Rights Reserved
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    DSD Report Format Leela

    Uploaded by

    Rupendra RK
    7 views3 pages

    Copyright

    © © All Rights Reserved

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    Download as docx, pdf, or txt
    7 views3 pages

    DSD Report Format Leela

    Uploaded by

    Rupendra RK

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
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    A Course Based Project on

    PROCESSOR DESIGN USING VERILOG HDL


    Submitted to the
    Department of ECE

    in partial fulfilment of the requirements for the


    completion of course

    Digital System Design


    Laboratory(A19PC2EC03)

    BACHELOR OF TECHNOLOGY
    in
    ELECTRONIC AND COMMUNICATION ENGINEERING
    Submitted by
    20071A04F7 ABIN BENI
    20071A04F4 MOHAMMED SAHEEL
    20071A04H8 V.SATWIK BABU
    20071A04G0 SHIVARAM
    20071A04E9 M.KAMAL SAI

    Under the guidance of


    Ms. G.Sahithya,
    Ms. S.Naga Leela
    (Course Instructors)

    VALLURUPALLI NAGESWARA RAO VIGNANA JYOTHI INSTITUTE OF


    ENGINEERING & TECHNOLOGY

    23
    An Autonomous Institute, NAAC Accredited with ‘A++’ Grade,
    NBA
    Vignana Jyothi Nagar, Pragathi Nagar, Nizampet (S.O), Hyderabad – 500 090, TS,
    India
    2022-23

    VALLURUPALLI NAGESWARA RAO VIGNANA JYOTHI INSTITUTE OF


    ENGINEERING AND TECHNOLOGY
    An Autonomous Institute, NAAC Accredited with ‘A++’ Grade, NBA Accredited for CE, EEE, ME, ECE, CSE,
    EIE, IT B. Tech Courses, Approved by AICTE, New Delhi, Affiliated to JNTUH, Recognized as “College with
    Potential for Excellence” by UGC, ISO 9001:2015 Certified, QS I GUAGE Diamond Rated

    Vignana Jyothi Nagar, Pragathi Nagar, Nizampet(SO), Hyderabad-500090, TS, India

    CERTIFICATE

    This is to certify that the course based project entitled “Tittle of the project” that is being
    submitted by N S ABIN BENI (20071A04F7), Md. SAHEEL (20071A04F4), V SATWIK
    BABU (20071A04H8), SHIVARAM ( 20071A04G0), M.KAMAL SAI ( 20071A04E9) for the
    fulfillment of Digital System Design (A19PC2EC03) in II year I semester of Bachelor of
    Technology in Electronics and Communication Engineering of the VNRVJIET, Hyderabad
    during the academic year 2022-2023 is a work carried out by them under our
    guidance and supervision.

    Course Coordinator Course Coordinator Head of the Dept.


    Ms. G. Sahithya Ms. S. Naga Leela Dr. S. Rajendra Prasad
    Assistant Professor Assistant Professor Professor & Head
    23
    VNRVJIET, Hyd. VNRVJIET, Hyd. VNRVJIET, Hyd

    23

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