DLD Lab Manual - 240605 - 203418

Lab Manual
DIGITAL LOGIC DESIGN
Faculty of Computing & Information Technology (FCIT)

University of the Punjab, Lahore.
www.pucit.edu.pk
DIGITAL LOGIC DESIGN
LAB Manual
Instructor Name: Dr. Arifa Mirza
Faculty of Computing & Information Technology
University of the Punjab, Lahore, Pakistan.
Digital Logic Design Lab Dr. Arifa Mirza

BS FCIT Assistant Professor
DIGITAL LOGIC DESIGN LAB 01
Topic: Familiarization with Digital Electronic Trainer, Breadboard and
Integrated Circuits (IC’s)
Basic Overview:
The trainer we are using in our lab is Logic Trainer Model (EES 2001) shown
in figure 1. It has many built-in functionalities, for example breadboards, power
supply, switches, variable resistors and state monitors (LEDs) etc.
Figure 1: Logic Trainer Model (EES 2001)
The Integrated Circuits (IC) has 14 pins that are being inserted into these dots. The
identification mark indicates its correct insertion side. It has pins from 1 to 14. High
voltage current VCC is applied to pin 14 and pin 7 is being grounded. Remaining pins
are used for input output connections.
-----------------------------------------------------------------------

DIGITAL LOGIC DESIGN LAB 02
Topic: Implementation of AND, OR and NOT gates using IC’s
Aim:
To study and verify the Truth Tables of AND, OR & NOT logic gates
Components:
IC 7408 (AND), 7432 (OR), 7404 (NOT)
Internal Architecture of Various ICs

Basic Overview:
1) AND GATE:
An AND gate has two inputs but only one output. The output assumes
the logic 1 state only when each one of its inputs is at logic 1 state. The output
assumes logic 0 state even if one of its inputs is at logic 0 state. With input
variables A & B the Boolean expression for output can be written as;
X = A.B
In IC 7408, pin 1, 2, 4, 5, 9, 10, 12 & 13 are input pins and 3, 6, 8 & 11 are their
corresponding output pins. One can use any one combination of pins for creating
logical AND gate. Input pins are attached with switches using wires and output pins
are with LED. If the LED glows as it should be, the experiment is successful.

2) OR GATE:
An OR gate has two inputs but only one output. The output assumes the
logic 1 state, even if one of its inputs is in logic 1 state. Its output assumes
logic 0 state, only when each one of its inputs is in logic 0 state. With input
variables A & B the Boolean expression for output can be written as;
X = A+B
logical OR gate. Input pins are attached with switches using wires and output pins
are with LED. If the LED glows as it should be, the experiment is successful.
Pin diagram of IC74LS32:
3) NOT GATE:
A NOT gate has only one input and one output. It is also known as “inverter”.
It is a device whose output is always the complement of its input. That is the
output assumes the logic 1 state when its input is in logic 0 state and assumes
the logic 0 state when its input is in logic 1 state. With input variable A the
Boolean expression for output can be written as;

Logic symbol: Truth table:
Input Output
A X
0 1
1 0
In IC 7404, pin 1, 3, 5, 9, 11, 13 are input pins and 2, 4, 6, 8, 10, 12 are their
logical NOT gate. Input pin is attached with switch using wire and output pin is with
LED. If the LED glows as it should be, the experiment is successful.
Pin diagram of IC74LS04:
-------------------------------------------------------------------------

DLD LAB 03
Topic: Implementation of NAND, NOR and conversion of NAND &
NOR gates using IC’s
Aim:
To study and verify the Truth Tables of NAND & NOR logic gates
Components:
IC 7400 (NAND), 7402 (NOR)
Apparatus:
Logic trainer, ICs, Connecting Wires
Basic Overview:
1) NAND GATE:
NAND gate is universal gate. NAND means NOT AND that is, AND
output is inverted, so NAND gate is combination of an AND gate and a NOT
gate. The output is logic 0 level, only when each of its inputs assumes a logic
1 level. For any other combination of inputs, the output is logic 1 level. NAND
gate is equivalent to a bubbled OR gate.
logical NAND gate. Input pins are attached with switches using wires and output
pins are with LED. If the LED glows as it should be, the experiment is successful.

2) NOR GATE:
NOR gate is universal gate. NOR means NOT OR that is, OR output is
inverted, so NOR gate is combination of an OR gate and a NOT gate. The
output is logic 1 level, only when each of its inputs assumes a logic 0 level.
For any other combination of inputs, the output is logic 0 level. For any other
combination of inputs, the output is logic 1 level. NOR gate is equivalent to a
bubbled AND gate.
logical NAND gate. Input pins are attached with switches using wires and output
pins are with LED. If the LED glows as it should be, the experiment is successful.

3) Conversion of NAND & NOR GATE:
It often happens on a logic circuit board that a NAND gate and a few
inverters may be available, whereas in reality an NOR function is required.
If this occurs then all is not lost. It is still possible to create an OR function
from an AND / NAND gate and inverters, or an AND gate from a NOR / OR
function. The diagram below gives some of the conversions. As an example,
it can be seen that a NOR gate is the same as an AND gate with two
inverters on the input. It is then possible to add inverters to create the
function that is required.
AND Gate and OR Gate Equivalents

LAB 04
Topic: Construction of XOR & XNOR gate using NAND & NOR gates
Apparatus:
Logic trainer, ICs, Connecting Wires
Basic Overview:
1. XNOR using NAND & NOR:
 Boolean expression of XNOR gate:

If A and B be the two inputs of an Exclusive NOR gate then the Boolean expression
for the output of XNOR gate is
Y=AB+AˉBˉ
 Circuit symbol of XNOR gate:
Exclusive NOR gate is the inverter of Exclusive OR gate. It consists a XOR gate and
a NOT gate in series which is shown below.
 Truth table of XNOR gate with 2 inputs:
Let a two input XNOR gate with the inputs A and B and the output of this gate is Y.
Then the truth table for the Ex-NOR gate with two inputs is as following
A B Y=AB+AˉBˉ
0 0 1
0 1 0
1 0 0
1 1 1
 Circuit diagram of XNOR gate using NAND gate:

 Circuit diagram of XNOR gate using NOR gate:
2. XOR using NAND & NOR:

 Truth Table of XOR gate:
Table-1 and Table -2 are the Truth tables for XOR gate with two inputs and three
inputs respectively.
Input (A) Input (B) Output, Y=AB‾+A‾B

0 0 0
0 1 1
1 0 1
1 1 0
 Circuit diagram of XOR gate using NOR gate:
 Circuit diagram of XOR gate using NAND gate:
-----------------------------------------------------------------------

Implement NAND gate using NOR gates only
Implement NOR gate using NAND gates only
---------------------------------------------------------------------------

Task LAB 05
Topic: DeMorgan’s Theorem and Boolean algebra
Objectives
To study DeMorgan’s theory and implement it.
DeMorgan’s Theory is used to convert AND/NAND gates to OR/NOR ones, and

presented OR/NOR gates by AND/NAND gates by these 2-laws:
Task 1: A’ . B’ = ( A + B)’
(a) Implement using NOT/AND/OR gates.
(b) Implement using NAND gates only.

Task 2: A’ + B’= (A. B)’
(a) Implement using NOT/AND/OR gates.
(b) Implement using NOR gates only.

Class:___________ Roll no. : ___
Task LAB 06
Topic: Digital logic circuits analysis and converting Boolean expressions to digital
circuits
Objectives:
 To learn how to directly convert a Boolean expression to circuit.
 To learn how to analyze a given digital logic circuit by finding the Boolean expression that
represents the circuit
 To learn how to analyze a given digital logic circuit by finding the truth table that represents
the circuit.
Task 1: Converting Boolean expressions into circuits:
Z = A + B . C’
The above function is implemented in the following digital logic Circuit:
Now after drawing the circuit we find that its truth table is as shown below:

Task 2: Converting Boolean expressions into circuits:
D = ( A . B ) + ( C’ . A )
Draw the circuit in the space below:
Now, fill-in the truth table of the circuit you drawn.

Task 3: Digital logic circuit analysis – Finding the Boolean expression of a given circuit:
Find the Boolean expression of the following circuit,
D=
and simulate it to fill-in its truth table

Task 4: Logic circuits with multiple outputs:
Find the Boolean expression of the outputs of the following circuit,
D=
E=
and simulate it to fill-in its truth table
Task 5: Converting Boolean expressions to circuits:

Use the logic converter to realize the following circuit using suitable logic gates:
AB'C (BD + CDE) + AC’

Class:___________ Roll no. : ___
Task LAB 06 B
Boolean algebra and Simplification of Boolean expressions

Task 1: Circuit analysis
Find the Boolean expression that represents the outputs X and Y shown in the
following circuit.
According to the circuit above find the equation for X and Y, then fill the truth
table.
X=
Y=

Draw the simplified and the original Boolean expression and make sure that
they are both equivalent by filling-in the table. Implement in the lab.
Task 2: Simplifying Boolean function

F (A, B) = (A . B) + A' (A+B)
Task 3: Simplifying Boolean function

F (A, B, C) = (A+C') + C (C.A' + (B.A) +C)

Class:___________ Roll no. : ___
Task LAB 07
Boolean algebra and Simplification of Boolean expressions Karnaugh

Map (K-Map) method
Objectives
Learn how to simplify Boolean logic equations using K-maps.
Draw the simplified and the original Boolean expression and make sure that
they are both equivalent by filling-in the table. Implement in the lab.
Simplify the given Boolean functions by using K-Map.
Task 1: F (A, B, C) = AB'C'+ A'B'C'+ A'BC'+ A'B'C
Task 2: F (A, B, C, D) = A'C'D' + A'B'C'D + A'B'C + ABCD + AC'

Task LAB 08
Topic: Multiple input logic gates
Simplify the given Boolean functions. Implement in the lab by using multiple input
gates.
F (A, B, C, D) = A'C'D' + A'B'C'D + A'B'C + ABCD + AC'
Following ICs are also available in lab in addition to all ICs we have used in previous labs.

DLD LAB 09
Topic: Binary Adders (Half adder and full adder)
Half Adder:
Specification: 2 inputs (X,Y)
2 outputs (C,S)
From the verbal explanation of a half adder, we find that this circuit needs two binary inputs and
two binary outputs. The input variables designate the augend and addend bits; the output variables
produce the sum and carry. We assign symbols x and y to the two inputs and S (for sum) and C
(for carry) to the outputs. The truth table for the half adder is listed in Table.
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
The C output is 1 only when both inputs are 1. The S output represents the least significant bit of the sum.

DLD LAB 10
Topic: Binary Subtractors (Half and full Subtractor)

Full Subtractor

DLD LAB 11
Topic: COMBINATIONAL LOGIC CIRCUITS - Decoders
A decoder is a combinational circuit that converts binary information from n

input lines to a maximum of 2n unique output lines.
The 2-to-4 Decoder:

The 3 x 8 Decoder:

DLD LAB 12
Topic: COMBINATIONAL LOGIC CIRCUITS - Encoders

Priority Encoders

DLD LAB 13
Topic: Multiplexers
Multiplexers:
• A multiplexer does just the opposite of a decoder.
• It selects a single output from several inputs.
• The particular input chosen for output is determined by the value of the multiplexer’s control
lines.
• To be able to select among n inputs, log2n control lines are needed.
• This is what a 4‐to‐1 multiplexer looks like on the inside.
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

DLD LAB 14
Topic: Implementation Using Multiplexers and DeMultiplexers
Implementation Using Multiplexers

DeMultiplexers / Decoders

DLD LAB 15
Topic: 7-Segment Display, BCD to seven segment

DLD LAB 16
Topic: Sequential Circuit - Flip Flops
SR Flip Flop with NOR Gates
S R Q Q’
Q 1 0 1 0
0 0 1 0 ( after S = 1, R = 0)
0 1 0 1
0 0 0 1 ( after S = 0, R = 1)
Q’
1 1 0 0
(a) Logic diagram (b) Function table
SR Flip Flop with NAND Gates
S R Q Q
Q
1 0 0 1
1 1 0 1 ( after S = 1, R = 0)
0 1 1 0
1 1 1 0 ( after S = 0, R = 1)
Q 0 0 1 1
(a) Logic diagram (b) Function table


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Lab Manual

DIGITAL LOGIC DESIGN

Faculty of Computing & Information Technology (FCIT)

Digital Logic Design Lab Dr. Arifa Mirza

Figure 1: Logic Trainer Model (EES 2001)

Digital Logic Design Lab Dr. Arifa Mirza

Internal Architecture of Various ICs

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza

AND Gate and OR Gate Equivalents

Digital Logic Design Lab Dr. Arifa Mirza

 Boolean expression of XNOR gate:

 Truth table of XNOR gate with 2 inputs:

 Circuit diagram of XNOR gate using NAND gate:

Digital Logic Design Lab Dr. Arifa Mirza

2. XOR using NAND & NOR:

Input (A) Input (B) Output, Y=AB‾+A‾B

 Circuit diagram of XOR gate using NOR gate:

 Circuit diagram of XOR gate using NAND gate:

Digital Logic Design Lab Dr. Arifa Mirza

Implement NOR gate using NAND gates only

Digital Logic Design Lab Dr. Arifa Mirza

To study DeMorgan’s theory and implement it.

DeMorgan’s Theory is used to convert AND/NAND gates to OR/NOR ones, and

(a) Implement using NOT/AND/OR gates.

(b) Implement using NAND gates only.

Digital Logic Design Lab Dr. Arifa Mirza

(a) Implement using NOT/AND/OR gates.

(b) Implement using NOR gates only.

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza

Now, fill-in the truth table of the circuit you drawn.

Digital Logic Design Lab Dr. Arifa Mirza

and simulate it to fill-in its truth table

Digital Logic Design Lab Dr. Arifa Mirza

and simulate it to fill-in its truth table

Task 5: Converting Boolean expressions to circuits:

Digital Logic Design Lab Dr. Arifa Mirza

Boolean algebra and Simplification of Boolean expressions

Digital Logic Design Lab Dr. Arifa Mirza

Task 2: Simplifying Boolean function

Task 3: Simplifying Boolean function

Digital Logic Design Lab Dr. Arifa Mirza

Boolean algebra and Simplification of Boolean expressions Karnaugh

Learn how to simplify Boolean logic equations using K-maps.

Simplify the given Boolean functions by using K-Map.

Task 1: F (A, B, C) = AB'C'+ A'B'C'+ A'BC'+ A'B'C

Task 2: F (A, B, C, D) = A'C'D' + A'B'C'D + A'B'C + ABCD + AC'

Digital Logic Design Lab Dr. Arifa Mirza

Topic: Multiple input logic gates

F (A, B, C, D) = A'C'D' + A'B'C'D + A'B'C + ABCD + AC'

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza

Digital Logic Design Lab Dr. Arifa Mirza