Updated - Analog & Digital Circuit Manual - BECL305

Department of Electronics & Communication Engineering
Analog and Digital Systems Design Laboratory Manual

Sub Code: BECL305
PROGRAM OUTCOMES
Engineering graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs
with appropriate consideration for the public health and safety, and the cultural,
societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge
and research methods including design of experiments, analysis and interpretation
of data, and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources,and
modern
engineering and IT tools including prediction and modelling to complex
engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual

knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large, such as, being
able to comprehend and write effective reports and design documentation, make
effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these to
one’s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context of
technological change
PEO (Program Educational Objectives)
PEO1 : Proficiency to work in multidisciplinary domains, technological

advancements through continuous learning process.
PEO2 : Graduate with moral and ethical values
PEO3 : Explore the research possibilities, innovative practices and

entrepreneurship.
PSO (Program Specific Outcomes)
PSO1: Understand, analyze and realize the concepts in the field of analog and digital
signal processing, communication, networking and semiconductor technology by
applying modern design tools.
PSO2: Ability to enrich the design in electronics through optimization, better

efficiency and innovative ideas
PSO3: Enabling the graduates with excellent technical and soft skills, lifelong
learning, leadership qualities, ethics and societal responsibilities.
Safety Measure
 Execution of Lab work in a safe manner is even more important than

performing accurate electronic measurements and construction neat
circuits.
 You should also know all equipment’s and components that are used in the
Lab to take the necessary precautions.
 Always power down the electrical equipment, disconnect the power cord,
and wait for a few seconds before touching exposed wires. And make sure
that your hands are dry.
 Do not wear rings, watches, necklace, and any other loose metallic objects.
Rings and watches are especially dangerous as the skin beneath them is wet
by sweat, making the resistance of skin much lower.
 In case of electric shock, cut the power and/or remove the victim as quickly
as possible without endangering yourself.
COURSE OUTCOMES (With PO & PSO Mapping)
Analog and Digital Systems Design

Semester 3rd Subject Name/Code Laboratory BECL305
Course Outcomes PO & PSO

PO1,PO2,PO3,PO4,P
CO1 Design and analyze the BJT/FET amplifier and oscillator
O8,PO9,PO10,PSO1,
circuits.
PSO2
PO1,PO2,PO3,PO4,P
CO2 Design and test Opamp circuits to realize the mathematical
O8,PO9,PO10,PSO1,
computations, DAC and precision rectifiers.
PSO2
Design and test the combinational logic circuits for the PO1,PO2,PO3,PO4,P
CO3
given specifications. O8,PO9,PO10,PSO1,
PSO2
PO1,PO2,PO3,PO4,P
CO4
Test the sequential logic circuits for the given functionality. O8,PO9,PO10,PSO1,
PSO2
PO1,PO2,PO3,PO4,P
CO5 Demonstrate the basic circuit experiments using 555 timer. O8,PO9,PO10,PSO1,
PSO2
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 P09 PO10 PO11 PO12 PSO1 PSO2 PSO3
CO1 3 3 3 2 2 2 2 3 1
CO2 3 3 3 2 2 2 2 3 2
CO3 3 3 3 2 2 1 2 3 1
CO4 3 3 1 2 2 1 2 3 1
CO5 3 3 1 2 2 1 2 3 1
Note: Correlation levels: 1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High), “-”  No correlation
Analog and Digital Systems Design LaboratoryBECL305
Choice Based Credit System (CBCS) and Outcome Based Education (OBE)
Laboratory Code BECL305 CIE Marks 50
Teaching Hours/Week
0:0:2:0 SEE Marks 50
(L: T:P: S)
Exam Hours
Credits 1 03
Course Learning Objectives: This laboratory course enables students to
 Understand the electronic circuit schematic and its working.
 Realize and test amplifier and oscillator circuits for the given specifications.
 Realize the op-amp circuits for the applications such as DAC, implement
mathematical functions and precision rectifiers.
 Study the static characteristics of SCR and test the RC triggering circuit.
 Design and test the combinational and sequential logic circuits for their
functionalities.
 Use the suitable ICs based on the specifications and functions.
Experiments (All the experiments have to be conducted using discrete components)
1. Design and set up the BJT common emitter voltage amplifier with and without feedback
and determine the gain- bandwidth product, input and output impedances.
2. Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator
3. Design and set up the circuits using op-amp: i) Adder, ii) Integrator, iii) Differentiator and
iv) Comparator
4. Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) for a 4-bit binary input
using toggle switches (ii) by generating digital inputs using mod-16
5. Design and implement (a) Half Adder & Full Adder using basic gates and NAND gates,
(b) Half subtractor& Full subtractor using NAND gates, (c) 4-variable function using
IC74151(8:1MUX).
6. Realize (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to Excess-3
code conversion and vice versa
7. a) Realize using NAND Gates: i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T
Flip-Flop b) Realize the shift registers using IC7474/7495: (i) SISO (ii) SIPO (iii) PISO
(iv) PIPO (v) Ring counter and (vi) Johnson counter.
8. Realize a) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK
Flip-flop b) Mod-N Counter using IC7490 / 7476 c) Synchronous counter using IC74192
Demonstration Experiments (For CIE)
9. Design and Test the second order Active Filters and plot the frequency response, i) Low
pass Filter ii) High pass Filter
10. Design and test the following using 555 timer i) Monostable Multivibraator ii)
Astable Multivibrator
11. Design and Test a Regulated Power supply
12. Design and test an audio amplifier by connecting a microphone input and observe the
output using a loudspeaker.
Course Outcomes: At the end of the course the student will be able to:
1. Design and analyze the BJT/FET amplifier and oscillator circuits.
2. Design and test Op-amp circuits to realize the mathematical computations, DAC
andprecision rectifiers.
3. Design and test the combinational logic circuits for the given specifications.
4. Test the sequential logic circuits for the given functionality.
5. Demonstrate the basic circuit experiments using 555 timers.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20
marks out of 50) and for the SEE minimum passing mark is 35% of the maximum marks (18
out of 50 marks). A student shall be deemed to have satisfied the academic requirements and
earned the credits allotted to each subject/ course if the student secures a minimum of 40% (40
marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE
(Semester End Examination) taken together.
Continuous Internal Evaluation (CIE):

CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment is to be evaluated for conduction with an observation sheet and
record write-up. Rubrics for the evaluation of the journal/write-up for
hardware/software experiments are designed by the faculty who is handling the
laboratory session and are made known to students at the beginning of the practical
session.
 Record should contain all the specified experiments in the syllabus and each
experiment write-up will be evaluated for 10 marks.
 Total marks scored by the students are scaled down to 30 marks (60% of maximum
marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct a test of 100 marks after the completion of all the
experiments listed in the syllabus.
 In a test, test write-up, conduction of experiment, acceptable result, and procedural
knowledge will carry a weightage of 60% and the rest 40% for viva- voce.
 The suitable rubrics can be designed to evaluate each student’s performance and
learning ability.
 The marks scored shall be scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and marks of
a test is the total CIE marks scored by the student.
Semester End Evaluation (SEE):
 SEE marks for the practical course are 50 Marks.
 SEE shall be conducted jointly by the two examiners of the same institute, examiners
are appointed by the Head of the Institute.
 The examination schedule and names of examiners are informed to the university
before the conduction of the examination. These practical examinations are to be
conducted between the schedule mentioned in the academic calendar of the University.
 All laboratory experiments are to be included for practical examination.
 (Rubrics) Breakup of marks and the instructions printed on the cover page of the
answer script to be strictly adhered to by the examiners. OR based on the course
requirement evaluation rubrics shall be decided jointly by examiners.
 Students can pick one question (experiment) from the questions lot prepared by the
examiners jointly.
 Evaluation of test write-up/ conduction procedure and result/viva will be conducted
jointly by examiners.
 General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction
procedure and result in -60%, Viva-voce 20% of maximum marks. SEE for practical
shall be evaluated for 100 marks and scored marks shall be scaled down to 50 marks
(however, based on course type, rubrics shall be decided by the examiners) Change
of experiment is allowed only once and 15% of Marks allotted to the procedure part
are to be made zero. The minimum duration of SEE is 02 hours.
CONTENTS
EXP. PAGE
NAME OF THE EXPERIMENT CO RBT
NO NO
Experiments (All the experiments have to be conducted using discrete components)
Design and set up the BJT common emitter voltage
L3, L4
1 amplifier with and without feedback and determine the CO1 1-7
, L6
gain- bandwidth product, input and output impedances.
L3,L4
Design and set-up BJT/FET i) Colpitts Oscillator, ii)
2 CO1 ,L6 8-15
Crystal Oscillator
L3,L4
Design and set up the circuits using opamp: i) Adder, ii)
3 CO2 ,L6 9-24
Integrator, iii) Differentiator and iv) Comparator
Design 4-bit R – 2R Op-Amp Digital to Analog L3,L4
4 Converter (i) for a 4-bit binary input using toggle CO2 ,L6 25-30
switches (ii) by generating digital inputs using mod-16
Design and implement (a) Half Adder & Full Adder L3,L4
using basic gates and NAND gates, (b) Half ,L6
5 CO3 31-38
subtractor& Full subtractor using NAND gates, (c) 4-
variable function using IC74151(8:1MUX).
Realize (i) Binary to Gray code conversion & vice- L3,L4
6 versa (IC74139), (ii) BCD to Excess-3 code conversion CO3 ,L6 39-44
and vice versa
a) Realize using NAND Gates: i) Master-Slave JK Flip- L3,L4
Flop, ii) D Flip-Flop and iii) T Flip-Flop b) Realize the ,L6
7 shift registers using IC7474/7495: (i) SISO (ii) SIPO CO4 45-53
(iii) PISO (iv) PIPO (v) Ring counter and (vi) Johnson
counter.
Realize a) Design Mod – N Synchronous Up Counter & L3,L4
Down Counter using 7476 JK Flip-flop b) Mod-N ,L6
8 CO4 54-61
Counter using IC7490 / 7476 c) Synchronous counter
using IC74192
Demonstration Experiments (For CIE)
Design and Test the second order Active Filters and L3,L4
CO5
9 plot the frequency response, i) Low pass Filter ii) High ,L6 62-70
pass Filter
L3,L4
Design and test the following using 555 timer i) CO5
10 ,L6 71-79
Monostable Multivibraator ii) Astable
Multivibrator
L3,L4
CO5
11 Design and Test a Regulated Power supply ,L6 80-81
Design and test an audio amplifier by connecting a L3,L4

CO5
12 microphone input and observe the output using a loud ,L6 82-83
speaker.
13 Appendix 84-87
PREFACE
Analog and Digital Electronic Circuits Laboratory is an introductory experimental
laboratory that explores the design, construction, and debugging of analog electronic
circuits and Digital circuits both combinational and sequential circuits. This laboratory
investigates the performance of transistors, JFETs/MOSFETs, and op-amps, timers, Logic
gates which includes the construction of an amplifier, Oscillators, multi-vibrators, data
conversion, rectifiers, Flip-flops, Adders and subtractors, counters, code converters
random generator and other applications. Fifteen weeks are devoted to the design and
implementation of discrete experiments. Written and oral viva-voce of a experiment is
conducted in an environment similar to that of engineering design teams in industry. The
course provides opportunity to design, analyze and test real-world problems and
solutions that involve tradeoffs and the use of engineering judgment.

Analog and Digital Systems Design Lab BECL305
EXPERIMENT No-1: BJT COMMON EMITTER VOLTAGE AMPLIFIER
Design and set up the BJT Common emitter voltage amplifier with and without feedback
and determine the gain-bandwidth product, input and output impedances.
AIM: - To Study the Common Emitter Amplifier and to find

1. Cut off frequencies.
2. Bandwidth
3. Mid band Voltage gain and Gain bandwidth product.
COMPONENTS/APPARATUS REQUIRED
Sl.
Apparatus and Components Range Quantity
No
1 Cathode Ray Oscilloscope 30Mhz 1
2 Regulated Power Supply 0-30v 1
3 Bread Board ………….. 1
4 Function generator 1MHz 1
5 Transistor BC107 B 1
R1(22KΩ) 1
R2(4.7kΩ) 1
6 Resistors RC(2.2KΩ) 1
RE(560Ω) 1
Cb,Cc(0.47μF) 2
7 Capacitors
Ce (47μF) 1
THEORY:
The CE amplifier provides high gain &wide frequency response. The emitter lead is common
to both input and output circuits and is grounded. The emitter base circuit is forward biased.
The collector current is controlled by the emitter base circuit is forward biased. The collector
current is controlled by the base current rather than emitter current. The input signal is applied
to base terminal of the transistor and amplifier output is taken across collector terminal very
small change in base current produces a much larger change in collector current. When +ve
half cycle is fed to the input circuit,it opposes the forward bias of the circuit which causes the
collector current to decrease, it decreases the voltage more –ve.thus when input cycle varies
through a –ve half cycle, increases the forward bias of the circuit , which causes the collector
current to increases thus the output signal is common emitter amplifier is in out of phase with
the input signal.
Dept. of ECE, RVITM Page 1

CIRCUIT DIAGRAM (with Feedback):
Fig(a) Circuit Diagram for Common Emitter Amplifier without Feedback
CIRCUIT DIAGRAM (without Feedback) :
Fig(b) Circuit Diagram for Common Emitter Amplifier with Feedback

PROCEDURE
1. Connect the circuit as shown above.
2. Feed a sine wave signal of amplitude 30 mV from signal generator.
3. Keep the frequency of the signal generator in mid band range i.e., around 2 KHz. Increase
amplitude of the input signal till the output signal is undistorted.(CRO at output).
4. Measure Vi amplitude = V for corresponding maximum undistorted output.
5. Measure Vo amplitude = V
6. The ratio of (Vo/Vi) max gives the maximum undistorted gain of the amplifier.
7. Now vary the input sine wave frequency from 5 Hz to 3 MHz in suitable steps. Measure
output voltage amplitude at each step using CRO.(See that amplitude of Vi remains constant
throughout the frequency range.)
8. Tabulate the results in the tabular column shown below.
9. Plot the frequency i.e., frequency versus Gain in dB, determine Bandwidth and G.B.W
product.
TABULAR COLUMN
Note downVi (P-P)…….
Common Emitter Amplifierwithout Feedback
SI. Output Voltage Gain=

Frequency(Hz) Voltage Gain= Vo/Vi
No (P-P)Volts 20log(Vo/Vi)
1 5Hz
2
3
4
5
6
7
8
9
10
11 3MHz
Common Emitter Amplifierwith Feedback
SI. Output Voltage Gain=

Frequency(Hz) Voltage Gain= Vo/Vi
No (P-P)Volts 20log(Vo/Vi)
1 5Hz
2
3
4
5
6
7
8
9
10
11 3MHz
Frequency Response
 f1 is Lower Cut-Off Frequency.

 f2 is Higher Cut-Off Frequency.
 Av is the Voltage Gain = 20log10 (Vo/Vi).
 Av mid is the Voltage Gain at mid-band.
 F2-F1 is the Band width of the amplifier.
 3dB = 20log10 (0.707).
RESULT
Thus the Common Emitter Amplifier was designed and studied.

VIVA questions and answers
1. What is a Common Emitter Amplifier?

Ans : A transistor in which the emitter terminal is made common for both the input and the
output circuit connections is known as common emitter configuration. When this
configuration is provided with the supply of the alternating current (AC) and operated
in between the both positive and the negative halves of the cycle in order to generate
the specific output signal is known as common emitter amplifier.
2. What are the characteristics of the common emitteramplifier?

 The voltage gain value obtained for the common emitter amplifier is medium.
 It also consists of the current gain in the medium range.
 Because of both the voltage and the current gains the power gain value of this
configuration is referred to be high.
 There is some resistance value at the inputs as well as the output but in this
configuration, it is maintained at the medium value.
 As the signals at the output generated because of the input signals applied are in
180-degree shift of the phase.
3. What is the effect of voltage series feedback?

Ans : In Voltage-Series feedback, the input impedance of the amplifier is increased and the
output impedance is decreased. Noise and distortions are reduced considerably.
4. What are the applications of common emitter amplifier?

Ans : These amplifiers are preferably used as the current amplifier than a voltage amplifier
as it has more current gain than the voltage gain.
In the radio frequency circuitry this configuration is preferred.
For the lower values of noise and its amplification this configuration is preferred.

EXPERIMENT No- 2(A) : COLPITTS OSCILLATOR

Design and set-up BJT/FET i) Colpitts Oscillator (ii) Crystal Oscillator
AIM: To calculate the output frequency of Colpitt’s oscillator theoretically and practically.
Sl.
No.
1 Cathode Ray Oscilloscope 30Mhz 1
4 Transistor BC107 1
10KΩ, 4.7KΩ
5 Resistors 560Ω,10KΩ Each 1
22KΩ,2.2kΩ
0.47μF 2
6 Capacitors 0.001μF 1
0.5nF 2
7 Inductors 10mH 1
THEORY
The tank circuit is made up of L1, C4 and C5 .The resistance R2 and R3 provides the necessary
biasing. The capacitance C2 blocks the D.C component. The frequency of oscillations is
determined by the values of L1, C4 and C5 and is given by
F=1/(2π(Ct L1 ) where Ct=C4*C5/(C4+C5)
The energy supplied to the tank circuit is of correct phase. The tank circuit provides 1800 in
this way energy feedback to the tank circuit is in phase with the generated oscillations.
CIRCUIT DIAGRAM:

PROCEDURE
1. Rig up the circuit as shown in Fig (a) for Hartley oscillator

2. Adjust 10K POT to obtain proper sinusoidal output waveform.
3. Measure the frequency of oscillations and compare with designed value.
RESULT:
The theoretical output frequency ……………….
Practical output frequency --------------.

EXPERIMENT No-2B: CRYSTAL OSCILLATOR

AIM :Test for the performance of BJT-Crystal oscillator for fo =2MHz.
Sl.
No
1 Cathode Ray Oscilloscope 30MHz 1
4 Transistor BC107 1
4.7KΩ 1
560Ω 1
5 Resistors 10KΩ 1pot
22KΩ 1
2.2kΩ 1
0.47μF 2
6 Capacitors
47μf 1
7 Crystal 2MHz 1
CIRCUIT DIAGRAM

PROCEDURE
1. Make the circuit connection as shown in fig. a

2. The output Vo is obtained on CRO.
3. The 10K POT is adjusted to get a stable output on the screen of CRO.
4. The frequency of oscillations is measured using CRO is then compared with theoretical
values.
RESULT
Theoretical frequency = …2Mhz… Practical frequency = ………………………

1. What is oscillator ?
Ans : An oscillator is a circuit which produces a continuous, repeated, alternating
waveform without any input. Oscillators basically convert unidirectional current flow
from a DC source into an alternating waveform which is of the desired frequency, as
decided by its circuit components.
2. Which type of feedback is used in oscillator. Specify the reason.

Ans : Positive feedback is used in oscillator to satisfy Barkhausen's Criteria in order to produce
sustain oscillations. Oscillator produces sinusoidal waveform without any input signal
hence starting voltage is noise signal which may be due to resistor's, power supply.
Positive feedback is used to have more gain. For oscillator the gain should be at
maximum to have sustained oscillations. On other hand negative feedback decreases
the gain but gives stability to the system. Usually negative feedback is used in
amplifiers.
3. What is BARKHAUSEN CRITERION for oscillator

Ans : The magnitude of the product of open loop gain of the amplifier and the magnitude
of the feedback factor is unity, i.e., |βA|=1 where A is the gain of the amplifying
element in the circuit and β(jω) is the transfer function of the feedback path.
The total phase shift around the loop is 0or integral multiples of 2π.
4. What are the advantages of Colpitts oscillator?

The advantages of Colpitts oscillator are as follows :
 Colpitts oscillator can generate sinusoidal signals of very high frequencies.
 It can withstand high and low temperatures.
 The frequency stability is high.
 Frequency can be varied by using both the variable capacitors.
 Less number of components are sufficient.
 The amplitude of the output remains constant over a fixed frequency range.



5. What are the applications of Colpitts oscillator?

Ans : Colpitts oscillator can be used as High frequency sinewave generator.
This can be used as a temperature sensor with some associated circuitry.
Mostly used as a local oscillator in radio receivers.It is also used as R.F. Oscillator.
It is also used in Mobile applications.
6. What are the applications of crystal oscillator?

Ans : They are widely used in computers, instrumentation, digital systems, in phase-locked
loop systems, modems, marine, telecommunications, in sensors and also in disk drives.
7. What is RC phase shift oscillator?

Ans : A phase-shift oscillator is a linear electronic oscillator circuit that produces a sine wave
output. It consists of an inverting amplifier element such as a transistor or op amp with its
output fed back to its input through a phase-shift network consisting of resistors and capacitors
in a ladder network.
8. What is the frequency range of RC phase shift oscillator?

Ans : RC phase shift oscillator is used for generating signals power a wide frequency range.
The frequency can be varied from few Hz to 200 Hz by employing one set of resistor with three
capacitor ganged together.
9. What is oscillator in communication?

Ans : An oscillator is a very useful part of all electronic circuit. In the
communication system for example transmitter, they are used to generate the required carrier
frequency. They are mainly used in the mixers circuit, where cost has to maintain as low as
possible.

EXPERIMENT No- 3: ADDER INTEGRATOR DIFFERENTIATOR&

COMPARATOR
Design and set up the circuits using opamp: i) Adder, ii) Integrator, iii) Differentiator
and iv) Comparator
AIM: To design and test the following circuits using op-amp i)Adder ii) Integrator iii)
Differentiator iv) Comparator for the given input signals.
COMPONENTS REQUIRED:
Sl.
Equipment/Component name Specifications/Value Quantity
No
1 IC 741 Refer page no 2 1
2 Resistor 1kΩ 4
3 Regulated Power supply (0 – 30V),1A 2
4 Function Generator (.1 – 1MHz), 20V p-p 1

5 Cathode Ray Oscilloscope (0 – 20MHz) 1
6 Multimeter 3 ½ digit display 1
THEORY:
i) Adder:A two input summing amplifier may be constructed using the inverting mode.
Theadder can be obtained by using either non-inverting mode or differential amplifier. Here
the inverting mode is used. So the inputs are applied through resistors to the inverting terminal
and non-inverting terminal is grounded. This is called “virtual ground”, i.e. the voltage at that
terminal is zero. The gain of this summing amplifier is 1, any scale factor can be used for the
inputs by selecting proper external resistors.
ii) Integrator: In an integrator circuit, the output voltage is integral of the input signal.
Theoutput voltage of an integrator is given by Vo = -1/R1CftVidt

o
At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like
an open circuit. The gain of an integrator at low frequency can be limited by connectinga
resistor in shunt with capacitor.
iii) Differentiator: In the differentiator circuit the output voltage is the differentiation of the

input voltage. The output voltage of a differentiator is given byVo = -RfC dV/dt. The input
impedance of this circuit decreases with increase in frequency, therebymaking the circuit
sensitive to high frequency noise. At high frequencies circuit may become unstable.
iv) Comparator:The Op-amp comparator compares one analogue voltage level with another
analogue voltage level, or some preset reference voltage, VREF and produces an output signal
based on this voltage comparison. In other words, the op-amp voltage comparator compares
the magnitudes of two voltage inputs and determines which is the largest of the two. Voltage
comparators on the other hand, either use positive feedback or no feedback atall (open-loop
mode) to switch its output between two saturated states, because in the open- loop mode the
amplifiers voltage gain is basically equal to AVO. Then due to this high open loop gain, the
output from the comparator swings either fully to its positive supply rail, +Vcc or fully
to its negative supply rail, -Vcc on the application of varying input signal which passes some
preset threshold value. The open-loop op-amp comparator is an analogue circuit that operates
in its non-linear region as changes in the two analogue inputs, V+ and V-causes it to behave
like a digital bistable device as triggering causes it to have two possible output states, +Vcc or
-Vcc. The voltage comparator is essentially a 1-bit analogue to digital converter, as the input
signal is analogue but the output behaves digitally.
DESIGN:-
i) Adder
Vo = - (V1 + V2)
If V1 = 2.5V and V2 = 2.5V, then
Vo = - (2.5+2.5) = -5V.
ii) Integrator:
Select fa =159Hz. Fb = 10 fa = 1.59KHz.

fa = 1 / (2πRfCf ) fb =1 / (2πR1Cf )
Assume Cf =0.01µf
Rf = 100kΩ, R1 = 10 kΩ
1 T/2
Vo (p-p) = R C Vi ( p p)dt

1 f O

iii) Differentiator:
Model Calculations:
Integrator:
Differentiator

CIRCUIT DIAGRAM :-
i) Adder :-
Figure 1
ii) Integrator:-
Figure 2
iii) Differentiator:
Figure 3

Procedures:
A) Adder:
1. Connect the circuit as per the diagram shown in Fig 1.
2. Apply the supply voltages of +12V to pin7 and pin4 of IC741 respectively.
3. Apply the inputs V1 and V2 as shown in Fig 1.
4. Apply two different signals (DC/AC ) to the inputs
5. Vary the input voltages and note down the corresponding output at pin 6 of the IC 741
adder circuit.
6. Notice that the output is equal to the sum of the two inputs.
B) Integrator
1. Connect the circuit as per the diagram shown in Fig 2
2. Apply a square wave/sine input of 2V(p-p) at 2KHz
3. Observe the output at pin 6.
4. Draw input and output waveforms as shown in Fig.
C) Differentiator
1. Connect the circuit as per the diagram shown in Fig 3
2. Apply a square wave/sine input of 2V(p-p) at 100Hz
3. Observe the output at pin 6
4. Draw the input and output waveforms as shown in Fig.
D) Comparator
1. Connect the circuit as shown in the figure
2. Set the reference voltage as 2V DC.
3. Apply sine wave of 10Vp-p with1KHz frequency from the function generator as Vi.
4. Check the output in CRO and calculate the amplitude of the output wave form.
5. Compare the output wave form amplitude with input signal
Sample readings:
a) Adder:
i) With DC input:i) With AC input:
V1 =……..V V1 = ......... V
V2 =…….V V2 = ........ V
V0 =…….V V0 = ........ V

Integrator:
Input –Square wave Output - Triangular
Amplitude(VP-P) Time period Amplitude (VP-P) Time

(V) (ms) (V) period
(ms)
Input –sine wave Output – cosine
Amplitude(VP-P) Time Amplitude (VP-P) Time

(V) period (V) period
(ms) (ms)
Differentiator:
Input –square wave Output – Spikes
Amplitude (VP-P) Time period Amplitude (VP-P) Time period

(V) (ms) (V) (ms)
Input –sine wave Output – cosine
Amplitude (VP-P) Time period Amplitude (VP-P) Time period

(V) (ms) (V) (ms)
d) Comparator:
i) DC input Vref:….. v
ii) AC input from function generator: …..
iii)Output from CRO: ……..
RESULT:Verified the Adder, Integrator, Differentiator& Comparator circuits using op-amp

w.r.t the specified input signals.

1. What is an integrator?
Ans : An integrator is a circuit that performs a mathematical operation called integration.
2. Give examples of linear circuits.

Ans : Adder, subtractor, differentiator, integrator fall under the category of linear circuits.
3. What is an adder or summing amplifier?

Ans : Adder or summing amplifier is a circuit that provides an output voltage proportional to
or equal to the algebraic sum of two or more input voltages multiplied by a constant
gain factor.
4. What are the limitations of the basic differentiator circuit?

Ans : At high frequency, a differentiator may become unstable and break into oscillations.
The input impedance decreases with increase in frequency.
5. What are the limitations of basic integrator circuit?

Ans : At low frequency, an integrator may become unstable and break into oscillations. The
input impedance decreases with decrease in frequency.
6. Give Examples of Linear Circuits?

Ans : Adder, subtractor, differentiator, integrator fall under the category of linear circuits.
7. Explain what is an Adder or Summing Amplifier?

Ans : Adder or summing amplifier is a circuit that provides an output voltage proportional
to or equal to the algebraic sum of two or more input voltages multiplied by a
constant gain factor.
8. Explain what are the applications of an Integrator?

Ans : Integrators are widely used in ramp or sweep generators, filters, analog computers etc.

9. Op-amp is used mostly as an Integrator than as Differentiator. Explain Why?

Ans : Op-amp is used mostly as an integrator than a differentiator because in differentiator
at high frequency, gain is high and so high-frequency noise is also amplified which
absolutely abstract the differentiated signal.
10. Define differentiator.

Ans : A Differentiator is a circuit that is designed such that the output of the circuit is
proportional to the time derivative of the input.
11. What are the problems in an ordinary op-amp differentiator? What are the changes in
the circuit of the practical differentiator to eliminate these problems?
Ans : Problems in an Ordinary op-amp differentiator are instability and high frequency noise.
A Resistor is added in series with the capacitor at the input and a capacitor is added in
parallel to the resistor in the feedback circuit in the practical differentiator to eliminate
the above problems.
12. What are the problems in an ordinary op-amp Integrator? What are the changes in the
circuit of a practical integrator?
Ans : The gain of an integrator at low frequency is very high and the circuit goes to
saturation. The feedback capacitor is shunted with a resistor in the practical integrator
to overcome the above problem.
13. What is a lossy integrator?

Ans: The practical integrator is known as lossy integrator.

EXPERIMENT No- 4: R-2R LADDER NETWORK
Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input
from toggle switches and (ii) by generating digital inputs using mod-16 counter.
Aim: To design and test a 4 bit R-2R DAC using Op-amp with 4 bit binary input from toggle
switches and by generating digital inputs using mod-16 counter.
Components Required:
1. IC - µA 741 – 1 Nos.
2. Resisters (Carbon, ¼ W, 10%) –9Nos. (To be designed)
Equipments Required:
1. Spring Board/Bread Board – 1 No.
2. Dual Power Supply (0-30V, 2A, ±12V) – 1 No.
3Dual Channel CRO (20 MHz.) – 1 No.
4. Patch Cards / Wires5. Probes – 3 Nos.
Note : For IC µA 741 Pin diagram, refer appendix A
Theory:
Nowadays digital systems are used in many applications because of their increasingly efficient,
reliable and economical operation. Since digital systems such as microcomputers use a binary
system of ones and zeros, the data to be put into the microcomputer have to be converted from
analog form to digital form. The circuit that performs this conversion and reverse conversion
are called A/D and D/A converters respectively. D/A converter in its simplest form uses an op-
amp and resistors either in the binary weighted form or R-2R form.It is so called as the resistors
used here are R and 2R. The binary inputs are simulated byswitches b0 to b3 and the output is
proportional to the binary inputs. Binary inputs are either in high (+5V) or low (0V) state. The
analysis can be carried out with the help of Thevenin’s theorem. DAC (digital to analog
converter) converts digital input to its equivalent analog output voltage.
There are two types of DAC:
1. Binary weighted DAC
2. R-2R ladder type DAC.

In binary weighted DAC, say for N-bit DAC requires (N+1) number of resistor. Hence it is
different to obtain all the standard resistor values. Accuracy is poor. Therefore R-2R ladder
network DAC is designed were it uses only R and 2R (two resistance values).
Pin Details :
Typical Circuit Diagram :
a) Using toggle switch
1. Using mod-16 counter

Design Procedure:
 RF   b3
b1 b0  b2
V =- 
O  Vref   4  8  16 
 R  2 
Assume RF = 2 K, R = 1K and Vref = 5V.
 2K   b3 b2 b1 b0 
VO = -  (5)    
    
 1K  2 4 8 16 

  b3 b2 b0 
VO = 10   b1  
2 4 8 16 

Example: (1). b3, b2, b1, b0 = 0001
VO = - 0.6625V (2). b3, b2, b1, b0 = 0010,VO = - 1.329V
Tabular Column:
Decimal Digital Input Theoretical Practical Value

Equivalent b3 b2 b1 b0 Value Case (a)
0 0 0 0 0 0
1 0 0 0 1 - 0.625
2 0 0 1 0 -1.25
3 0 0 1 1 -1.875
4 0 1 0 0 -2.5
5 0 1 0 1 -3.125
6 0 1 1 0 -3.75
7 0 1 1 1 -4.375
8 1 0 0 0 -5.0

9 1 0 0 1 -5.625
10 1 0 1 0 -6.25
11 1 0 1 1 -6.875
12 1 1 0 0 -7.5
13 1 1 0 1 -8.125
14 1 1 1 0 -8.75
15 1 1 1 1 -9.375
Procedure:
a. Make connections as shown in the circuit diagram.
b. Vary the digital input from 0000 to 1111and note down the output of the op-
amp in each case. Tabulate the readings in the tabular column.
c. Apply the clock pulse of 5v 1KHz input from function generator to count digital
input from 0000 to 1111 using mod-16 counter and observe the output
waveform on CRO

Result :
4-Bit -R-2R ladder DAC using op-amp is designed and verified the output on multi-meter and
on CRO with binary input from toggle switches and from IC 7493 respectively.
1. What is DAC
Ans : Digital to Analog Converter (DAC) is a device that transforms digital data into an analog
signal. According to the Nyquist-Shannon sampling theorem, any sampled data can be
reconstructed perfectly with bandwidth and Nyquist criteria. A DAC can reconstruct
sampled data into an analog signal with precision. The digital data may be produced
from a microprocessor, Application Specific Integrated Circuit (ASIC), or Field
Programmable Gate Array (FPGA), but ultimately the data requires the conversion to
an analog signal in order to interact with the real world.
2. What is the drawback of weighted resistor method in DAC?

Ans : As the number of bits is increasing in the digital input voltage, the range of the resistor
values becomes large and accordingly, the accuracy becomes poor.
3. What are the applications of DAC?

Ans : DACs are used in many digital signal processing applications

 Audio Amplifier
 Video Encoder
 Display Electronics
 Data Acquisition Systems
 Calibration
 Motor Control
 Data Distribution System
 Digital Potentiometer
 Software Radio
4. What is meant by linearity?

Ans : The linearity of an ADC/DAC is an important measure of its accuracy & tells us how close the
converter output is to its ideal transfer characteristics.
5. What is monotonic DAC?

Ans : A monotonic DAC is one whose analog output increases for an increase in digital input.
6. What is a sample and hold circuit? Where it is used?

Ans : which samples an input signal and holds on to its last sampled value until the input is sampled again.
This is mainly used in analog to digital conversion
7. Explain the various types of digital to analog converters\

 Weighted resistor DAC
 R2R ladder DAC
 Inverted R2R ladder DAC

Experiment No. 5 Adder,Subtractor& Function Realization
Aim:Design and implement
(a) Half Adder & Full Adder using (i) basic logic gates and (ii) NAND gates.
(b) Half subtractor& Full subtractor using (i) basic logic gates and (ii) NANAD gates.
(c) 4-variable function using IC74151(8:1MUX)
Particulars Quantity
IC 7408, 7432, 7486 ,7404, 74151 01 each
IC7400 03
Half Adder:
Logic Diagram: Using Logic Gates Truth Table
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
𝑆 = 𝐴⨁𝐵
𝐶 = 𝐴. 𝐵
𝑆𝑈𝑀 = 𝐴𝐵 + 𝐴𝐵
𝐶𝐴𝑅𝑅𝑌 = 𝐴. 𝐵
Logic Diagram: Using NAND Gates

Full Adder:
Truth Table
Inputs Outputs
A B C Sum (S) Carry Out (Co)

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Design:
SUM
S = A𝐵̅𝐶̅ +𝐴̅𝐵̅C+𝐴̅B𝐶̅ +ABC S
= 𝐶̅ (A𝐵̅+𝐴̅B)+C(𝐴̅𝐵̅+AB) S =
𝐶̅ (AB)+C(̅𝐴̅
𝐵̅)
S=A  (BC)
CARRY
Co=𝐴̅BC+A𝐵̅C+AB𝐶̅ +ABC
Co=AB(C+𝐶̅) + C(AB)
Co=AB+ C(AB)
Full adder using basic logic gates

Full adder using NAND gates
Half Substractor
Block Diagram:
Logic Diagram: Using Logic Gates Truth Table
A
SUM A B DIFF. BORROW
B
0 0 0 0
0 1 1 1
CARRY
1 0 1 0
1 1 0 0

Logic Diagram: Using NAND Gates
FULL Substractor
Truth Table
Inputs Outputs
A B C Diff (D) Borrow(Bo)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

DIFFERENCE BORROW:
D = A𝐵̅𝐶̅+𝐴̅𝐵̅C+𝐴̅B𝐶̅ +ABC D Bo = 𝐴̅𝐵̅C+𝐴̅B𝐶̅ +𝐴̅BC+ABC
= 𝐶̅ (A𝐵̅+𝐴̅B)+C(𝐴̅𝐵̅+AB) D = Bo = 𝐴̅B(C+𝐶̅ )+C̅(̅𝐴̅
̅𝐵
)
̅
𝐶̅ (AB) +C(𝐴𝐵̅)
Bo=𝐴̅B + C̅(̅𝐴̅
̅𝐵
)
D = A  (BC)

Full Substractor using NAND gates:
Procedure
1. Place the IC in the socket of the trainer kit.

2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to the truth table.
4. Note down the output readings for full adder and full Substractor sum/difference and
the carry/borrow bit for different combinations of inputs.
(C) 4 -variable function using IC 74151(8:1MUX).

Pin configuration

4 D0 Y 5
3 D1 outputs
2 D2 ~W 6
Data 1 D3
15 D4
Inputs 14 D5 Vcc 16
13 D6
12 D7
Select 11 A GND 8
10 B
lines 9 C
7 ~G
74151N
Truth Table
Enable input Select Inputs Outputs

G A B C Y W
1 X x X 0 1
0 0 0 0 D0 ̅𝐷̅0̅
0 0 0 1 D1 ̅𝐷̅1̅
0 0 1 0 D2 ̅𝐷̅2̅
0 0 1 1 D3 ̅𝐷̅3̅
0 1 0 0 D4 ̅𝐷̅4̅
0 1 0 1 D5 ̅𝐷̅5̅
0 1 1 0 D6 ̅𝐷̅6̅
0 1 1 1 D7 ̅𝐷̅7̅
a) Realize the given function F= f(A,B,C,D) =∑(1,2,4,5,7,9,11,13,15) using IC

74151(8:1 MUX)
Logic diagram:

VCC
VCC 5.0V
5.0V U1
A
4 D0 16
3 VCC
D1
2 D2 5
Y
B 1 D3
15 D4 ~W 6
14 D5
13 D6
C 12 D7
11 A
10 B
9 C
D 7 ~G
8 GND
7432
74LS VCC Y
U1251D
5.0V
4 D0 16 OR2
3 VCC
D1
2 D2 5
1 Y
D3
15 D4 ~W 6 = f(A,B,C,D) =∑(1,2,4,5,7,9,11,13,15)
14 D5
13 D6
12 D7
11 A
10 B
7404 9 C
7
~G
8 GND
NOT 74LS151D
Truth Table:
Select Inputs Output
D C B A Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Procedure:
1. The IC is fixed on the IC zip socket and VCC &GND connections are given from 5V

Supply.
2. Connections are made as shown in the Logic diagram.

3. All the inputs are connected to the switches & output to the LEDs.
4. Truth table is verified for different combinations of input.
Result: ……………………………………………………………………………………
Staff Signature
VIVA Question
1. Define half adder and full adder?
2. Define halfSubstractor and fullSubstractor?
3. Explain the different types of canonical form with example?
4. Define prime implicants and essential prime implicants?
5. Find the prime and essential prime implicants from the switching equation?
6. D=f(W,X,Y,Z)=m(5,7,8,9,13) b). U=f(W,X,Y,Z)=m(1,5,7,8,9,10,11,13,15)
7. Explain incompletely specified functions(Don’t care terms)?
8. Explain Combinational and Sequential circuits?
9. What is the difference between Adder and Substractor?
10. Applications of Adders and Substractor
11. What is multiplexer?
12. Give the applications of multiplexer?
13. What are the advantages of multiplexer?
14. Give the design of 8X1 multiplexer using 2X1 multiplexers?
15. What is difference between decoder and multiplexer?
Experiment No. 6 Code Conversions: Binary Vs Gray& BCD Vs Excess-3
Aim: Realize (i) Binary to Gray code conversion & vice-versa (IC74139)
(ii) BCD to Excess-3 code conversion and vice versa

IC 74139, 7483 01 each
Truth Table: Binary to Gray
X (A,B,C)= ∑m (4,5,6,7) Y (A,B,C)= ∑m (2,3,4,5) Z (A,B,C)= ∑m (1,2,5,6)
Logic diagram:
= ∑m (4,5,6,7)
= ∑m (2,3,4,5)
= ∑m (1,2,5,6)
i) Realize GREY TO BINARY CODE conversion using decoder 74139

x(A,B,C)= ∑m (1,3,5,7) y(A,B,C)= ∑m (1,2,5,6) z(A,B,C)= ∑m (1,2,4,7)
Logic diagram:
= ∑m (1,3,5,7)
= ∑m (1,2,5,6)
= ∑m (1,2,4,7)
Procedure:
1. The IC is fixed on the IC zip socket and VCC &GND connections are given from 5V
Supply.
3. All the inputs are connected to the switches & output to the LEDs.
4. Truth table is verified for different combinations of input.
ii) BCD To Excess-3 Code Conversion and Vise Versa Using IC 7483

Theory:
Code converter is a combinational circuit that translates the input code word into a new
corresponding word. The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD code
to the 4- bit adder as the first operand and then feed constant 3 as the second operand. The
output is the corresponding excess-3 code.
To make it work as an excess-3 to BCD converter, we feed excess-3 code as the first operand
and then feed 2's complement of 3 as the second operand. The output is the BCD code.
Truth Table
BCD (8421) Excess-3

A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X

Pin Diagram:
Logic Diagram:
Note: Keep the input (B3,B2,B1,B0=0011) constant and Cin=0

To realize EXCESS-3 CODE to BCD conversion
Excess-3 BCD (8421)
W X Y Z A B C D
0 0 0 0 X X X X
0 0 0 1 X X X X
0 0 1 0 X X X X
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X
Logic Diagram:
Note: Keep the input (B3,B2,B1,B0=0011) constant and Cin=1

Procedure
1. The IC is fixed on the IC base board and VCC & GND connections are given from
5V supply.
3. The truth table is verified for different combinations of input.
Result: …………………………………………………………………………………...
Staff Signature
VIVA Question
1. Explain how MEV map differs from K-map?

2. Explain the terms.
3. a) Arithmetic logic unit (ALU) b) Array multiplier c) BCD adder
d)Comparator
4. Draw and explain the block diagram of n-bit parallel adder?
5. What do you mean by carry propagation delay?
6. Define clock skew, negative clock skew, positive clock skew?
7. Explain the method used for carry look ahead generation

Experiment No.7 Flip Flop & Shift Registers

Aim:Realize
a) Realize using NAND GatesMaster-Slave JK Flip-Flop, D Flip-Flop and T Flip-Flop

using NAND Gates
b) Realize the shift registers using IC7474/7495 (i) SISO (ii) SIPO (iii) PISO (iv) PIPO
(v) Ring counter and (vi) Johnson counter.
Sl.No Particulars Quantity
01 IC 7410 2 No
02 IC 7400 1 No
Logic symbol of Flip flops:
(a) Master Slave JK Flip flop using NAND gates
Truth Table:

Logic Diagram:
Note:
Case 1: Asynchronous:
1. In the absence of clock.

a) With preset = 0 and clear =1, the output is set.
b) With preset = 1 and clear = 0, the output is reset.
Case 2: Synchronous:
2. Both present and clear are made high.

3. All combination of inputs is applied at J & K.
(b) D-Flip flop using NAND gates
Truth table:
Inputs Output
Preset Clear D Clock Qn + 1 Qn + 1
1 1 0 0 1
1 1 1 1 0
Logic Diagram:

(a) T-Flip flop using NAND gates
Truth table:
Inputs Output
Preset Clear T Clock Qn + 1 Qn + 1
1 1 0 Qn Qn
1 1 1 Qn Qn
Logic Diagram:
Procedure:
1. Connections are made as shown in Logic diagram.

2. The Truth Tables of flip flops are verified for various combinations of inputs.
SHIFT REGISTERS
Aim: To realize
a) The following shift operations using IC 7474/7495.i) SISO ii) SIPO (Right shift)
iii) PISO iv)PIPO
b) The ring and Johnson counter using IC 7495

Components required:
IC 7495 1 No
IC 7404 1 No
Pin configuration of IC 7495
Truth Table:
Operating INPUT OUTPUT

mode Mode Clk2 Clk1 SDI PARALLEL QA QB QC QD
control (CP1) (CP2) (DS) INPUT (Pn)
(S) (A B C D)
SHIFT L X L X L qb qc qd
L X H X H qb qc qd
Parallel H X X Pn P0 P1 P2 P3
Load (1011) 1 0 1 1
a) Shift registers operations
 SDI: Serial data input(to be shifted)

 A,B,C,D: Parallel data inputs to be loaded into the shift register.
 Mode control (M)
Keep, M=1 for loading parallel data and to enable clock 2.
M=0 for enabling clock 1
 Clk 2: For loading parallel input data and for shift left of data.
 Clk 1: For right shift of data.
 QA, QB, QC and QD: Parallel outputs of the shift register.

i) Serial In Serial Out (SISO)

Tabular Column
Inputs Outputs
Clock Serial i/p QA QB QC QD
1 d0=0 0 X X X
2 d1=1 1 0 X X
3 d2=1 1 1 0 X
4 d3=1 1 1 1 0=d0
5 X X 1 1 1=d1
6 X X X 1 1=d2
7 X X X X 1=d3
Procedure:
1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply another clock pulse; the second data ‘d1’ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD. Thus the data
applied serially at the input comes out serially at QD.
ii) Serial In Parallel Out SIPO (Right Shift)

Tabular Column
Inputs Outputs
Clock Serial i/p QA QB QC QD
1 d0=0 0 X X X
2 d1=1 1 0 X X
3 d2=1 1 1 0 X
4 d3=1 d0=1 d1=1 d2=1 d3=0

Procedure:

2. Apply the data at serial i/p
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new
data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift register.
(iii) Parallel In Serial Out (PISO)
Tabular Column
Mode Clk Parallel i/p Serial o/p
A B C D Q QB Q QD
A C
1 1 1 0 1 1 1 0 1 1=d0
0 2 X X X X X 1 0 1=d1
0 3 X X X X X X 1 0=d2
0 4 X X X X X X X 1=d3
Note: Mode M = 1 for Parallel
loading.
Mode M = 0 for serial shifting.
Procedure:

2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied atA, B, C
and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the data
coming out serially at QD.

(iv) Parallel In Parallel Out (PIPO)
Tabular Column
Inputs Outputs
Cloc Parallel i/p Parallel o/p

k
A B C D Q QB QC QD
A
1 1 0 1 1 1 0 1 1
Procedure: -
2. Apply the 4bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively
V) Ring counter using IC 7495 Counting sequence

Vi) Johnson counter using IC 7495 Counting sequence
Procedure: -
1. Connections are made as per the circuit diagram.

2. Apply the data 1000 at A, B, C and D respectively.
3. Keeping the mode M = 1, apply one clock pulse.
4. Now the mode M is made 0 and clock pulses are applied one by one and the truth table is
verified.
5. Above procedure is repeated for Johnson counter also.
Result:
Staff Signature

VIVA Question
1. Give the difference between latches and flip-flops?
2. Draw and explain the working of
a) SR flip-flop, b) Gated SR flip-flop, c)Gated D latch
3. Explain any one application of SR latch?
4. Draw the logic diagram, construct the excitation table and write the characteristic
equations for the following flip-flop?
a) SR flip-flop, b) JK flip-flop, c) T or Toggle flip-flop, d) D or Delay flip-flop
5. What is race around condition? How it is avoided?
6. Explain the advantage of JK flip-flop over SR flip-flop?
7. Sketch the logic diagram of a master-slave flip-flop?.Explain its operation and
features?
8. What is the function of shift register
9. What is shift left register?
10. How does a Johnson counter work?
11. What is shift register application?
12. Explain the different types of triggering?
13. What do you mean by sequential circuits?
14. Give the comparison between combinational and sequential circuits?
15. Give the comparison between synchronous and asynchronous circuits?
16. Draw and explain the working of basic bistable element?

Experiment No.8: COUNTERS
Aim:Realize
i) Design MOD- N synchronous UP counter and DOWN Counter Using 7476 JK Flip-flop
ii) Mod N Asynchronous counter using IC7490 and
(iii) Mod-N Synchronous counter using IC74192
Components required:
Sl.No Particulars Quantity
01 IC 7490 1
02 IC 74192 1
03 IC 7476,7404 1 Each
i) Design MOD- N synchronous UP counter and DOWN Counter using 7476 JK Flip-flop
Pin diagram of 7476

3 bit/ Mod 8 Synchronous Up counter for the given sequence using IC 7476.
Given State Diagram

000
111 001
110 010
101 011
Design: 100
State Table
Clock QC QB QA
0 0 0 0 State Change J-K Input
1 0 0 1 Qn Qn+1 J K
2 0 1 0
3 0 1 1 0 0 0 X
4 1 0 0 0 1 1 X
5 1 0 1 1 0 X 1
6 1 1 0
1 1 X 0
7 1 1 1
Transition Table
Present State Next State Flip flop Inputs

FF-2 FF-1 FF-0
QB QA QC QB QA JC KC JB KB JA KA
QC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1

Logic Diagram for 3-bit Synchronous up counter using discrete components:

ii) Asynchronous counter using IC7490
Internal Diagram of 7490:
Function Table:
Clock MR1 MR2 MS1 MS2 Q3 Q2 Q1 Q0 Remarks
X 1 1 0 X 0 0 0 0 Reset
X 1 1 X 0 0 0 0 0 Reset
X X X 1 1 1 0 0 1 Set to 9
X 0 X 0 Count
0 X 0 X Count
0 X X 0 Count
X 0 0 X Count

Truth Table of Mod-10 Counter:
Clock Q3 Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0
Timing diagram of Mod 10 Counter:
b. Mod 8 Counter using 7490:
Q0 Q1 Q2 Q3
12 9 8 11
CP1 Mod 5
Mod 2
Clock I/P 14
CP2 2 3 6 7
MR1 MR2 MS1 MS2

Truth Table for Mod 8 Counter:
Inputs Outputs
Clock Q3 Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
th
At the 8 clock pulse reset the counter
Timing diagram of Mod-8 counter:
i) Synchronous counter using IC74192
Pin Configuration:
15 3
parallel 1
2 outputs
10 6
inputs
9 7
11 13
14 12
Clock 5 16
4
input 8
74192N

Upcounter
Downcounter
outputs parallel
15 A QA 3
1 B QB 2
10 6 outputs
inputs C QC
9 D QD 7
~LOAD ~BO 13
logic 1 11 CLR ~CO 12
14 Vcc 16
logic 0 UP
5 DOWN GND 8
4
clk i/p clk i/p

74192N 74192N
Function table:
Clr Load UP(CU) Down(CD) Mode

1 X X X Reset
0 0 X X Preset
0 1 1 1 No change
Clock i/p
0 1 1 Count up
(L-H)
Clock i/p
0 1 1 Count down
(L-H)
Truth table:
Input(clock) Up counter Down counter

(CU / CD)
QD QC QB QA QD QC QB QA
0 0 0 0 0 1 0 0 1
1 0 0 0 1 1 0 0 0
2 0 0 1 0 0 1 1 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 0 1
5 0 1 0 1 0 1 0 0
6 0 1 1 0 0 0 1 1
7 0 1 1 1 0 0 1 0
8 1 0 0 0 0 0 0 1

9 1 0 0 1 0 0 0 0

Procedure:
1. Connections are made as shown in Logic diagram.

2. Verify the function table
3. Verify the truth table of logic circuit of up/down counter by applying respective clock
pulses.
Result: …………………………………………………………………………………….
Staff Signature
VIVA Question:
1. What is counter?
2. What is ring counter?
3. What are synchronous counters?
4. How many Flip-Flops are required for mod–16 counter?
5. Difference between synchronous and asynchronous?
6. Explain the working of 4 bit synchronous counter?
7. Explain the working of 4 bit asynchronous counter?
8. What is advantages and disadvantages of counter?
9. What is difference between synchronous counter and asynchronous counter?
10. Why counter is called as clock divider? Explain?
11. Design a BCD counter with JK flip-flops?
12. Design a counter with the following binary sequence 0,1,9,3,2,8,4 and repeat? Use T
flip-flops?
13. Design a counter with the following binary sequence 0,1,9,3,2,8,4 and repeat? Use JK
flip-flops?
14. Design a counter which counts 1 to 10 using flip-flops.
15. Define Metastablity?

Demonstration Experiments
EXPERIMENT No- 09 :
A. SECOND ORDER ACTIVE LOW PASS FILTER
AIM: To design a Second Order Active Low Pass filter for cut off frequency fc= 1KHz and
to draw the frequency response and verify the Roll-off factor.
Sl.
COMPONENTS RANGES QUANTITY
No.
1 Resistors 27K 1
15K 3
1K 2
10K 1
2 Capacitors 0.01µF 2
3 0pAmp uA41 1
BRIEF THEORY:
A low pass filter has a constant gain from 0 Hz to a high cutoff frequency fc. Therefore band
width is also fc. At fc the gain is down by 3 dB. After that ( f>fc) it decreases with the increase
in input frequency . The key characteristic of the Butterworth filter is that it has a flatpass band
as well as stop band. The rate at which the gain of the filter changes in the stop band is
determined by the order of the filter. For the first order low pass filter the gain rolls off at the
rate of 20dB/decade in the stop band, that is f >fc on the other hand, for the second order low
pass filter the roll off rate is 40dB/decade and so on.
CIRCUIT DIAGRAM:

DESIGN:
MODEL GRAPH:

TABULAR COLUMN:
Input voltage = Vin (p-p) =
Sl.No Frequency in KHz Output Voltage Vo (p-p) Voltage Gain Gain in dB
Av = Vo / Vi Av in (dB)
=20log (Av )
PROCEDURE:
1. Rig up the circuit as shown in the figure.
2. Apply sine wave i/p signal of amplitude 1Vp-p from signal generator.
3.Vary the input signal frequency from 10 Hz to 10KHz in the steps of 100Hz and
corresponding output voltage is noted.
4. Results are tabulated and gain in dB are calculated.
5. Graph of frequency v/s gain in dB is plotted.
To find the Roll-off factor:
1. Keeping the i/p signal amplitude constant, adjust the i/p frequency at 10fc note
down o/p signal amplitude.
2. The difference in the gain of the filter at fc and 10fc gives the Roll-Off factor

RESULT:
Cut-off frequency of 2ndorder LPF =
Roll- off factor of 2ndorder LPF =
B. SECOND ORDER ACTIVE HIGH PASS FILTER
AIM: To design a second order active High Pass filter for cut off frequency fc =1KHz and to
draw the frequency response &verify the Roll- off factor.
Sl.
COMPONENTS RANGES QUANTITY
No.
1 Resistors 27K 1
15K 3
1K 2
10K 1
2 Capacitors 0.01µF 2
3 0pAmp uA41 1
BRIEF THEORY:
A high pass tiller has n constant gainabove cut off frequency fc where as range of frequencies
those below fc, are attenuated. Therefore a high pass filter has stop band 0<f>fc and a pass
band f>fc. fc is the cut off frequency, and f is the operating frequency.
CIRCUIT DIAGRAM:

DESIGN:
MODEL GRAPH:

TABULAR COLUMN:
Input voltage = Vin (p-p) =
Sl.No Frequency in KHz Output Voltage Vo (p-p) Voltage Gain Gain in dB
Av = Vo / Vi Av in (dB)
=20log (Av )

PROCEDURE:
1. Rig up the circuit as shown in the figure.
2. Apply sine wave i/p signal of amplitude 1Vp-p from signal generator.
3.Vary the input signal frequency from 10 Hz to 10KHz in the steps of 100Hz and
corresponding output voltage is noted.
4. Results are tabulated and gain in dB are calculated.
5. Graph of frequency v/s gain in dB is plotted.
6. Verify the Roll-off factor from the graph.
To find the Roll-off factor:
1. Keeping the i/p signal amplitude constant, adjust the i/p frequency at 10fc note
down o/p signal amplitude.
2. The difference in the gain of the filter at fc and 10fc gives the Roll-Off factor
RESULT:-
i. Cut-off frequency of 2nd order HPF=

ii. Roll- off factor of 2ndorder HPF=
VIVA QUESTIONS
1. Define low pass filter
A low-pass filter is a filter that passes low-frequencysignals but attenuates (reduces the
amplitude of) signals with frequencies higher than the cutoff frequency. The actual amount
of attenuation for each frequency varies from filter to filter.
The concept of a low-pass filter exists in many different forms, including electronic circuits
(like a hiss filter used in audio), digital algorithms for smoothing sets of data, acoustic
barriers, blurring of images, and so on. Low-pass filters play the same role in signal
processing that moving averages do in some other fields, such as finance; both tools
provide a smoother form of a signal which removes the short-term oscillations, leaving only
the long-term trend.
2. What are the functions of low pass filters?
An ideal low-pass filter completely eliminates all frequencies above the cutoff frequency while
passing those below unchanged: its frequency response is a rectangular function, and is a brick-
wall filter.
3. Where is the electronic low pass filters used?
Electronic low-pass filters are used to drive subwoofers and other types of loudspeakers, to
block high pitches that they can't efficiently broadcast.
4. Why do radio transmitters use low pass filters?
Radio transmitters use low-pass filters to block harmonic emissions which might cause
interference with other communications.

5. What is use of low pass filters in Guitars?

The tone knob found on many electric guitars is a low-pass filter used to reduce the amount of
treble in the sound.
6. What is a first order filter?
A first-order filter, for example, will reduce the signal amplitude by half (so power reduces by
6 dB) every time the frequency doubles (goes up one octave); more precisely, the power rolloff
approaches 20 dB per decade in the limit of high frequency.
7. What is a second order filter?
Second-order filter attenuates higher frequencies more steeply. The Bode plot for this type of
filter resembles that of a first-order filter, except that it falls off more quickly.
8. What is a high pass filter?
A high-pass filter, or HPF, is an LTIfilter that passes high frequencies well but attenuates (i.e.,
reduces the amplitude of) frequencies lower than the filter's cutoff frequency. The actualamount
of attenuation for each frequency is a design parameter of the filter. It is sometimes called a
low-cut filter or bass-cut filter.
9. What are applications of high pass filters in communication?
They are used as part of an audio crossover to direct high frequencies to a tweeter while
attenuating bass signals which could interfere with, or damage, the speaker. High-pass filters
are also used for AC coupling at the inputs of many audio amplifiers, for preventing the
amplification of DC currents which may harm the amplifier, rob the amplifier of headroom,
and generate waste heat at the loudspeakersvoice coil
10. How do LPF and HPF help for image processing?
High-pass and low-pass filters are also used in digital image processing to perform
transformations in the spatial frequency domain.
11. Define a band pass filter?
A band-pass filter is a device that passes frequencies within a certain range and rejects
(attenuates) frequencies outside that range.
12. Define bandwidth.
The bandwidth of the filter is simply the difference between the upper and lower cutoff
frequencies.
13. What is roll off factor?
The filter does not attenuate all frequencies outside the desired frequency range completely;
in particular, there is a region just outside the intended passband where frequencies are
attenuated, but not rejected. This is known as the filter roll-off, and it is usually expressed in
dB of attenuation per octave or decade of frequency.
14. What are active filter?
An active filter is a type of analogelectronic filter, distinguished by the use of one or more
active components i.e. voltage amplifiers or buffer amplifiers.
15. What are the advantages of active filters over passive filters?
Active filters have three main advantages over passive filters:
 Inductors can be avoided. Passive filters without inductors cannot obtain a high Q (low
damping), but with them are often large and expensive (at low frequencies), mayhave
significant internal resistance, and may pick up surrounding electromagnetic signals.
 The shape of the response, the Q (Quality factor), and the tuned frequency can often
be set easily by varying resistors, in some filters one parameter can be adjusted without
affecting the others. Variable inductances for low frequency filters are not practical.

 The amplifier powering the filter can be used to buffer the filter from the electronic
components it drives or is fed from, variations in which could otherwise significantly
affect the shape of the frequency response
16. What are passive filters?
Passive implementations of linear filters are based on combinations of resistors (R), inductors
(L) and capacitors (C). These types are collectively known as passive filters, because they do
not depend upon an external power supply and/or they do not contain active components such
as transistors.
17. What is the role of inductor, capacitor and resistor in a filter?
Inductors block high-frequency signals and conduct low-frequency signals, while capacitors
do the reverse. A filter in which the signal passes through an inductor, or in which a capacitor
provides a path to ground, presents less attenuation to low-frequency signals than high-
frequency signals and is a low-pass filter. If the signal passes through a capacitor, or has a path
to ground through an inductor, then the filter presents less attenuation to high-frequency signals
than low-frequency signals and is a high-pass filter. Resistors on their own have no frequency-
selective properties, but are added to inductors and capacitors to determine the time-constants
of the circuit, and therefore the frequencies to which it responds.
The inductors and capacitors are the reactive elements of the filter. The number of elements
determines the order of the filter. In this context, an LC tuned circuit being used in a band- pass
or band-stop filter is considered a single element even though it consists of two components.

EXPERIMENT No- 10 :
A.MONOSTABLE MULTIVIBRATOR USING IC 555 TIMER
Design and test Monostable and astable Multivibrator using 555 Timer.
AIM: Design and test Monostable multi-vibrator using IC 555 timer.
THEORY : A Monostable Multivibrator, often called a one-shot Multivibrator, is a

pulsegeneratingcircuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable or stand by mode the output of the circuit is
approximately Zero or at logic-low level. When an external trigger pulse is obtained, the
output is forced to go high (  VCC). The time for which the output remains high is
determined by the external RC network connected to the timer. At the end of the timing
interval, the output automatically reverts back to its logic-low stable state. The output stays
low until the trigger pulse is again applied. Then the cycle repeats. The Monostable circuit
has only one stable state (output low), hence the name monostable. Normally the output of
the Monostable Multivibrator is low.

CIRCUIT DIAGRAM:-
DESIGN:
Consider VCC = 5V, for given tp

Output pulse width tp= 1.1 RA C
Assume C in the order of microfarads & Find RA
Typical values:
If C=0.1 μF , RA = 10k then tp= 1.1 ms
Trigger Voltage =4 V

PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.

2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
3. Observe the output waveform and measure the pulse duration.
4. Theoretically calculate the pulse duration as Thigh=1.1. RAC
5. Compare it with experimental values.
RESULT:
The Monostable multivibrator was designed and output was tested using IC 555 Timer.

EXPERIMENT No-10 :
B. ASTABLE MULTIVIBRATOR USING IC 555 TIMER
AIM:
Design an Astable multi-vibrator using IC 555 timer to generate a clock signal of :
1. Frequency 1 KHz with 0.75 duty cycle (unsymmetrical) and
2. Frequency 1 KHz with 0.50 duty cycle (symmetrical)
COMPONENTS REQUIRED: Resistors [16.8 KΩ and 3.3 KΩ], connecting wire,
Capacitors [0.1 μf and 0.01 μf], 555 timer, power supply and CRO.
THEORY : An Astable multi-vibrator, often called a free running multi-vibrator, is a
rectangular-wave generating circuit. Unlike the Monostable multi-vibrator, this circuit does not
require an external trigger to change the state of the output, hence the name free running.
However the time during which the output is either high or low is determined by the two
resistors and a capacitors which are connected externally.
PROCEDURE:
 Verify all the components and patch-chords whether they are in good condition.
 Connect the Astable multi-vibrator circuit using IC 555 timer as like shown in fig.
 Switch on the DC power-supply unit Vcc=+12 v.
 Observe the output waveform at pin no. 3 on CRO.
 Measure the output pulse amplitude.
 Observe the capacitor voltage wave form at pin no.6 and measure the maximum and
minimum voltage levels. Verify that VUT=2/3 VCC and VLT=1/3 VCC
 Compare the capacitor voltage VC with output waveform VO and note that capacitor
charges and VC rises exponentially when output is high. The capacitor C discharges
through RB and discharges the transistor, and VC falls exponentially when output is low
 Calculate the Duty cycle‘d’, output frequency ‘f’ and verify.
[Note: Astable multi-vibrator using IC 555 timer to obtain output waveform with TH
< or =T L so that output cycle 50%.
1) To obtain above condition, circuit must be connected as like shown in fig. 2.
2) Four such circuit R=R1=R2
3) Suitable value must be selected for C
4) Duty cycle ‘d’=50% or ‘d’=0.5
 Verify whether the theoretical value is matching with practical values and observe the
outputs.

CIRCUIT OPERATION: Figure (a) shows the 555 timer connected as an astable vibration.
Initially when the output is high, capacitor C starts towards VCC through RA and Rg.However
as soon as voltage across the capacitor equals 2/3 VCC, comparator-1 triggers the flip-flop and
the output switches low. Now capacitor C starts discharging through RB and transistor Q1.
When the voltage across C equals 1/3 VCC comparator’s output triggers the flip-flop and output
goes high. Then the cycle repeats the output voltage and capacitor voltage waveform as shown
in fig (b).
The time during which the capacitor charges from 1/3 VCC is equal to the time the output
is high and is given by:
tc= 0.69 (R1 + R2 ) C
Similarly, the time during which the capacitor discharges from 2/3 VCC to 1/3 VCC is
equal to the time the output is low and is given by:
td=0.69 (R2) C
Thus the total period of the output waveform is
T=tC + td=0.69 (R1 + 2R2) C
The frequency of oscillation is given by:
F =1/T= 1.44 /(R1 + 2R2) C
Where RA and RB is in Ohms and C in Farads for in independent of supply voltage VCC
APPLICATION:
1) Generates square-wave oscillator
2) Free running ramp generator
PIN DIAGRAM:
555 Timer IC Block diagram:

DESIGN:
(a) Unsymmetrical astable multivibrator:
Given f=1KHz and Duty cycle=0.75
T=1ms, since f=1KHz
Tc=Ton=0.75ms and Td=Toff=0.25ms (Tc=Charging time and Td= Discharging time)
Tc= 0.69 (R1 + R2 ) C -------------- (1)

Td=0.69 (R2) C ---------------- (2)
Assume C=0.1µF
From eq(2)
0.25ms=0.69 (R2) 0.1µF
R2=0.25m/0.69* 0.1µF= 3.6KΩ approximately=3.3KΩ
Therefore R2=3.3KΩ
Substituting the value of RB in eq(1) we get 0.75m=0.69(R1+3.3KΩ)0.1µF =(0.69R1+
227.7)0.1µF
Solving we get R1= 6.8KΩ and R2=3.3KΩ
(b) Symmetrical astable multivibrator:
Given f=1KHz, Duty cycle=0.5

Ton+Toff=1ms, But Ton=0.69 (R1) C and Toff= 0.69 (R2) C
Let C=0.1µF, so 0.50ms= 0.69* R1 *0.1 µF
Therefore R1 = 7.2KΩ approximately=6.8KΩ, Similarly R2= 6.8KΩ
Therefore R1= R2= 6.8KΩ.

CIRCUIT DIAGRAM:
(a) Unsymmetrical astable multivibrator:
Symmetrical astable multivibrator:
PROCEDURE:
 Verify all the components and patch-chords whether they are in good condition.
 Connect the Astable multi-vibrator circuit using IC 555 timer as like shown in fig.
 Switch on the DC power-supply unit Vcc=+12 v.
 Observe the output waveform at pin no. 3 on CRO.
 Measure the output pulse amplitude.
 Observe the capacitor voltage wave form at pin no.6 and measure the maximum and
minimum voltage levels. Verify that VUT=2/3 VCC and VLT=1/3 VCC

 Compare the capacitor voltage VC with output waveform VO and note that capacitor
charges and VC rises exponentially when output is high. The capacitor C discharges
through RB and discharges the transistor, and VC falls exponentially when output is low
 Calculate the Duty cycle‘d’, output frequency ‘f’ and verify.
[Note: Astable multi-vibrator using IC 555 timer to obtain output waveform with TH
< or =T L so that output cycle 50%.
5) To obtain above condition, circuit must be connected as like shown in fig. 2.
6) Four such circuit R=RA=RB
7) Suitable value must be selected for C
8) Duty cycle ‘d’=50% or ‘d’=0.5
Verify whether the theoretical value is matching with practical values and observe the
outputs.
CALCULATIONS:
(b) Unsymmetrical astable multivibrator:
Ton = Tc =
Toff = Td =
Duty Cycle = Ton / (Ton +Toff) =
LTP = 1/3 Vcc =
UTP = 2/3Vcc =
(c) symmetrical astable multivibrator:
Ton = Tc =
Toff = Td =
Duty Cycle = Ton / (Ton +Toff) =
LTP = 1/3 Vcc =
UTP = 2/3Vcc =
RESULT:
Astable unsymmetrical and symmetrical multivibrators were designed and tested using IC
555 timer.


1. What is monostable multivibrator using 555 timer?
Ans :It has one stable state and it switches to unstable state for a predetermined time period
T when it is triggered. Monostable mode of 555 Timer is commonly used for generating
Pulse Width Modulated (PWM) waves.
2. Why is it called 555 timer?

Ans :555 is called so because of it's internal circuit. There are 'three' 5k ohm resistors used
in the IC and hence the name '555'. The resistors are connected in series and are used
as voltage dividers.
3. What is the output voltage of 555 timer?
Ans :The 555 timer can be used with a supply voltage (Vs) in the range 4.5V to 15V (18V
is the absolute maximum).
4. What does multivibrator mean?
Ans :A multivibrator is an electronic circuit used to implement a variety of simple two-
state devices such as relaxation oscillators, timers and flip-flops. It consists of two
amplifying devices (transistors, vacuum tubes or other devices) cross-coupled by
resistors or capacitors.
5. Why astable multivibrator is called astable?

Ans :An astable multivibrator is also known as a free running multivibrator. Itis
called free-running because it alternates between two different output voltage levels.
The output remains at each voltage level for a definite period of time.
6. What are the applications of 555 timers in monostable mode?

Ans :Missing pulse detector, Frequency divider, Pulse width modulation etc.
7. . Write down the expression for output pulse width in monostable mode?
Ans :T = 1.1R1C1
8. Why the number has come for 555 IC as 555?

Ans :It has three 5K Resistors at the input of the comparators to get 2/3 V cc and 1/3 Vcc,
hence the name came as 555.
9. Write down the expression for output pulse width in Astable mode?
Ans :T = 0.69(RA + 2RB)C , TON = 0.69(RA + RB)C, TOFF = 0.69RBC
10. What are the applications of 555 timers in Astable mode?

Ans :Square wave generator, FSK generator, pulse position modulator etc.
11. What is a quasi-stable state and what is a steady state?

Ans :A quasi stable state is also known as temporary state, where the output stays in this
state only for a fixed time and goes back to the stable state after that time period. A
stable state is a state where the output will be in that state until unless an external trigger
is given.

EXPERIMENT No-11:
Aim : To construct and verify the Power supply unit using Bridge rectifier, Capacitor
filter and IC 7805
Abstract:A rectifier is an electrical device that converts alternating current (AC)voltage or

current in to direct current (DC), voltage or current which flows in only one direction. The step
down transformer converts the AC mains supply of 230V to 12V AC. This 12V AC is applied
to the bridge rectifier arrangement such that the alternate diodes conduct for each half cycle
producing a pulsating DC voltage consisting of AC ripples. A capacitor connected across the
output allows the AC signal to pass through it and blocks the DC signal, thus acting as a high
pass filter. The output across the capacitor is thus an unregulated filtered DC signal. This output
can be used to drive electrical components like relays, motors, etc.
Components required: Step down tranformer(0-12V),capacitor 0.22µF, capacitor 0.1 µF,

capacitor 1000 µF, Diodes IN 4007,7805voltage regulator
Circuit Diagram:

Waveform:
Input waveform observed
Waveform observed across capacitor
Output Waveform
Procedure:
1. Connect the circuit as shown in the circuit diagram

2. Switch on the power
3. Observe the waveform across the Rectifier (A),capacitor filter (B) and Regulator (C)
4. Plot the waveforms using graph sheet.

Observation :
A step down transformer converts 230V AC to 12V AC,bridge rectifier converts AC into
pulsating DC.A capacitor filter circuit removes the AC ripples. IC 7805 voltage regulator is
used to get regulated DC voltage of 5 V
Result:

EXPERIMENT No-12
Aim :To Operate a small loud speaker by generating oscillator using IC 555
Abstract: Astable Multivibrator using a 555 timer IC generates a continuous square wave
output. The circuit has an oscillation frequency about 670-680 HZ. The audio frequency of the
circuit can be changed to wide ranges by varying the values of any of the resistance R1, R2 or
the capacitance C1. Potentiometer is usedfor frequencytuning &the loudspeaker is usedwith a
appropriate impedance and power. A tone generator circuit can be used for various applications
such as alarms, bells, indicators etc
Components required:555 Timer IC, Speaker, Resistors - 1kohm, 10kpot, 10kohm,
Capacitors - 10µF, 0.01nF(2)
Circuit Diagram:
Procedure:
1. Connect the circuit as shown in the circuit diagram

2. Switch on the power
3. Vary the potientiometer value to hear the changes in intensity of sound
4. Observe the intensity of sound across output (pin no 3)
Observation : A low power audio signal can be amplified using 555 Timer IC
Result:

APPENDIX
PIN CONFIGURATION OF ICS




COURSE EXIT SURVEY:2023-24
Student Name: USN:
Semester: III Subject Name: Analog and Digital Systems Design Lab
Subject Code: BECL305
Faculty Members Name:
Dear Student,
Congratulations for completing this course / subject. Please provide your prompt
opinion on the potentiality of the course in terms of knowledge gained by you .
Please rate attainment level appropriately as applicable in the below Form.
Attainment Level: 1 to 5 (1-Poor, 2-Satisfactory, 3-Good, 4-Very Good and 5-Excellent)
Sl. CO Level of
Description PO Mapped
No. Mapped attainment
Design and analyze the PO1,PO2,PO3,PO4,PO9,PO10,PSO1,PSO2
1 CO1 BJT/FET amplifier and
oscillator circuits.
Design and test Opamp PO1,PO2,PO3,PO4,PO9,PO10,PSO1,PSO2
circuits to realize the
2 CO2 mathematical computations,
DAC and precision
rectifiers.
Design and test the PO1,PO2,PO3,PO4,PO9,PO10,PSO1,PSO2
3 CO3 combinational logic circuits
for the given specifications.
Test the sequential logic PO1,PO2,PO3,PO4,PO9,PO10,PSO1,PSO2

4 CO4 circuits for the given
functionality.
Demonstrate the basic PO1,PO2,PO3,PO4,PO9,PO10,PSO1,PSO2
5 CO5 circuit experiments using
555 timer.
Signature of Student

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Department of Electronics & Communication Engineering

Analog and Digital Systems Design Laboratory Manual

1. Engineering knowledge: Apply the knowledge of mathematics, science,

6. The engineer and society: Apply reasoning informed by the contextual

PEO1 : Proficiency to work in multidisciplinary domains, technological

PEO2 : Graduate with moral and ethical values

PEO3 : Explore the research possibilities, innovative practices and

PSO (Program Specific Outcomes)

PSO2: Ability to enrich the design in electronics through optimization, better

 Execution of Lab work in a safe manner is even more important than

Analog and Digital Systems Design

Course Outcomes PO & PSO

Laboratory Code BECL305 CIE Marks 50

Continuous Internal Evaluation (CIE):

Design and test an audio amplifier by connecting a L3,L4

Analog and Digital Electronic Circuits Laboratory is an introductory experimental

investigates the performance of transistors, JFETs/MOSFETs, and op-amps, timers, Logic

gates which includes the construction of an amplifier, Oscillators, multi-vibrators, data

conversion, rectifiers, Flip-flops, Adders and subtractors, counters, code converters

implementation of discrete experiments. Written and oral viva-voce of a experiment is

conducted in an environment similar to that of engineering design teams in industry. The

solutions that involve tradeoffs and the use of engineering judgment.

EXPERIMENT No-1: BJT COMMON EMITTER VOLTAGE AMPLIFIER

AIM: - To Study the Common Emitter Amplifier and to find

Dept. of ECE, RVITM Page 1

CIRCUIT DIAGRAM (with Feedback):

Fig(a) Circuit Diagram for Common Emitter Amplifier without Feedback

CIRCUIT DIAGRAM (without Feedback) :

Fig(b) Circuit Diagram for Common Emitter Amplifier with Feedback

Dept. of ECE, RVITM Page 2

Note downVi (P-P)…….

Common Emitter Amplifierwithout Feedback

SI. Output Voltage Gain=

Common Emitter Amplifierwith Feedback

SI. Output Voltage Gain=

 f1 is Lower Cut-Off Frequency.

Thus the Common Emitter Amplifier was designed and studied.

Dept. of ECE, RVITM Page 4

VIVA questions and answers

1. What is a Common Emitter Amplifier?

2. What are the characteristics of the common emitteramplifier?

3. What is the effect of voltage series feedback?

4. What are the applications of common emitter amplifier?

Dept. of ECE, RVITM Page 5

EXPERIMENT No- 2(A) : COLPITTS OSCILLATOR

Dept. of ECE, RVITM Page 6

1. Rig up the circuit as shown in Fig (a) for Hartley oscillator

The theoretical output frequency ……………….

Practical output frequency --------------.

Dept. of ECE, RVITM Page 7

EXPERIMENT No-2B: CRYSTAL OSCILLATOR

Dept. of ECE, RVITM Page 8

1. Make the circuit connection as shown in fig. a

Theoretical frequency = …2Mhz… Practical frequency = ………………………

Dept. of ECE, RVITM Page 9

VIVA questions and answers

2. Which type of feedback is used in oscillator. Specify the reason.

3. What is BARKHAUSEN CRITERION for oscillator

4. What are the advantages of Colpitts oscillator?