11N06LTA Datasheet
11N06LTA Datasheet
11N06LTA Datasheet
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
1 gate
2 drain 1
3 source
2 2
tab drain 1 3
1 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDSS Drain-source voltage Tj = 25 ˚C to 175˚C - 55 V
VDGR Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 55 V
VGS Gate-source voltage - ± 13 V
ID Continuous drain current Tmb = 25 ˚C - 11 A
Tmb = 100 ˚C - 7.6 A
IDM Pulsed drain current Tmb = 25 ˚C - 44 A
PD Total power dissipation Tmb = 25 ˚C - 36 W
Tj, Tstg Operating junction and - 55 175 ˚C
storage temperature
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-mb Thermal resistance junction - 4.17 K/W
to mounting base
Rth j-a Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT428 and SOT404 package, pcb 50 - K/W
mounted, minimum footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
V(BR)GSS Gate-source breakdown IG = ±1 mA; 10 - - V
voltage
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 5.5 A - 100 130 mΩ
resistance VGS = 5 V; ID = 5.5 A - 120 150 mΩ
Tj = 175˚C - 250 315 mΩ
gfs Forward transconductance VDS = 25 V; ID = 5.5 A 4 10 - S
IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA
Tj = 175˚C - - 20 µA
IDSS Zero gate voltage drain VDS = 55 V; VGS = 0 V; - 0.05 10 µA
current Tj = 175˚C - - 500 µA
Qg(tot) Total gate charge ID = 11 A; VDD = 44 V; VGS = 5 V - 6.1 - nC
Qgs Gate-source charge - 1.3 - nC
Qgd Gate-drain (Miller) charge - 3.2 - nC
td on Turn-on delay time VDD = 30 V; ID = 5 A; - 6 16 ns
tr Turn-on rise time VGS = 5 V; RG = 10 Ω - 23 35 ns
td off Turn-off delay time Resistive load - 18 30 ns
tf Turn-off fall time - 18 30 ns
Ld Internal drain inductance Measured from tab to centre of die - 3.5 - nH
Ls Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 250 330 pF
Coss Output capacitance - 34 50 pF
Crss Feedback capacitance - 35 50 pF
PD% Normalised Power Derating Transient thermal impedance, Zth j-mb (K/W)
120 10
110
100
90 1
80
70
60 0.1
50
40
30 0.01 PD tp tp
D=
T
20
10 t
T
0 0.001
0 20 40 60 80 100 120 140 160 180 1us 10us 100us 1ms 10ms 0.1s 1s 10s
Tmb / C pulse width, tp (s) PHB11N06LT
Fig.2. Normalised continuous drain current. Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V ID = f(VDS); parameter VGS
0.2
DC 1 ms
1 VGS = 5 V
10 ms
0.1
10 V
0.1 0
1 10 100 0 2 4 6 8 10
VDS, Drain-source voltage (Volts) ID, Drain current (Amps) PHB11N06LT
Fig.3. Safe operating area. Tmb = 25 ˚C Fig.6. Typical on-state resistance, Tj = 25 ˚C.
ID & IDM = f(VDS); IDM single pulse; parameter tp RDS(ON) = f(ID); parameter VGS
typ.
6 1.5
min.
4 1
175 C
2 0.5
Tj = 25 C
0 0
0 1 2 3 4 5 -100 -50 0 50 100 150 200
Gate-source voltage, VGS (V) Tj / C
5 2% typ 98%
Tj = 175 C 1E-03
4
3 1E-04
2
1E-05
1
0
0 2 4 6 8 10 1E-05
Drain current, ID (A) 0 0.5 1 1.5 2 2.5 3
a BUK959-60 Rds(on) normlised to 25degC Capacitances, Ciss, Coss, Crss (pF) PHB11N06LT
2.5 1000
2 Ciss
Coss
1.5 100
Crss
0.5 10
-100 -50 0 50 100 150 200 0.1 1 10 100
Tmb / degC Drain-source voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance. Fig.12. Typical capacitances, Ciss, Coss, Crss.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5.5 A; VGS = 5 V C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics. Fig.15. Normalised avalanche energy rating.
VGS = f(QG); parameter VDS WDSS% = f(Tmb)
10
175 C
VGS
-
-ID/100
Tj = 25 C
0 T.U.T.
5
R 01
RGS
shunt
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Source-drain voltage, VSDS (V)
Fig.16. Avalanche energy test circuit.
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
MECHANICAL DATA
11 max
15.4
2.5
MOUNTING INSTRUCTIONS
Dimensions in mm 11.5
9.0
17.5
2.0
3.8
5.08
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
MECHANICAL DATA
seating plane
4 min
6.22 max
10.4 max
4.6
2 0.5 min
0.5
1 3 0.3
0.8 max 0.5
(x2)
2.285 (x2)
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15 1.5
2.5
4.57
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
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