Dp83867e Sgmii

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DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015
DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical
Layer Transceiver
1 Features 3 Description
•
1 Extra Low Latency TX < 90ns, RX < 290ns The DP83867 is a robust, low power, fully featured
Physical Layer transceiver with integrated PMD
• Power consumption 457mW sublayers to support 10BASE-Te, 100BASE-TX and
• Exceeds 8kV IEC 61000-4-2 ESD Protection 1000BASE-T Ethernet protocols. Optimized for ESD
• Meets EN55011 Class B Emission Standards protection, the DP83867 exceeds 8kV IEC 61000-4-2
• 16 Programmable RGMII Delay Modes on RX/TX (direct contact).
• Integrated MDI Termination Resistors The DP83867 is designed for easy implementation of
10/100/1000 Mbps Ethernet LANs. It interfaces
• Programmable MAC Interface Termination
directly to twisted pair media via an external
impedance transformer. This device interfaces directly to the
• WoL (Wake on LAN) Packet Detection MAC layer through Reduced GMII (RGMII) or
• 25-MHz or 125-MHz Synchronized Clock Output embedded clock Serial GMII (SGMII).
• IEEE 1588 Time Stamp Support The DP83867 provides precision clock
• RJ45 Mirror Mode synchronization, including a synchronous Ethernet
clock output. It has low latency and provides IEEE
• Fully Compatible to IEEE 802.3 10BASE-Te,
1588 Start of Frame Detection.
100BASE-TX, and 1000BASE-T specification
• Cable Diagnostics Designed for low power, the DP83867 consumes only
457mW under full operating power. Wake on LAN
• RGMII and SGMII MAC Interface Options can be used to lower system power consumption.
• Configurable I/O Voltage (3.3V, 2.5V, 1.8V)
• Fast Link up / Link Drop Modes Device Information(1)
• JTAG Support Body Size
Part Number Temperature Package
(NOM)
DP83867CSRGZ 0°C to +70°C QFN (48) 7 mm x 7 mm
2 Applications
-40°C to
• Motor and Motion Control DP83867ISRGZ QFN (48) 7 mm x 7 mm
+85°C
• Industrial Factory Automation DP83867ERGZ
-40°C to
QFN (48) 7 mm x 7 mm
+105°C
• Industrial Embedded Computing
• Wired and Wireless Communications (1) For all available packages, see the orderable addendum at
the end of the data sheet.
Infrastructure
• Test and Measurement
• Consumer Electronics
4 System Diagram
10BASE-Te
RGMII
100BASE-TX
SGMII
1000BASE-T
DP83867
Ethernet MAC 10/100/1000 Mbps Magnetics RJ-45
Ethernet Physical Layer
25 MHz Status
Crystal or Oscillator LEDs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DP83867CS, DP83867IS, DP83867E
SNLS504 – OCTOBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.3 Feature Description................................................. 19
2 Applications ........................................................... 1 9.4 Device Functional Modes........................................ 21
3 Description ............................................................. 1 9.5 Programming .......................................................... 36
9.6 Register Maps ......................................................... 45
4 System Diagram..................................................... 1
5 Revision History..................................................... 2 10 Application and Implementation........................ 98
10.1 Application Information.......................................... 98
6 Device Comparison ............................................... 3
10.2 Typical Application ............................................... 98
7 Pin Configuration and Functions ......................... 3
11 Power Supply Recommendations ................... 102
7.1 Unused Pins............................................................. 6
12 Layout................................................................. 104
8 Specifications......................................................... 7
12.1 Signal Traces ...................................................... 104
8.1 Absolute Maximum Ratings ...................................... 7
12.2 Return path ......................................................... 104
8.2 ESD Ratings.............................................................. 7
12.3 Transformer Layout............................................. 105
8.3 Recommended Operating Conditions....................... 7
12.4 Metal Pour........................................................... 105
8.4 Thermal Information .................................................. 8
12.5 PCB Layer Stacking............................................ 105
8.5 Electrical Characteristics........................................... 8
12.6 Layout Example .................................................. 106
8.6 Powerup Timing ..................................................... 10
8.7 Reset Timing ........................................................... 11 13 Device and Documentation Support ............... 107
13.1 Documentation Support ..................................... 107
8.8 MII Serial Management Timing ............................... 12
13.2 Related Links ...................................................... 107
8.9 SGMII Timing .......................................................... 13
13.3 Community Resources........................................ 107
8.10 RGMII Timing ........................................................ 14
13.4 Trademarks ......................................................... 107
8.11 Typical Characteristics .......................................... 16
13.5 Electrostatic Discharge Caution .......................... 107
9 Detailed Description ............................................ 17
13.6 Glossary .............................................................. 107
9.1 Overview ................................................................. 17
9.2 Functional Block Diagram ....................................... 18 14 Mechanical, Packaging, and Orderable
Information ......................................................... 107
5 Revision History
DATE REVISION NOTES
October 2015 * Initial release.
2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

DP83867CS, DP83867IS, DP83867E
www.ti.com SNLS504 – OCTOBER 2015
6 Device Comparison
Table 1. Device Features Comparison

DEVICE MAC TEMPERATURE RANGE TEMPERATURE GRADE
DP83867CSRGZ SGMII/RGMII 0°C 70°C Commercial
DP83867ISRGZ SGMII/RGMII -40°C 85°C Industrial
DP83867ERGZ SGMII/RGMII -40°C 105°C Extended
7 Pin Configuration and Functions
48-Pin QFN
Package RGZ
Top View
INT/PWDN
RESET_N
VDDA1P8
RX_CTRL
TX_CTRL
VDD1P0
GPIO_1
GPIO_0
VDDIO
LED_0
LED_1
LED_2
48 47 46 45 44 43 42 41 40 39 38 37
TD_P_A 1 36 RX_D3/SGMII_SON
TD_M_A 2 35 RX_D2/SGMII_SOP
VDDA2P5 3 34 RX_D1/SGMII_CON
TD_P_B 4 33 RX_D0/SGMII_COP
DP83867
TD_M_B 5 32 RX_CLK
TOP VIEW
VDDA1P0 6 (not to scale) 31 VDD1P0
TD_P_C 7 48-pin QFN Package 30 VDDIO
TD_M_C 8 DAP = GND 29 GTX_CLK
VDDA2P5 9 28 TX_D0/SGMII_SIN
TD_P_D 10 27 TX_D1/SGMII_SIP
TD_M_D 11 26 TX_D2
RBIAS 12 25 TX_D3
13 14 15 16 17 18 19 20 21 22 23 24
VDDA1P8
X_O
X_I
MDC
MDIO
CLK_OUT
VDDIO
JTAG_CLK
JTAG_TDO
JTAG_TMS
JTAG_TDI
VDD1P0
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3

DP83867CS, DP83867IS, DP83867E
Table 2. Pin Functions

PIN
TYPE (1) DESCRIPTION
NAME NUMBER
MAC INTERFACES (SGMII, RGMII)
TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in
TX_D3 25 I, PD
RGMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D2 26 I, PD
Differential SGMII Data Input: This signal carries data from the MAC to the PHY
in SGMII mode. It is synchronous to the differential SGMII clock input.
SGMII_SIP 27 I, PD
This pin should be AC coupled to the MAC via a 0.1µF capacitor when
operating in SGMII mode.
TX_D1 27 I, PD
Differential SGMII Data Input: This signal carries data from the MAC to the PHY
in SGMII mode. It is synchronous to the differential SGMII clock input.
SGMII_SIN 28 I, PD
TX_D0 28 I, PD
RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the
GTX_CLK 29 I, PD
MAC layer to the PHY. Nominal frequency is 125 MHz.
RGMII RECEIVE CLOCK: Provides the recovered receive clocks for different
modes of operation:
RX_CLK 32 O 2.5 MHz in 10 Mbps mode.
25 MHz in 100 Mbps mode.
125 MHz in 1000 Mbps mode.
Differential SGMII Clock Output: This signal is a continuous 625MHz clock
signal driven by the PHY in SGMII mode.
SGMII_COP 33 S, O
RECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in
RX_D0 33 S, O, PD
RGMII mode. It is synchronous to the receive clock RX_CLK.
Differential SGMII Clock Output: This signal is a continuous 625MHz clock
signal driven by the MAC in SGMII mode.
SGMII_CON 34 S, O, PD
RX_D1 34 O, PD
Differential SGMII Data Output: This signal carries data from the PHY to the
MAC in SGMII mode. It is synchronous to the differential SGMII clock output.
SGMII_SOP 35 S, O, PD
RX_D2 35 S, O, PD
Differential SGMII Data Output: This signal carries data from the PHY to the
MAC in SGMII mode. It is synchronous to the differential SGMII clock output.
SGMII_SON 36 S, O, PD
(1) The definitions below define the functionality of each pin.

(a) Type: I Input
(b) Type: O Output
(c) Type: I/O Input/Output
(d) Type: PD, PU Internal Pulldown/Pullup
(e) Type: S Configuration Pin
(f) Type: P Power or GND
(g) Type: A Analog pins
NOTE: Internal Pull-Up/Pull-Down resistors on the IO pins are disabled when the device enters functional mode after power up.
DP83867CS, DP83867IS, DP83867E
Table 2. Pin Functions (continued)

PIN
NAME NUMBER
RX_D3 36 O, PD
TRANSMIT CONTROL: In RGMII mode, it combines the transmit enable and
TX_CTRL 37 I, PD
the transmit error signals of GMII mode using both clock edges.
RECEIVE CONTROL: In RGMII mode, the receive data available and receive
RX_CTRL 38 S, O, PD error are combined (RXDV_ER) using both rising and falling edges of the
receive clock (RX_CLK).
GENERAL PURPOSE I/O
General Purpose I/O: This signal provides a multi-function configurable I/O.
GPIO_0 39 S, O, PD
Please refer to the GPIO_MUX_CTRL register for details.
General Purpose I/O: This signal provides a multi-function configurable I/O.
GPIO_1 40 S, O, PD
Please refer to the GPIO_MUX_CTRL register for details.
MANAGEMENT INTERFACE
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial
management input/output data. This clock may be asynchronous to the MAC
MDC 16 I, PD
transmit and receive clocks. The maximum clock rate is 25MHz and no
minimum.
MANAGEMENT DATA I/O: Bi-directional management instruction/data signal
that may be sourced by the management station or the PHY. This pin requires
MDIO 17 I/O
pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ is
acceptable.
INTERRUPT / POWER DOWN:
The default function of this pin is POWER DOWN.
POWER DOWN: This is an Active Low Input. Asserting this signal low enables
the Power Down mode of operation. In this mode, the device will power down
and consume minimum power. Register access will be available through the
INT / PWDN 44 I/O, PU Management Interface to configure and power up the device.
INTERRUPT: This pin may be programmed as an interrupt output instead of a
Powerdown input. In this mode, Interrupts will be asserted low using this pin
making it an active low output. Register access is required for the pin to be
used as an interrupt mechanism. When operating this pin as an interrupt, an
external 2.2kΩ connected to the VDDIO supply is recommended.
RESET
RESET: The active low RESET initializes or re-initializes the DP83867. All
RESET_N 43 I, PU internal registers will re-initialize to their default state upon assertion of RESET.
The RESET input must be held low for a minimum of 1µs.
CLOCK INTERFACE
XI 15 I CRYSTAL/OSCILLATOR INPUT: 25 MHz oscillator or crystal input (50 ppm)
CRYSTAL OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if
XO 14 O
a clock oscillator is used.
CLK_OUT 18 O CLOCK OUTPUT: Output clock
JTAG INTERFACE
JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all
JTAG_CLK 20 I, PU
test logic input and output controlled by the testing entity.
JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most
JTAG_TDO 21 O
recent test results are scanned out of the device via TDO.
JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin
sequences the Tap Controller (16-state FSM) to select the desired test
JTAG_TMS 22 I, PU
instruction. It is recommended to apply 3 clock cycles with JTAG_TMS high to
reset the JTAG.
JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is
JTAG_TDI 23 I, PU
scanned into the device via TDI.
LED INTERFACE
LED_2: By default, this pin indicates receive or transmit activity. Additional
LED_2 45 S, I/O, PD
functionality is configurable via LEDCR1[11:8] register bits.

DP83867CS, DP83867IS, DP83867E
Table 2. Pin Functions (continued)

PIN
NAME NUMBER
LED_1: By default, this pin indicates that 1000BASE-T link is established.
LED_1 46 S, I/O, PD
Additional functionality is configurable via LEDCR1[7:4] register bits.
LED_0: By default, this pin indicates that link is established. Additional
LED_0 47 S, I/O, PD
functionality is configurable via LEDCR1[3:0] register bits.
MEDIA DEPENDENT INTERFACE
TD_P_A 1 A Differential Transmit and Receive Signals
TD_M_A 2 A Differential Transmit and Receive Signals
TD_P_B 4 A Differential Transmit and Receive Signals
TD_M_B 5 A Differential Transmit and Receive Signals
TD_P_C 7 A Differential Transmit and Receive Signals
TD_M_C 8 A Differential Transmit and Receive Signals
TD_P_D 10 A Differential Transmit and Receive Signals
TD_M_D 11 A Differential Transmit and Receive Signals
OTHER PINS
Bias Resistor Connection. A 11 kΩ +/-1% resistor should be connected from
RBIAS 12 A
RBIAS to GND.
POWER AND GROUND PINS
I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1µF &
VDDIO 19, 30, 41 P
0.1µF capacitor to GND
1.8V Analog Supply (+/-5%).
No external supply is required for this pin. When unused, no connections
should be made to this pin.
VDDA1P8 13, 48 P
For additional power savings, an external 1.8V supply can be connected to
these pins. When using an external supply, each pin requires a 1µF & 0.1µF
capacitor to GND.
2.5V Analog Supply (+/-5%). Each pin requires a 1µF & 0.1µF capacitor to
VDDA2P5 3, 9 P
GND.
1.0V Analog Supply (+15.5%, -5%). Each pin requires a 1µF & 0.1µF capacitor
VDD1P0 6, 24, 31, 42 P
to GND.
GND Die Attach Pad P Ground
7.1 Unused Pins

DP83867 has internal pull-ups or pull-downs on most pins. The datasheet details which pins have internal pull-
ups or pull-downs, and which pins require external pull resistors.
Even though a device may have internal pull-up or pull-down resistors, a good practice is to terminate unused
inputs, rather than allowing them to float. Floating inputs could result in unstable conditions. Except for VDDA1P8
pins, if they are not used then they should be left floating. It’s considered a safer practice to pull an unused input
pin high or low with a pull-up or pull-down resistor. It is also possible to group together adjacent unused input
pins, and as a group pull them up or down using a single resistor.

DP83867CS, DP83867IS, DP83867E
8 Specifications
8.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage (VDDA2P5) -0.3 3.0 V
Supply Voltage (VDDA1P8) -0.3 2.1 V
Supply Voltage (VDD1P0) -0.3 1.3 V
3.3 V Option -0.3 3.8 V
Supply Voltage (VDDIO) 2.5 V Option -0.3 3.0 V
1.8 V Option -0.3 2.1 V
MDI -0.3 6.5
MAC interface, MDIO, MDC, GPIO -0.3 VDDIO + 0.3V
PINS V
INT/PWDN, RESET -0.3 VDDIO + 0.3V
JTAG -0.3 VDDIO + 0.3V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per All pins except Media
±2500
ANSI/ESDA/JEDEC JS-001 (1) Dependent Interface pins
Media Dependent
Interface pins ±8000
V(ESD) Electrostatic discharge (ERGZ/ISRGZ) (2) V
Media Dependent
±6000
Interface pins (CSRGZ)
Charged-device model (CDM), per JEDEC
±1500
specification JESD22-C101 (3)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±8 V and/or ± 2 V may actually have higher
performance.
(2) MDI Pins tested as per IEC 61000-4-2 standards.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VDDA2P5 Supply Voltage 2.375 2.5 2.625 V
VDDA1P8 Supply Voltage 1.71 1.8 1.89 V
VDD1P0 Supply Voltage 0.95 1.0 1.155 V
3.3 V Option 3.15 3.3 3.45 V
VDDIO Supply Voltage 2.5 V Option 2.375 2.5 2.625 V
1.8 V Option 1.71 1.8 1.89 V
Operating Free Air Commercial (DP83867CSRGZ) 0 25 70 °C
Temperature
Industrial (DP83867ISRGZ) -40 25 85 °C
Extended (DP83867ERGZ) -40 25 105 °C

DP83867CS, DP83867IS, DP83867E
8.4 Thermal Information

RGZ
THERMAL METRIC (1) UNIT
48 PINS
RθJA Junction-to-ambient thermal resistance 30.8
RθJC(top) Junction-to-case (top) thermal resistance 18.7
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4
°C/W
RθJB Junction-to-board thermal resistance 7.5
ψJT Junction-to-top characterization parameter 0.3
ψJB Junction-to-board characterization parameter 7.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
Specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.3 V VDDIO
VOH High Level Output Voltage IOH = -4 mA 2 V
VOL Low Level Output Voltage IOL = 4 mA 0.6 V
VIH High Level Input Voltage 1.7 V
VIL Low Level Input Voltage 0.7 V
2.5 VVDDIO
VOH High Level Output Voltage IOH = -4 mA VDDIO * 0.8 V
VIH High Level Input Voltage 1.7 V
VIL Low Level Input Voltage 0.7 V
1.8 V VDDIO
VOH High Level Output Voltage IOH = -1 mA VDDIO – 0.2 V
VIH High Level Input Voltage 0.7 * VDDIO V
VIL Low Level Input Voltage 0.2 * VDDIO V
DC CHARACTERISTICS
IIH Input High Current VIN = VDD -40°C to +85°C -10 10 µA
VIN = VDD 85°C to +105°C -20 20 µA
IIL Input Low Current VIN = GND -40°C to +85°C -10 10 µA
VIN = GND 85°C to +105°C -20 20 µA
IOZ TRI-STATE Output Current VOUT = VDD, VOUT = GND
-10 10 µA
-40°C to +85°C
VOUT = VDD, VOUT = GND
-20 20 µA
85°C to +105°C
(1)
CIN Input Capacitance See 5 pF
PMD OUTPUTS
VOD-10 MDI ERGZ/ISRGZ 1.54 1.75 1.96 V Peak
CSRGZ 1.75 Differential
VOD-100 MDI ERGZ/ISRGZ 0.95 1 1.05 V Peak
CSRGZ 1 Differential
VOD-1000 MDI ERGZ/ISRGZ 0.67 0.745 0.82 V peak
CSRGZ 0.745 Differential
POWER CONSUMPTION
(1) Ensured by production test, characterization, or design.

DP83867CS, DP83867IS, DP83867E
Electrical Characteristics (continued)

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
Specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
P1000 RGMII Power consumption, 2
495 mW
supplies (2) (3)
P1000 RGMII Power consumption,
457 mW
optional 3rd supply (2) (3)
IDD25 Supply Current, 2 supplies 137 mA
IDD10 108 mA
IDDIO (1.8 V) 24 mA
IDD25 Supply Current, optional 3rd
86 mA
supply
IDD10 108 mA
IDD18 50 mA
IDDIO (1.8 V) 24 mA
(2) Power consumption represents total operational power for 1000BASE-T.

(3) See Power Supply Recommendations for details on 2 supply and 3 supply configuration.

DP83867CS, DP83867IS, DP83867E
(1)
8.6 Powerup Timing
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
T1 Post Power Up Stabilization time
MDIO is pulled high for 32-bit
prior to MDC preamble for 200 ms
serial management initialization.
register accesses
T2 Hardware Configuration Latch-in Hardware Configuration Pins are
200 ms
Time from power up described in Strap Configuration.
T3 Hardware Configuration pins
64 ns
transition to output drivers
VDD
X1 clock
T1
Hardware
RESET_N
32 CLOCKS
MDC
T2
Latch-In of Hardware
Configuration Pins
T3
Dual Function Pins

INPUT OUTPUT
Become Enabled As Outputs
Figure 1. Powerup Timing

DP83867CS, DP83867IS, DP83867E
8.7 Reset Timing (1)

T1 Post RESET Stabilization time MDIO is pulled high for 32-bit µs
prior to MDC preamble for serial management initialization. 195
register accesses
T2 Hardware Configuration Latch-in Hardware Configuration Pins are ns
Time from the Deassertion of described in Strap Configuration. 120
RESET (either soft or hard)
T3 Hardware Configuration pins ns
64
transition to output drivers
T4 RESET pulse width X1 Clock must be stable for a µs
minimum of 1 μs during RESET 1
pulse low time
VDD
X1 clock
T1
T4
Hardware
RESET _N
32 CLOCKS
MDC
T2
Latch-In of Hardware
Configuration Pins
T3
Dual F unction Pins

input output
Become Enabled As Outputs
Figure 2. Reset Timing

DP83867CS, DP83867IS, DP83867E
8.8 MII Serial Management Timing (1)

T1 MDC to MDIO (Output) Delay
0 10 ns
Time
T2 MDIO (Input) to MDC Setup
10 ns
Time
T3 MDIO (Input) to MDC Hold Time 10 ns
T4 MDC Frequency 2.5 25 MHz
MDC
T4 T1
MDIO (output )
MDC
T2 T3
MDIO (input) Valid Data
Figure 3. MII Serial Management Timing

DP83867CS, DP83867IS, DP83867E
8.9 SGMII Timing (1)

T1 SGMII Clock Output Duty Cycle 48 52 %
(2)
T2 Setup time See 100 ps
(3)
T3 Clock to Data relationship from See
either edges of the clock to valid 250 550 ps
data
TR VOD fall time 20% - 80% 100 200 ps
TF VOD rise time 20% - 80% 100 200 ps
(2)
Thold Hold time See 100 ps

(2) Setup and hold time are measured at 50% of the transition.
(3) T3 is measured at 0 V differential.
SG_RXCK
(single ended)
SG_RXCK
(differential)
tT2t tT1t
SG_RXDA
(single ended)
SG_RXDA
(differential)
T3 (min)
T3 (max)
Figure 4. SGMII Timing

DP83867CS, DP83867IS, DP83867E
8.10 RGMII Timing (1)

(2)
TskewT Data to Clock output Skew See -500 0 500 ps
(at Transmitter)
(2)
TskewR Data to Clock input Skew See 1 1.8 2.6 ns
(at Receiver)
(3)
TsetupT Data to Clock output Setup See 1.2 2 ns
(at Transmitter – internal
delay)
(3)
TholdT Clock to Data output Hold See 1.2 2 ns
(at Transmitter – internal
delay)
(3)
TsetupR Data to Clock input Setup See 1 2 ns
(at Reciever – internal delay)
(3)
TholdR Data to Clock input Setup See 1 2 ns
(at Receiver – internal delay)
Tcyc Clock Cycle Duration (4) See (4)
7.2 8 8.8 ns
(5) (5)
Duty_G Duty Cycle for Gigabit See 45 50 55 %
Duty_T Duty Cycle for 10/100T (5) See (5)
40 50 60 %
TR Rise Time (20% to 80%) 0.75 ns
TF Fall Time (20% to 80%) 0.75 ns
(6)
TTXLAT RGMII to MDI Latency See 88 ns
(6)
TRXLAT MDI to RGMII Latency See 288 ns

(2) When operating without RGMII internal delay, the PC board design requires clocks to be routed such that an additional trace delay of
greater than 1.5ns is added to the associated clock signal.
(3) Device may operate with or without internal delay.
(4) For 10Mbps and 100Mbps, Tcyc will scale to 400ns +/- 40ns and 40ns +/- 4ns.
(5) Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as
minimum duty cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.
(6) Operating in 1000Base-T .
GTX
(at Transmitter)
TskewT
TXD [8:5][3:0] TXD [8:5]

TXD [3:0]
TXD [7:4][3:0] TXD [7:4]
TXD [4] TXD [9]

TX_CTL
TXEN TXERR
TskewR
GTX
(at Receiver)
Figure 5. RGMII Transmit Multiplexing and Timing Diagram

DP83867CS, DP83867IS, DP83867E
RXC RXC with Internal

(Source of Data) Delay Added
TsetupT
RXD [8:5][3:0] RXD [8:5]

RXD [3:0]
RXD [7:4][3:0] RXD [7:4]
TholdT
RXD [4] RXD [9]

RX_CTL
RXDV RXERR
RXC
TholdR
(at Receiver)
TsetupR
Figure 6. RGMII Receive Multiplexing and Timing Diagram

DP83867CS, DP83867IS, DP83867E
8.11 Typical Characteristics

(200 mV/DIV)
(500 mV/DIV)
C1
C1
Time (4 ns/DIV) Time (32 ns/DIV)
1000Base-T Signaling 100Base-TX Signaling

(Test Mode TM2 Output) (Scrambled Idles)
Figure 7. 1000Base-T Signaling Figure 8. 100Base-TX Signaling

DP83867CS, DP83867IS, DP83867E
9 Detailed Description
9.1 Overview
The DP83867 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-
Te, 100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to
twisted pair media via an external transformer. This device interfaces directly to the MAC layer through the
Reduced GMII (RGMII) or embedded clock Serial GMII (SGMII).
The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has
deterministic, low latency and provides IEEE 1588 Start of Frame Detection.
The DP83867 offers innovative diagnostic features including dynamic link quality monitoring for fault prediction
during normal operation. It can support up to 130m cable length.

DP83867CS, DP83867IS, DP83867E
9.2 Functional Block Diagram
MGMT INTERFACE COMBINED RGMII / SGMII INTERFACE
RX_CTRL
GTX_CLK
TX_CTRL
RXD[3:0]
TXD[3:0]
RX_CLK
Interrupt
MDIO
MDC
MGNT
MUX / DMUX
& PHY CNTRL
100BASE-TX 10BASE-Te 1000BASE-T

Block Block Block
100BASE-TX 1000BASE-T Echo cancellation

10BASE-Te PLS
PCS PCS Crosstalk cancellation
ADC
Decode / Descramble
Equalization
Wake on Timing
LAN Skew compensation
100BASE-TX 10BASE-Te 10000BASE-T BLW
PMA PMA PMA
Auto-
Negotiation
Manchester
100BASE-TX 10 Mbps PAM-5
PMD 17 Level PR Shaped
125 Msymbols/s
MLT-3
100 Mbps
DAC / ADC
SUBSYSTEM
TIMING
DRIVERS /
RECEIVERS
DAC / ADC
TIMING BLOCK
MAGNETICS
4-pair CAT-5 Cable

DP83867CS, DP83867IS, DP83867E
9.3 Feature Description

9.3.1 WoL (Wake on LAN) Packet Detection
Wake on LAN provides a mechanism for bringing the DP83867 out of a low-power state using a special Ethernet
packet, called a Magic Packet. The DP83867 can be configured to generate an interrupt to wake up the MAC
when a qualifying packet is received. An option is also available to generate a signal on a GPIO when a
qualifying signal is received.
The Wake on LAN feature includes the following functionality
• Identification of magic packets in all supported speeds (1000BASE-T, 100BASE-TX, 10BASE-Te)
• Wakeup interrupt generation upon receiving a valid magic packet
• CRC checking of magic packets to prevent interrupt generation for invalid packets
In addition to the basic magic packet support, the DP83867 also supports:
• Magic packets that include secure-on password
• Pattern match – one configurable 64 byte pattern of that can wake up the MAC similar to magic packet
• Independent configuration for Wake on Broadcast and Unicast packet types.
9.3.1.1 Magic Packet Structure

When configured for Magic Packet mode, the DP83867 scans all incoming frames addressed to the node for a
specific data sequence. This sequence identifies the frame as a Magic Packet frame. It should be noted that the
Magic Packet should be byte aligned.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as SOURCE
ADDRESS, DESTINATION ADDRESS (which may be the receiving station’s IEEE address or a BROADCAST
address), and CRC.
The specific Magic Packet sequence consists of 16 duplications of the IEEE address of this node, with no breaks
or interruptions, followed by secure-on password if security is enabled. This sequence can be located anywhere
within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as 6
bytes of FFh.
DEST (6 bytes)
SRC (6 bytes)
MISC (X bytes, X >= 0)
))« )) (6 bytes)
MAGIC pattern
DEST * 16
SecureOn Password (6 bytes) Only if Secure-On is enabled
MISC (Y bytes, Y >= 0)
CRC (4 bytes)
Figure 9. Magic Packet Structure

DP83867CS, DP83867IS, DP83867E
Feature Description (continued)

9.3.1.2 Magic Packet Example
The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a
SecureOn Password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh:
DESTINATION SOURCE MISC FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22
33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44
55 66 11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC
9.3.1.3 Wake on LAN Configuration and Status

Wake on LAN functionality is configured via the RXFCFG register (address 0x0134). Wake on LAN status is
reported in the RXFSTS register (address 0x0135).
9.3.2 Start of Frame Detect for IEEE1588 Time Stamp

The DP83867 supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the receive and
transmit paths. The pulse can be delivered to various pins. The pulse indicates the actual time the symbol is
presented on the lines (for transmit), or the first symbol received (for receive). The exact timing of the pulse can
be adjusted via register. Each increment of phase value is an 8ns step.
Figure 10. IEEE 1588 Message Timestamp Point
The SFD pulse output can be configured using the GPIO Mux Control registers, GPIO_MUX_CTRL1 (register
address 0x0171) and GPIO_MUX_CTRL2 (register address 0x0172). The ENHANCED_MAC_SUPPORT bit in
RXCFG (register address 0x0134) must also be set to allow output of the SFD.
9.3.3 Clock Output

The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and the
Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock. The
local reference clock acts as the central source for all clocking in the device.
The local reference clock is embedded into the transmit network packet traffic and is recovered from the network
packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream
and is locked to the transmit clock in the partner.
Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal
clocks via the CLK_OUT pin. By default, the output clock is synchronous to the X_I oscillator / crystal input. The
default output clock is suitable for use as the reference clock of another DP83867 device. Via registers, the
output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or at the divide
by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock. When operating in
1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels.
The output clock can be disabled using the CLK_O_DISABLE bit of the I/O Configuration register.

DP83867CS, DP83867IS, DP83867E
9.4 Device Functional Modes

9.4.1 MAC Interfaces
The DP83867 supports connection to an Ethernet MAC via the following interfaces: SGMII and RGMII.
The SGMII Enable (LED_0) strap allows the user to turn on/off the SGMII MAC interface. The SGMII Enable
strap corresponds to the SGMII Enable (bit 11) in the PHYCR register (address 0x0010).
The SGMII enable has higher priority than the RGMII enable. Table 3 is the configuration table for the MAC
interfaces:
Table 3. Configuration Table for the MAC Interfaces

SGMII ENABLE (Register 0x0010, bit 11) RGMII ENABLE (Register 0x0032, bit 7) DEVICE FUNCTIONAL MODE
0x1 0x1 SGMII
0x1 0x0 SGMII
0x0 0x1 RGMII
The initial strap values for the SGMII enable and the RGMII disable are also available in the Strap Configuration
Status Register 1 (STRAP_STS1).
9.4.1.1 Serial GMII (SGMII)

The Serial Gigabit Media Independent Interface (SGMII) provides a means of conveying network data and port
speed between a 100/1000 PHY and a MAC with significantly less signal pins (4 or 6 pins) than required for GMII
(24 pins) or RGMII (12 pins). The SGMII interface uses 1.25Gbps LVDS differential signaling which has the
added benefit of reducing EMI emissions relative to GMII or RGMII.
Since the internal clock/data recovery circuitry (CDR) of DP83867 can detect the transmit timing of the SGMII
data, TX_CLK is not required. SGMII interface is capable of working as a 4-wire or 6-wire SGMII interface. The
default SGMII connection is via four wires. Two differential pairs are used for the transmit and receive
connections. Clock and data recovery are performed in the MAC and in the PHY so no additional differential pair
is required for clocking. Alternately, if the MAC is not capable of recovering the clock from the SGMII receive
data, the DP83867 can be configured to provide the SGMII receive clock via a differential pair
The 1.25Gbps rate of SGMII is excessive for 100Mbps operation. When operating in 100 Mbps mode, the PHY
"elongates" the frame by replicating each frame byte 10 times. This frame elongation takes place "above" the
IEEE 802.3 PCS layer, thus the start of frame delimiter only appears once per frame.
The SGMII interface includes Auto-Negotiation capability. Auto-Negotiation provides a mechanism for control
information to be exchanged between the PHY and the MAC. This allows the interface to be automatically
configured based on the media speed mode resolution on the MDI side. In MAC loopback mode, the SGMII
speed is determined by the MDI speed selection. The SGMII interface works in both Auto-Negotiation and forced
speed mode during the MAC loopback operation. SGMII Auto-Negotiation is the default mode of the operation.
The SGMII Auto-Negotiation process can be disabled and the SGMII speed mode can be forced to the MDI
resolved speed. The SGMII forced speed mode can be enabled with the MDI auto-negotiation or MDI manual
speed mode. SGMII Auto-Negotiation can be disabled via the SGMII_AUTONEG_EN register bit in the CFG2
register (address 0x0014).
The 10M_SGMII_RATE_ADAPT bit (bit 7) of 10M_SGMII_CFG register (0x016F) needs to be cleared for
enabling 10M SGMII operation.
SGMII is enabled via a resistor strap option. See Strap Configuration for details.
All SGMII connections should be AC coupled via an 0.1µF capacitor.
The connection diagrams for 4-wire SGMII and 6-wire SGMII are shown in Figure 11 and Figure 12.

DP83867CS, DP83867IS, DP83867E
Figure 11. SGMII 4-Wire Connections
Figure 12. SGMII 6-Wire Connections

DP83867CS, DP83867IS, DP83867E
9.4.1.2 Reduced GMII (RGMII)

The Reduced Gigabit Media Independent Interface (RGMII) is designed to reduce the number of pins required to
interconnect the MAC and PHY (12 pins for RGMII relative to 24 pins for GMII). To accomplish this goal, the data
paths and all associated control signals are reduced and are multiplexed. Both rising and trailing edges of the
clock are used. For Gigabit operation the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10 and 100 Mbps
operation the clock frequencies are 2.5 MHz and 25 MHz, respectively.
9.4.1.2.1 1000 Mbps Mode Operation

All RGMII signals are positive logic. The 8-bit data is multiplexed by taking advantage of both clock edges. The
lower 4 bits are latched on the positive clock edge and the upper 4 bits are latched on trailing clock edge. The
control signals are multiplexed into a single clock cycle using the same technique.
To reduce power consumption of RGMII interface, TXEN_ER and RXDV_ER are encoded in a manner that
minimizes transitions during normal network operation. This is done by following encoding method. Note that the
value of GMII_TX_ER and GMII_TX_EN are valid at the rising edge of the clock. In RGMII mode, GMII_TX_ER
is presented on TX_CTRL at the falling edge of the GTX_CLK clock. RX_CTRL coding is implemented the same
fashion.
When receiving a valid frame with no error, “RX_CTRL = True” is generated as a logic high on the rising edge of
RX_CLK and “RX_CTRL = False” is generated as a logic high at the falling edge of RX_CLK. When no frame is
being received, “RX_CTRL = False” is generated as a logic low on the rising edge of RX_CLK and “RX_CTRL =
False” is generated as a logic low on the falling edge of RX_CLK.
TX_CTRL is treated in a similar manner. During normal frame transmission, the signal stays at a logic high for
both edges of GTX_CLK and during the period between frames where no error is indicated, the signal stays low
for both edges.
9.4.1.2.2 1000 Mbps Mode Timing

The DP83867 provides configurable clock skew for the GTX_CLK and RX_CLK to optimize timing across the
interface. The transmit and receive paths can be optimized independently. Both the transmit and receive path
support 16 programmable RGMII delay modes via register configuration. Strap configuration can also be used to
configure 8 programmable RGMII modes for both the transmit and receive paths. See Strap Configuration for
details.
The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is
introduced. In Shift mode, the clock skew can be introduced in 0.5ns increments (via strap configuration) or in
0.25 ns increments (via register configuration). Configuration of the Aligned mode or Shift mode is accomplished
via the RGMII Control Register (RGMIICTL), address 0x0032. In Shift mode, the clock skew can be adjusted
using the RGMII Delay Control Register (RGMIIDCTL), address 0x0086.
9.4.1.2.3 10/100 Mbps Mode

When the RGMII interface is operating in the 100 Mbps mode, the Ethernet Media Independent Interface (MII) is
implemented by reducing the clock rate to 25 MHz. For 10 Mbps operation, the clock is further reduced to 2.5
MHz. In the RGMII 10/100 mode, the transmit clock RGMII TX_CLK is generated by the MAC and the receive
clock RGMII RX_CLK is generated by the PHY. During the packet receiving operation, the RGMII RX_CLK may
be stretched on either the positive or negative pulse to accommodate the transition from the free running clock to
a data synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or
negative pulses is allowed. No glitch is allowed on the clock signals during clock speed transitions.
This interface will operate at 10 and 100 Mbps speeds the same way it does at 1000 Mbps mode with the
exception that the data may be duplicated on the falling edge of the appropriate clock.
The MAC will hold RGMII TX_CLK low until it has ensured that it is operating at the same speed as the PHY.

DP83867CS, DP83867IS, DP83867E
Figure 13. RGMII Connections
9.4.2 Serial Management Interface

The Serial Management Interface (SMI), provides access to the DP83867 internal register space for status
information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register
set consists of the registers required by the IEEE 802.3, plus several others to provide additional visibility and
controllability of the DP83867 device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is
sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of
25 MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when
the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched
on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2 kΩ) which, during IDLE and
turnaround, pulls MDIO high.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During
power-up reset, the DP83867 latches the PHY_ADD configuration pins to determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid
operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In normal
MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus
allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific). The
data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes
sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time
inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no
device may actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83867 drives the
MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 14 shows the
timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the DP83867 (PHY)
for a typical register read access.
For write transactions, the station-management entity writes data to the addressed DP83867, thus eliminating the
requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>.
Figure 14 shows the timing relationship for a typical MII register write access. The frame structure and general
read/write transactions are shown in Table 4, Figure 14, and Figure 15.
Table 4. Typical MDIO Frame Format

Typical MDIO Frame Format <idle><start><op code><device addr><reg addr><turnaround><data<<idle>
Read Operation <idle><01><10><AAAA><RRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01<01><AAAA><RRRR><10><xxxx xxxx xxxx xxxx><idle>

DP83867CS, DP83867IS, DP83867E
Figure 14. Typical MDC/MDIO Read Operation
Figure 15. Typical MDC/MDIO Write Operation

DP83867CS, DP83867IS, DP83867E
9.4.2.1 Extended Address Space Access

The DP83867 SMI function supports read/write access to the extended register set using registers REGCR
(0x000Dh) and ADDAR (0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in
IEEE802.3ah Draft for clause 22 for accessing the clause 45 extended register set.
The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the
indirect method, except for register REGCR (0x000Dh) and ADDAR (0x000Eh) which is accessed only using the
normal MDIO transaction. The SMI function will ignore indirect accesses to these registers.
REGCR (0x000Dh) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the device
address DEVAD that directs any accesses of ADDAR (0x000Eh) register to the appropriate MMD.
The DP83867 supports one MMD device address. The vendor-specific device address DEVAD[4:0] = "11111" is
used for general MMD register accesses.
All accesses through registers REGCR and ADDAR must use the correct DEVAD. Transactions with other
DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01),
data with post increment on read and writes (10) and data with post increment on writes only (11).
• ADDAR is the address/data MMD register. ADDAR is used in conjunction with REGCR to provide the access
to the extended register set. If register REGCR[15:1] is 00, then ADDAR holds the address of the extended
address space register. Otherwise, ADDAR holds the data as indicated by the contents of its address
register. When REGCR[15:14] is set to 00, accesses to register ADDAR modify the extended register set
address register. This address register must always be initialized in order to access any of the registers within
the extended register set.
• When REGCR[15:14] is set to 01, accesses to register ADDAR access the register within the extended
register set selected by the value in the address register.
• When REGCR[15:14] is set to 10, access to register ADDAR access the register within the extended register
set selected by the value in the address register. After that access is complete, for both reads and writes, the
value in the address register is incremented.
• When REGCR[15:14] is set to 11, access to register ADDAR access the register within the extended register
set selected by the value in the address register. After that access is complete, for write accesses only, the
value in the address register is incremented. For read accesses, the value of the address register remains
unchanged.
The following sections describe how to perform operations on the extended register set using register REGCR
and ADDAR. The descriptions use the device address for general MMD register accesses (DEVAD[4:0] =
"11111").
9.4.2.2 Write Address Operation

1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
2. Write the desired register address to register ADDAR.
Subsequent writes to register ADDAR (step 2) continue to write the address register.
9.4.2.3 Read Address Operation

To read the address register:
2. Read the register address from register ADDAR.

DP83867CS, DP83867IS, DP83867E
9.4.2.4 Write (No Post Increment) Operation

To write a register in the extended register set:
3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.
4. Write the content of the desired extended register set register to register ADDAR.
Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the
address register.
Note: steps (1) and (2) can be skipped if the address register was previously configured.
9.4.2.5 Read (No Post Increment) Operation

To read a register in the extended register set:
3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.
4. Read the content of the desired extended register set register to register ADDAR.
Subsequent reads from register ADDAR (step 4) continue reading the register selected by the value in the
address register.
Note: steps (1) and (2) can be skipped if the address register was previously configured.
9.4.2.6 Write (Post Increment) Operation

2. Write the register address from register ADDAR.
3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) or the
value 0xC01F (data, post increment on writes function field = 11. DEVAD = 31) to register REGCR.
4. Write the content of the desired extended register set register to register ADDAR.
Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the
value of the address register; the address register is incremented after each access.
9.4.2.7 Read (Post Increment) Operation

To read a register in the extended register set and automatically increment the address register to the next
higher value following the write operation:
3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) to
register REGCR.
4. Read the content of the desired extended register set register to register ADDAR.
Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the value
of the address register; the address register is incremented after each access.
9.4.2.8 Example of Read Operation Using Indirect Register Access

Read register 0x0170.
1. Write register 0x0D to value 0x001F.
2. Write register 0x0E to value 0x0170
4. Read register 0x0E.
The expected default value is 0x0C10.

DP83867CS, DP83867IS, DP83867E
9.4.2.9 Example of Write Operation Using Indirect Register Access

Write register 0x0170 to value 0x0C50.
2. Write register 0x0E to value 0x0170
4. Write register 0x0E to value 0x0C50.
This write will disable the output clock on the CLK_OUT pin.
9.4.3 Auto-Negotiation
All 1000BASE-T PHYs are required to support Auto-Negotiation. The Auto-Negotiation function in 1000BASE-T
has three primary purposes:
• Auto-Negotiation of Speed & Duplex Selection
• Auto-Negotiation of Master/Slave Resolution
• Auto-Negotiation of Pause/Asymetrical Pause Resolution
9.4.3.1 Speed/Duplex Selection - Priority Resolution

The Auto-Negotiation function provides a mechanism for exchanging configuration information between the two
ends of a link segment. This mechanism is implemented by exchanging Fast Link Pulses (FLP). FLPs are burst
pulses that provide the signalling used to communicate the abilities between two devices at each end of a link
segment. For further details regarding Auto-Negotiation, refer to Clause 28 of the IEEE 802.3 specification. The
DP83867 supports 1000BASE-T, 100BASE-TX, and 1000BASE-T modes of operation. The process of Auto-
Negotiation ensures that the highest performance protocol is selected (i.e., priority resolution) based on the
advertised abilities of the Link Partner and the local device.
9.4.3.2 Master/Slave Resolution

If 1000BASE-T mode is selected during the priority resolution, the second goal of Auto-Negotiation is to resolve
Master/ Slave configuration. The Master mode priority is given to the device that supports multiport nodes, such
as switches and repeaters. Single node devices such as DTE or NIC card takes lower Master mode priority.
9.4.3.3 Pause and Asymmetrical Pause Resolution

When Full-Duplex operation is selected during priority resolution, the Auto-Negotiation also determines the Flow
Control capabilities of the two link partners. Flow control was originally introduced to force a busy station’s Link
Partner to stop transmitting data in Full-Duplex operation. Unlike Half-Duplex mode of operation where a link
partner could be forced to back off by simply generating collisions, the Full-Duplex operation needed a
mechanism to slow down transmission from a link partner in the event that the receiving station’s buffers are
becoming full. A new MAC control layer was added to handle the generation and reception of Pause Frames.
Each MAC Controller has to advertise whether it is capable of processing Pause Frames. In addition, the MAC
Controller advertises if Pause frames can be handled in both directions, i.e. receive and transmit. If the MAC
Controller only generates Pause frames but does not respond to Pause frames generated by a link partner, it is
called Asymmetrical Pause. The advertisement of Pause and Asymmetrical Pause capabilities is enabled by
writing ‘1’ to bits 10 and 11 of ANAR (register address 0x0004). The link partner’s Pause capabilities is stored in
ANLPAR (register address 0x0005) bits 10 and 11. The MAC Controller has to read from ANLPAR to determine
which Pause mode to operate. The PHY layer is not involved in Pause resolution other than simply advertising
and reporting of Pause capabilities.

DP83867CS, DP83867IS, DP83867E
9.4.3.4 Next Page Support

The DP83867 supports the Auto-Negotiation Next Page protocol as required by IEEE 802.3 clause 28.2.4.1.7.
The ANNPTR 0x07 allows for the configuration and transmission of the Next Page. Refer to clause 28 of the
IEEE 802.3 standard for detailed information regarding the Auto-Negotiation Next Page function.
9.4.3.5 Parallel Detection

The DP83867 supports the Parallel Detection function as defined in the IEEE 802.3 specification. Parallel
Detection requires the 10/100 Mbps receivers to monitor the receive signal and report link status to the Auto-
Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that
the Link Partner does not support Auto-Negotiation, yet is transmitting link signals that the 10BASE-Te or
100BASE-X PMA recognize as valid link signals.
If the DP83867 completes Auto-Negotiation as a result of Parallel Detection, without Next Page operation, bits 5
and 7 of ANLPAR (register address 0x0005) will be set to reflect the mode of operation present in the Link
Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may determine that the negotiation is completed via Parallel
Detection by reading ‘0’ in bit 0 of ANER (register address 0x006) after Auto-Negotiation Complete, bit 5 of
BMSR (register address 0x0001), is set. If the PHY is configured for parallel detect mode and any condition other
than a good link occurs, the parallel detect fault, bit 4 of ANER (register address 0x06), will set.
9.4.3.6 Restart Auto-Negotiation

If a link is established by successful Auto-Negotiation and then lost, the Auto-Negotiation process will resume to
determine the configuration for the link. This function ensures that a link can be re-established if the cable
becomes disconnected and re-connected. After Auto-Negotiation is completed, it may be restarted at any time by
writing ‘1’ to bit 9 of the BMCR (register address 0x0000). A restart Auto-Negotiation request from any entity,
such as a management agent, will cause DP83867 to halt data transmission or link pulse activity until the
break_link_timer expires. Consequently, the Link Partner will go into link fail mode and the resume Auto-
Negotiation. The DP83867 will resume Auto-Negotiation after the break_link_timer has expired by transmitting
FLP (Fast Link Pulse) bursts.
9.4.3.7 Enabling Auto-Negotiation via Software

If the DP83867 is initialized upon power-up with Auto-Negotiation disabled and the user may desire to restart
Auto-Negotiation, this could be accomplished by software access. Bit 12 of BMCR (register address 0x00) should
be cleared and then set for Auto-Negotiation operation to take place.
9.4.3.8 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation typically take 2-3 seconds to complete. In addition, Auto-Negotiation with
next page exchange takes approximately 2-3 seconds to complete, depending on the number of next pages
exchanged. Refer to Clause 28 of the IEEE 802.3 standard for a full description of the individual timers related to
Auto-Negotiation
9.4.3.9 Auto-MDIX Resolution

The DP83867 can determine if a “straight” or “crossover” cable is used to connect to the link partner. It can
automatically re-assign channel A and B to establish link with the link partner, (and channel C and D in
1000BASE-T mode). Auto-MDIX resolution precedes the actual Auto-Negotiation process that involves exchange
of FLPs to advertise capabilities. Automatic MDI/MDIX is described in IEEE 802.3 Clause 40, section 40.8.2. It is
not a required implementation for 10BASE-Te and 100BASE-TX.
Auto-MDIX can be enabled or disabled by strap, using the AMDIX Disable strap, or by register configuration,
using bit 6 of the PHYCR register (address 0x0010). When Auto-MDIX is disabled, the PMA is forced to either
MDI (“straight”) or MDIX (“crossed”). Manual configuration of MDI or MDIX can also be accomplished by strap,
using the Force MDI/X strap, or by register configuration, using bit 5 of the PHYCR register.
For 10/100, Auto-MDIX is independent of Auto-Negotiation. Auto-MDIX works in both Auto-Negotiation mode and
manual forced speed mode.

DP83867CS, DP83867IS, DP83867E
9.4.4 Loopback Mode

There are several options for Loopback that test and verify various functional blocks within the PHY. Enabling
loopback mode allows in-circuit testing of the digital and analog data paths. Generally, the DP83867 may be
configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. MII Loopback is
configured using the BMCR (register address 0x0000). All other loopback modes are enabled using the BISCR
(register address 0x16). Except where otherwise noted, loopback modes are supported for all speeds
(10/100/1000) and all MAC interfaces (SGMII and RGMII).
The availability of Loopback depends on the operational mode of the PHY. The Link Status in these loopback
modes is also affected by the operational mode. The following table lists out the availability of Loopback Modes
and their corresponding Link Status indication.
Table 5. Loopback Availability

Loopback Mode MAC Interface 1000M 100M 10M
Availability Link Status Availability Link Status Availability Link Status
MII RGMII Yes No Yes No Yes No
PCS RGMII Yes No Yes Yes No No
Digital RGMII Yes Yes Yes Yes Yes Yes
Analog RGMII Yes Yes Yes Yes Yes Yes
External RGMII No No Yes Yes Yes Yes
MII SGMII Yes No Yes No No No
Digital SGMII Yes Yes Yes Yes No No
IO SGMII Yes Yes Yes Yes No No
9.4.4.1 Near-End Loopback

Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog
circuitry. The point at which the signal is looped back is selected using loopback control bits with several options
being provided.
When configuring loopback modes, the Loopback Configuration Register (LOOPCR), address 0x00FE, should be
set to 0xE720.
To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting the Near-End
Loopback mode. This constraint does not apply for external-loopback mode.
Auto-MDIX should be disabled before selecting the Near-End Loopback mode. MDI or MDIX configuration should
be manually configured.
9.4.4.1.1 MII Loopback

MII Loopback is the shallowest loop through the PHY. It is a useful test mode to validate communications
between the MAC and the PHY. While in MII Loopback mode the data is looped back, and can also be
configured via register to transmit onto the media.
9.4.4.1.2 PCS Loopback

PCS Loopback occurs in the PCS layer of the PHY. No signal processing is performed when using PCS
Loopback.
9.4.4.1.3 Digital Loopback

Digital Loopback includes the entire digital transmit – receive path. Data is looped back prior to the analog
circuitry.
9.4.4.1.4 Analog Loopback

Analog Loopback includes the entire analog transmit-receive path.

DP83867CS, DP83867IS, DP83867E
9.4.4.2 External Loopback

When operating in 10BASE-Te or 100Base-T mode, signals can be looped back at the RJ-45 connector by wiring
the transmit pins to the receive pins. Due to the nature of the signaling in 1000Base-T mode, this type of external
loopback is not supported. Analog Loopback provides a way to loop data back in the analog circuitry when
operating in 1000Base-T mode. For proper operation in Analog Loopback mode, attach 100-Ω terminations to the
RJ45 connector.
9.4.4.3 Far-End (Reverse) Loopback

Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In this
mode, data that is received from the link partner passes through the PHY's receiver, is looped back at the MAC
interface and is transmitted back to the link partner. While in Reverse Loopback mode, all data signals that come
from the MAC are ignored. Through register configuration, data can also be transmitted onto the MAC Interface.

DP83867CS, DP83867IS, DP83867E
9.4.5 BIST Configuration

The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or
diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST
can be performed using both internal loopback (digital or analog) or external loopback using a cable fixture. The
BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet Gap (IPG) on
the lines. The BIST allows full control of the packet lengths and of the IPG.
The BIST is implemented with independent transmit and receive paths, with the transmit block generating a
continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for
the BIST. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback
Shift Register (LFSR) to determine the BIST pass/fail status. The number of error bytes that the PRBS checker
received is stored in the BICSR2 register (0x0072). The status of whether the PRBS checker is locked to the
incoming receive bit stream, whether the PRBS has lost sync, and whether the packet generator is busy, can be
read from the STS2 register (0x0017h). While the lock and sync indications are required to identify the beginning
of proper data reception, for any link failures or data corruption, the best indication is the contents of the error
counter in the BICSR2 register (0x0072). The number of received bytes are stored in BICSR1 (0x0071).
The PRBS test can be put in a continuous mode by using bit 14 of the BISCR register (0x0016h). In continuous
mode, when one of the PRBS counters reaches the maximum value, the counter starts counting from zero again.
Packet transmission can be configured for one of two types, 64 and 1518 bytes, through register bit 13 of the
BISCR register (0x0016).
9.4.6 Cable Diagnostics

With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable
diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed
results in the need to non-intrusively identify and report cable faults. The TI cable-diagnostic unit provides
extensive information about cable integrity. The DP83867 offers the following capabilities in its Cable Diagnostic
tools kit:
1. Time Domain Reflectometry (TDR)
2. Active Link Cable Diagnostic (ALCD)
9.4.6.1 TDR
The DP83867 uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and
terminations in addition to estimating the cable length. Some of the possible problems that can be diagnosed
include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, cross faults, cross
shorts and any other discontinuities along the cable.
The DP83867 transmits a test pulse of known amplitude (1 V or 2.5 V) down each of the two pairs of an attached
cable. The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad
connector, and from the end of the cable itself. After the pulse transmission, the DP83867 measures the return
time and amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude
(impedance) of non-terminated cables (open or short), discontinuities (bad connectors), improperly-terminated
cables, and crossed pairs wires with ±1m accuracy.
The DP83867 also uses data averaging to reduce noise and improve accuracy. The DP83867 can record up to
five reflections within the tested pair. If more than 5 reflections are recorded, the DP83867 saves the first 5 of
them. If a cross fault is detected, the TDR saves the first location of the cross fault and up to 4 reflections in the
tested channel. The DP83867 TDR can measure cables beyond 100m in length.
For all TDR measurements, the transformation between time of arrival and physical distance is done by the
external host using minor computations (such as multiplication, addition and lookup tables). The host must know
the expected propagation delay of the cable, which depends, among other things, on the cable category (for
example, CAT5, CAT5e, or CAT6).

DP83867CS, DP83867IS, DP83867E
TDR measurement is allowed in the DP83867 in the following scenarios:

• While Link partner is disconnected – cable is unplugged at the other side
• Link partner is connected but remains “quiet” (for example, in power down mode)
• TDR could be automatically activated when the link fails or is dropped by setting bit 7 of register 0x0009
(CFG1). The results of the TDR run after the link fails will be saved in the TDR registers.
Software could read these registers at any time to apply post processing on the TDR results. This mode is
designed for cases in which the link dropped due to cable disconnections, in which case, after link failure, the line
will be quiet to allow a proper function of the TDR.
9.4.6.2 ALCD
The DP83867 also supports Active Link Cable Diagnostic (ALCD). The ALCD offers a passive method to
estimate the cable length during active link. The ALCD uses passive digital signal processing based on adapted
data, thus enabling measurement of cable length with an active link partner. The ALCD Cable length
measurement accuracy is ±5m for the pair used in the Rx path (due to the passive nature of the test, only the
receive path is measured).
9.4.6.3 Energy Detect

The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an
IIR filter, this robust energy detector has excellent reaction time and reliability. The filter output is compared to
predefined thresholds in order to decide the presence or absence of an incoming signal. The energy detector
also implements hysteresis to avoid jittering in signal-detect indication. In addition it has fully-programmable
thresholds and listening-time periods, enabling shortening of the reaction time if required.
9.4.6.4 Fast Link Drop

The DP83867 includes advanced link-down capabilities that support various real-time applications. The link down
mechanism is configurable and includes enhanced modes that allow extremely fast reaction times to link-drops.
First Link Failure
Occurrence
Valid Data LOW Quality Data / Link Loss
Signal
Link Drop
T1
Link Loss
Indication
(Link LED)
Figure 16. Fast Link Drop Mechanism
As described in Figure 16, the link loss mechanism is based on a time window search period, in which the signal
behavior is monitored. The T1 window is set by default to reduce typical link-drops to less than 1ms in 100M and
0.5ms in 1000M mode.
The DP83867 supports enhanced modes that shorten the window called Fast Link Down mode. In this mode the
T1 window is shortened significantly, in most cases less than 10 μs. In this period of time there are several
criteria allowed to generate link loss event and drop the link:
1. Loss of descrambler sync
2. Receive errors
3. MLT3 errors
4. Mean Squared Error (MSE)
5. Energy loss
DP83867CS, DP83867IS, DP83867E
The Fast Link Down functionality allows the use of each of these options separately or in any combination. Note
that since this mode enables extremely quick reaction time, it is more exposed to temporary bad link quality
scenarios.
9.4.6.5 Fast Link Detect

Several advanced modes are available for fast link establishment. Unlike the Auto-Negotiation and Auto-MDIX
mechanisms defined by the IEEE 802.3 specification, these modes are specific to the DP83867. Care must be
taken when implementing these modes. For best operation, it is recommended that these modes be
implemented with a DP83867 on both ends of the link.
These advanced link and crossover modes depend on the speed selected for the link. Some modes are intended
for use in 1000Base-T operation. Others are intended for use in 100Base-TX operation.
Fast Link Detect functionality can be configured using the Configuration Register 3 (CFG3), address 0x001E.
9.4.6.6 Speed Optimization

Speed optimization, also known as link downshift, enables fallback to 100M operation after multiple consecutive
failed attempts at Gigabit link establishment. Such a case could occur if cabling with only four wires (two twisted
pairs) were connected instead of the standard cabling with eight wires (four twisted pairs).
The number of failed link attempts before falling back to 100M operation is configurable. By default, four failed
link attempts are required before falling back to 100M.
In enhanced mode, fallback to 100M can occur after one failed link attempt if energy is not detected on the C and
D channels. Speed optimization also supports fallback to 10M if link establishment fails in Gigabit and in 100M
mode.
Speed optimization can be enabled via register configuration.

DP83867CS, DP83867IS, DP83867E
9.4.6.7 Mirror Mode

In some multiport applications, RJ-45 ports may be mirrored relative to one another. This mirroring can require
crossing board traces. The DP83867 can resolve this issue by implementing mirroring of the ports inside the
device.
In 10/100 operation, the mapping of the port mirroring is:
MDI MODE MIRROR PORT CONFIGURATION

MDI A→D
B→C
MDIX A→D
B→C
In Gigabit operation, the mapping of the port mirroring is:
MDI MODE MIRROR PORT CONFIGURATION

MDI or MDIX A→D
B→C
C→B
D→A
Mirror mode can be enabled via strap or via register configuration using the Port Mirror Enable bit in the CFG4
9.4.6.8 Interrupt
The DP83867 can be configured to generate an interrupt when changes of internal status occur. The interrupt
allows a MAC to act upon the status in the PHY without polling the PHY registers. The interrupt source can be
selected through the interrrupt registers, MICR (register address 0x0012) and ISR (register address 0x0013).
9.4.6.9 IEEE 802.3 Test Modes

IEEE 802.3 specification for 1000BASE-T requires that the PHY layer be able to generate certain well defined
test patterns on TX outputs. Clause 40 section 40.6.1.1.2 “Test Modes” describes these tests in detail. There are
four test modes as well as the normal operation mode. These modes can be selected by writing to the CFG1
See IEEE 802.3 section 40.6.1.1.2 “Test modes” for more information on the nature of the test modes. The
DP83867 provides a test clock synchronous to the IEEE test patterns. The test patterns are output on the MDI
pins of the device and the transmit clock is output on the CLK_OUT pin.

DP83867CS, DP83867IS, DP83867E
9.5 Programming
9.5.1 Strap Configuration
The DP83867 uses many of the functional pins as strap options to place the device into specific modes of
operation. The values of these pins are sampled at power up or hard reset. During software resets, the strap
options are internally reloaded from the values sampled at power up or hard reset. The strap option pin
assignments are defined below. The functional pin name is indicated in parentheses.
The strap pins supported are 4-level straps, which are described in greater detail below.
NOTE
Since strap pins may have alternate functions after reset is deasserted, they should not be
connected directly to VDD or GND.
Configuration of the device may be done via the 4-level strap pins or via the management register interface. A
pullup resistor and a pulldown resistor of suggested values may be used to set the voltage ratio of the 4-level
strap pin input and the supply to select one of the possible selected modes.
The MAC interface pins must support I/O voltages of 3.3 V, 2.5 V, and 1.8 V. As the strap inputs will be
implemented on these pins, the straps must also support operation at 3.3-V, 2.5-V, and 1.8-V supplies.
The device should feature 4-level strap pins, each supporting at least 4 selectable options.
VDDIO DP83867
Rhi
V STRAP
9k
Rlo
±25%
Figure 17. Strap Circuit
Table 6. 4-level Strap Resistor Ratios

MODE Target Voltage IDEAL Rhi (kΩ) IDEAL Rlo (kΩ)
Vmin (V) Vtyp (V) Vmax (V)
1 0 0 0.065*VDDIO OPEN OPEN
2 0.139*VDDIO 0.15*VDDIO 0.16*VDDIO 11 2.49
3 0.228*VDDIO 0.244*VDDIO 0.256*VDDIO 6.04 2.49
4 0.728*VDDIO 0.783*VDDIO 0.82*VDDIO 2.49 OPEN
For SGMII Mode 4 strap, it is recommended to use Rhi=4kΩ and Rlo=10kΩ on RX_D0 & RX_D1 , RX_D2 &
RX_D3.
All straps have a 9kΩ ±25% internal pull down resistor. The voltage at strap pins should be between the Vmin
and Vmax mentioned in the 'Target Voltage' column in the table above. Strap resistors with 1% tolerance are
recommended.

DP83867CS, DP83867IS, DP83867E
The following tables describes the DP83867 configuration straps:
Table 7. 4-Level Strap Pins

PIN NAME 48 QFN PIN # DEFAULT STRAP FUNCTION
RX_D0 33 [00] MODE PHY_ADD1 PHY_ADD0
1 0 0
2 0 1
3 1 0
4 1 1
RX_D2 35 [00] MODE PHY_ADD3 PHY_ADD2
1 0 0
2 0 1
3 1 0
4 1 1
RX_CTRL 38 [00] MODE Autoneg Disable
1 0
2 1
3 0
4 1
(1) RGMII Clock Skew
GPIO_0 39 [00] MODE
RX[0]
1 0
2 Not Applicable
3 1
4 Not Applicable
RGMII Clock Skew RGMII Clock Skew
GPIO_1 40 [00] MODE
RX[2] RX[1]
1 0 0
2 0 1
3 1 0
4 1 1
RGMII Clock Skew RGMII Clock Skew
LED_2 45 [00] MODE
TX[1] TX[0]
1 0 0
2 0 1
3 1 0
4 1 1
(1) Only Mode 1 and 3 are valid for GPIO_0. Mode 2 and Mode 4 are not applicable and should not be used.

DP83867CS, DP83867IS, DP83867E
Table 7. 4-Level Strap Pins (continued)

PIN NAME 48 QFN PIN # DEFAULT STRAP FUNCTION
RGMII Clock Skew
LED_1 46 [00] MODE SPEED_SEL
TX[2]
1 0 0
2 0 1
3 1 0
4 1 1
LED_0 47 [00] MODE Mirror Enable SGMII Enable
1 0 0
2 0 1
3 1 0
4 1 1
NOTE
Note: RX_D1 is not a strap input, but this pin must be populated with the same strap
resistors chosen for RX_D0. RX_D0 and RX_D1 form an SGMII differential pair. The
dummy straps on RX_D1 are required to provide a balanced load for this SGMII
differential pair.
NOTE
Note: RX_D3 is not a strap input, but this pin must be populated with the same strap
resistors chosen for RX_D2. RX_D2 and RX_D3 form an SGMII differential pair. The
dummy straps on RX_D3 are required to provide a balanced load for this SGMII
differential pair.
Table 8. Speed Select Strap Details

MODE SPEED_SEL REMARKS
10/100/1000 0 advertise ability of 10/100/1000
100/1000 1 advertise ability of 100/1000 only
Table 9. RGMII Transmit Clock Skew Details

RGMII CLOCK SKEW RGMII CLOCK SKEW RGMII CLOCK SKEW
MODE RGMII TX CLOCK SKEW
TX[2] TX[1] TX[0]
1 0 0 0 2.0 ns
2 0 0 1 1.5 ns
3 0 1 0 1.0 ns
4 0 1 1 0.5 ns
5 1 0 0 4.0 ns
6 1 0 1 3.5 ns
7 1 1 0 3.0 ns
8 1 1 1 2.5 ns

DP83867CS, DP83867IS, DP83867E
Table 10. RGMII Receive Clock Skew Details

RGMII CLOCK SKEW RGMII CLOCK SKEW RGMII CLOCK SKEW
MODE RGMII RX CLOCK SKEW
RX[2] RX[1] RX[0]
1 0 0 0 2.0 ns
2 0 0 1 1.5 ns
3 0 1 0 1.0 ns
4 0 1 1 0.5 ns
5 1 0 0 4.0 ns
6 1 0 1 3.5 ns
7 1 1 0 3.0 ns
8 1 1 1 2.5 ns
9.5.2 LED Configuration

The DP83867 supports four configurable Light Emitting Diode (LED) pins: LED_0, LED_1, and LED_2. A GPIO
can also be configured to operate as an LED. Several functions can be multiplexed onto the LEDs for different
modes of operation. The LED operation mode can be selected using the LEDCR1 register (address 0x0018).
Since the LED output pins are also used as straps, the external components required for strapping and LED
usage must be considered in order to avoid contention. Specifically, when the LED outputs are used to drive
LEDs directly, the active state of each output driver is dependent on the logic level sampled by the corresponding
AN input upon power-up/reset.
If a given strap input is resistively pulled low then the corresponding output will be configured as an active high
driver. In the context of the 4-level straps, this will occur for modes 1, 2, and 3. Conversely, if a given strap input
is resistively pulled high, then the corresponding output will be configured as an active low driver. In the context
of the 4-level straps, this will occur only for mode 4.
Refer to Figure 18 for an example of strap connections to external components. In this example, the strapping
results in Mode 1 for LED_0 and Mode 4 for LED_1.
The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose
pins.
LED_0
LED_1
Mode 1 Mode 4
2.49 lQ
470Q 470Q
VDD
GND
Figure 18. Example Strap Connections

DP83867CS, DP83867IS, DP83867E
9.5.3 LED Operation from 1.8 V I/O VDD Supply

Operation of LEDs from a 1.8-V supply results in dim LED lighting. For best results, the recommendation is to
operate from a higher supply (2.5 V or 3.3 V). Refer to Figure 19 for a possible implementation of this
functionality.
LED_2
2.5V or 3.3V
Mode 2
200 Q
1.8V
11 lQ
2.49 lQ
GND GND
Figure 19. LED Operation from 1.8 V I/O VDD Supply

DP83867CS, DP83867IS, DP83867E
9.5.4 PHY Address Configuration

The DP83867 can be set to respond to any of 16 possible PHY addresses via strap pins. The information is
latched into the device at a device power up or hardware reset. Each DP83867 or port sharing an MDIO bus in a
system must have a unique physical address. The DP83867 supports PHY address strapping values 0 (<0000>)
through 15 (<1111>).
For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other
hardware configuration pins, refer to Reset Operation.
Based on the default strap configuration of PHY_ADD[3:0], the DP83867 PHY address will initialize to 0x00
without any external strap configuration.
Refer to Figure 20 for an example of a PHY address connection to external components. In this example, the
pins are configured as follows: RX_D2 = Strap Mode 3 and RX_D0 = Strap Mode 2. Therefore, the PHY address
strapping results in address 1001 (09h).
VDDIO
11 NŸ
RX_D0
VDDIO
2.49 NŸ
6.04 NŸ
RX_D2
2.49 NŸ
Figure 20. PHY Address Strapping Example
When operating in SGMII mode, dummy straps must be added to provide a balanced load for the SGMII
differential pairs. Therefore, for SGMII applications with the straps shown in Figure 20, the corresponding
connections for RX_D1 and RX_D3 are shown in Figure 21.

DP83867CS, DP83867IS, DP83867E
VDDIO
11 NŸ
RX_D1
VDDIO 2.49 NŸ
6.04 NŸ
RX_D3
2.49 NŸ
Figure 21. PHY Address Strapping Example for SGMII

DP83867CS, DP83867IS, DP83867E
9.5.5 Reset Operation

The DP83867 includes an internal power-on reset (POR) function and therefore does not need to be explicitly
reset for normal operation after power up. If required during normal operation, the device can be reset by a
hardware or software reset.
9.5.5.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse, with a duration of at least 1 μs, to the RESET_N pin.
This will reset the device such that all registers will be reinitialized to default values and the hardware
configuration values will be re-latched into the device (similar to the power-up/reset operation).
9.5.5.2 IEEE Software Reset

An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (address
0x0000). This bit resets the IEEE-defined standard registers.
9.5.5.3 Global Software Reset

A global software reset is accomplished by setting bit 15 of register CTRL (address 0x001F) to ‘1’. This bit resets
all the internal circuits in the PHY including IEEE-defined registers and all the extended registers. The global
software reset resets the device such that all registers are reset to default values and the hardware configuration
values are maintained.
9.5.5.4 Global Software Restart

A global software restart is accomplished by setting bit 14 of register CTRL (0x001F) to ‘1’. This action resets all
the PHY circuits except the registers in the Register File.
9.5.5.5 PCS Restart

A PCS reset is accomplished by setting bit 15 of register MMD3_PCS_CTRL (MMD3 register 0x1000). Setting
this bit will reset the MMD3 and MMD7 registers. This bit subsequently cause a soft reset via the BMCR RESET
bit (bit 15 of register address 0x0000).
9.5.6 Power Saving Modes

DP83867 supports 4 power saving modes. The details are provided below.
9.5.6.1 IEEE Power Down

The PHY is powered down but access to the PHY via MDIO-MDC pins is retained. This mode can be activated
by asserting external PWDN pin or by setting bit 11 of BMCR (Register 0x00).
The PHY can be taken out of this mode by a power cycle, software reset or by clearing the bit 11 in BMCR
register. However, the external PWDN pin should be de-asserted. If the PWDN pin is kept asserted then the PHY
will remain in power down.
9.5.6.2 Deep Power Down Mode

This same as IEEE power down but the XI pad will also be turned off. This mode can be activated by asserting
the external PWDN pin or by setting bit 11 of BMCR (Register 0x00). Before activating this mode, it is required to
set bit 7 for PHYCR (Register 0x10).
The PHY can be taken out of this mode by a power cycle, software reset or by clearing the bit 11 in BMCR
register. However, the external PWDN pin should be de-asserted. If the PWDN pin is kept asserted then the PHY
will remain in power down.
9.5.6.3 Active Sleep

In this mode all the digital and analog blocks are powered down. The PHY is automatically powered up when a
link partner is detected. This mode is useful for saving power when the link partner is down/inactive but PHY
cannot be powered down. In Active Sleep mode, the PHY will still routinely send NLP to the link partner. This
mode can be active by writing binary ‘10’ to bits [9:8] for PHYCR (Register 0x10).

DP83867CS, DP83867IS, DP83867E
9.5.6.4 Passive Sleep

This is just like Active sleep except the PHY does not send NLP. This mode can be activated by writing binary
‘11’ to bits [9:8] PHYCR (Register 0x10).

DP83867CS, DP83867IS, DP83867E
9.6 Register Maps

In the register definitions under the ‘Default’ heading, the following definitions hold true:
RW Read Write access
SC Register sets on event occurrence and Self-Clears when event ends
RW/SC ReadWrite access/Self Clearing bit
RO Read Only access
COR COR = Clear On Read
RO/COR Read Only, Clear On Read
RO/P Read Only, Permanently set to a default value
LL Latched Low and held until read, based upon the occurrence of the corresponding event
LH Latched High and held until read, based upon the occurrence of the corresponding event
9.6.1 Basic Mode Control Register (BMCR)
Table 11. Basic Mode Control Register (BMCR), Address 0x0000

BIT BIT NAME DEFAULT DESCRIPTION
15 RESET 0, RW/SC Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset
process is complete. The configuration is re-strapped.
14 LOOPBACK 0, RW Loopback:
1 = Loopback enabled.
The loopback function enables MAC transmit data to be routed to
the MAC receive data path.
Setting this bit may cause the descrambler to lose synchronization
and produce a 500 µs “dead time” before any valid data will appear
at the MII receive outputs.
13 SPEED SELECTION LSB Strap, RW Speed Select (Bits 6, 13):
When auto-negotiation is disabled writing to this bit allows the port
speed to be selected.
11 = Reserved
10 = 1000 Mbps
1 = 100 Mbps
0 = 10 Mbps
12 AUTO-NEGOTIATION ENABLE Strap, RW Auto-Negotiation Enable:
Strap controls initial value at reset.
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are
ignored when this bit is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port
speed and duplex mode.
11 POWER DOWN 0, RW Power Down:
1 = Power down.
Setting this bit powers down the PHY. Only the register block is
enabled during a power down condition. This bit is ORd with the
input from the PWRDOWN_INT pin. When the active low
PWRDOWN_INT pin is asserted, this bit will be set.

DP83867CS, DP83867IS, DP83867E
Register Maps (continued)

Table 11. Basic Mode Control Register (BMCR), Address 0x0000 (continued)
10 ISOLATE 0, RW Isolate:
1 = Isolates the Port from the MII with the exception of the serial
management.
9 RESTART AUTO- 0, RW/SC Restart Auto-Negotiation:
NEGOTIATION
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation
process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is
ignored. This bit is self-clearing and will return a value of 1 until
Auto-Negotiation is initiated, whereupon it will self-clear. Operation
of the Auto-Negotiation process is not affected by the management
entity clearing this bit.
8 DUPLEX MODE Strap, RW Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port
Duplex capability to be selected.
1 = Full Duplex operation.
0 = Half Duplex operation.
7 COLLISION TEST 0, RW Collision Test:
1 = Collision test enabled.
When set, this bit will cause the COL signal to be asserted in
response to the assertion of TX_EN within 512-bit times. The COL
signal will be de-asserted within 4-bit times in response to the de-
assertion of TX_EN.
6 SPEED SELECTION MSB Strap, RW Speed Select: See description for bit 13.
5:0 RESERVED 0 0000, RO RESERVED: Write ignored, read as 0.

DP83867CS, DP83867IS, DP83867E
9.6.2 Basic Mode Status Register (BMSR)
Table 12. Basic Mode Status Register (BMSR), Address 0x0001

15 100BASE-T4 0, RO/P 100BASE-T4 Capable:
0 = Device not able to perform 100BASE-T4 mode.
14 100BASE-TX 1, RO/P 100BASE-TX Full Duplex Capable:
FULL DUPLEX 1 = Device able to perform 100BASE-TX in full duplex mode.
13 100BASE-TX 1, RO/P 100BASE-TX Half Duplex Capable:
HALF DUPLEX 1 = Device able to perform 100BASE-TX in half duplex mode.
12 10BASE-Te 1, RO/P 10BASE-Te Full Duplex Capable:
FULL DUPLEX 1 = Device able to perform 10BASE-Te in full duplex mode.
11 10BASE-Te 1, RO/P 10BASE-Te Half Duplex Capable:
HALF DUPLEX 1 = Device able to perform 10BASE-Te in half duplex mode.
10 100BASE-T2 0, RO/P 100BASE-T2 Full Duplex Capable:
FULL DUPLEX 0 = Device not able to perform 100BASE-T2 in full duplex mode.
9 100BASE-T2 0, RO/P 100BASE-T2 Half Duplex Capable:
HALF DUPLEX 0 = Device not able to perform 100BASE-T2 in half duplex mode.
8 EXTENDED STATUS 1, RO/P 1000BASE-T Extended Status Register:
1 = Device supports Extended Status Register 0x0F.
7 RESERVED 0, RO RESERVED: Write as 0, read as 0.
6 MF PREAMBLE SUPPRESSION 1, RO/P Preamble Suppression Capable:
1 = Device able to perform management transaction with preamble
suppressed, 32-bits of preamble needed only once after reset,
invalid opcode or invalid turnaround.
0 = Normal management operation.
5 AUTO-NEGOTIATION 0, RO Auto-Negotiation Complete:
COMPLETE 1 = Auto-Negotiation process complete.
0 = Auto-Negotiation process not complete.
4 REMOTE FAULT 0, RO/LH Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset).
Fault criteria: Far End Fault Indication or notification from Link
Partner of Remote Fault.
0 = No remote fault condition detected.
3 AUTO-NEGOTIATION ABILITY 1, RO/P Auto Negotiation Ability:
1 = Device is able to perform Auto-Negotiation.
0 = Device is not able to perform Auto-Negotiation.
2 LINK STATUS 0, RO/LL Link Status:
1 = Valid link established.
0 = Link not established.
The criteria for link validity is implementation specific. The
occurrence of a link failure condition will causes the Link Status bit
to clear. Once cleared, this bit may only be set by establishing a
good link condition and a read via the management interface.

DP83867CS, DP83867IS, DP83867E
Table 12. Basic Mode Status Register (BMSR), Address 0x0001 (continued)
1 JABBER DETECT 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mbps mode.
1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the
occurrence of a jabber condition causes it to set until it is cleared by
a read to this register by the management interface or by a reset.
0 EXTENDED CAPABILITY 1, RO/P Extended Capability:
1 = Extended register capabilities.
0 = Basic register set capabilities only.

DP83867CS, DP83867IS, DP83867E
9.6.3 PHY Identifier Register #1 (PHYIDR1)

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83867. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model
revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The
PHY Identifier is intended to support network management. Texas Instruments' IEEE assigned OUI is 080028h.
Table 13. PHY Identifier Register #1 (PHYIDR1), address 0x0002

15:0 OUI_MSB 0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are
0000, RO/P stored in bits 15 to 0 of this register. The most significant two bits of
the OUI are ignored (the IEEE standard refers to these as bits 1 and
2).
9.6.4 PHY Identifier Register #2 (PHYIDR2)
Table 14. PHY Identifier Register #2 (PHYIDR2), Address 0x0003

15:10 OUI_LSB 1010 00, RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of
this register respectively.
9:4 VNDR_MDL 10 0011, RO/P Vendor Model Number:
The six bits of vendor model number are mapped from bits 9 to 4
(most significant bit to bit 9).
3:0 MDL_REV 0001, RO/P Model Revision Number:
Four bits of the vendor model revision number are mapped from bits
3 to 0 (most significant bit to bit 3). This field will be incremented for
all major device changes.

DP83867CS, DP83867IS, DP83867E
9.6.5 Auto-Negotiation Advertisement Register (ANAR)

This register contains the advertised abilities of this device as they will be transmitted to its link partner during
Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic
Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a
renegotiation. This will ensure that the new values are properly used in the Auto-Negotiation.
Table 15. Auto-Negotiation Advertisement Register (ANAR), Address 0x0004

15 NP 0, RW Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
14 RESERVED 0, RO/P RESERVED by IEEE: Writes ignored, Read as 0.
13 RF 0, RW Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
12 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0
11 ASM_DIR 0, RW Asymmetric PAUSE Support for Full Duplex Links:
The ASM_DIR bit indicates that asymmetric PAUSE is supported.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3
Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution
status is reported in PHYCR[13:12].
1 = Advertise that the DTE (MAC) has implemented both the
optional MAC control sublayer and the pause function as specified
in clause 31 and annex 31B of 802.3u.
0 = No MAC based full duplex flow control.
10 PAUSE 0, RW PAUSE Support for Full Duplex Links:
The PAUSE bit indicates that the device is capable of providing the
symmetric PAUSE functions as defined in Annex 31B.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3
Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution
status is reported in PHYCR[13:12].
1 = Advertise that the DTE (MAC) has implemented both the
optional MAC control sublayer and the pause function as specified
in clause 31 and annex 31B of 802.3u.
0 = No MAC based full duplex flow control.
9 T4 0, RO/P 100BASE-T4 Support:
1 = 100BASE-T4 is supported by the local device.
0 = 100BASE-T4 not supported.
8 TX_FD Strap, RW 100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the local device.
0 = 100BASE-TX Full Duplex not supported.
7 TX Strap, RW 100BASE-TX Support:
1 = 100BASE-TX is supported by the local device.
0 = 100BASE-TX not supported.
6 10_FD Strap, RW 10BASE-Te Full Duplex Support:
1 = 10BASE-Te Full Duplex is supported by the local device.
0 = 10BASE-Te Full Duplex not supported.

DP83867CS, DP83867IS, DP83867E
Table 15. Auto-Negotiation Advertisement Register (ANAR), Address 0x0004 (continued)

5 10 Strap, RW 10BASE-Te Support:
1 = 10BASE-Te is supported by the local device.
0 = 10BASE-Te not supported.
4:0 SELECTOR 0 0001, RW Protocol Selection Bits:
These bits contain the binary encoded protocol selector supported
by this port. <00001> indicates that this device supports IEEE
802.3u.

DP83867CS, DP83867IS, DP83867E
9.6.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The
content changes after the successful auto-negotiation if Next-pages are supported.
Table 16. Auto-Negotiation Link Partner Ability Register (ANLPAR), Address 0x0005
15 NP 0, RO Next Page Indication:
0 = Link Partner does not desire Next Page Transfer.
1 = Link Partner desires Next Page Transfer.
14 ACK 0, RO Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Auto-Negotiation state machine will automatically control this bit
based on the incoming FLP bursts.
13 RF 0, RO Remote Fault:
1 = Remote Fault indicated by Link Partner.
0 = No Remote Fault indicated by Link Partner.
12 RESERVED 0, RO RESERVED for Future IEEE use: Write as 0, read as 0.
11 ASM_DIR 0, RO ASYMMETRIC PAUSE:
1 = Asymmetric pause is supported by the Link Partner.
0 = Asymmetric pause is not supported by the Link Partner.
10 PAUSE 0, RO PAUSE:
1 = Pause function is supported by the Link Partner.
0 = Pause function is not supported by the Link Partner.
9 T4 0, RO 100BASE-T4 Support:
1 = 100BASE-T4 is supported by the Link Partner.
0 = 100BASE-T4 not supported by the Link Partner.
8 TX_FD 0, RO 100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the Link Partner.
0 = 100BASE-TX Full Duplex not supported by the Link Partner.
7 TX 0, RO 100BASE-TX Support:
1 = 100BASE-TX is supported by the Link Partner.
0 = 100BASE-TX not supported by the Link Partner.
6 10_FD 0, RO 10BASE-Te Full Duplex Support:
1 = 10BASE-Te Full Duplex is supported by the Link Partner.
0 = 10BASE-Te Full Duplex not supported by the Link Partner.
5 10 0, RO 10BASE-Te Support:
1 = 10BASE-Te is supported by the Link Partner.
0 = 10BASE-Te not supported by the Link Partner.
4:0 SELECTOR 0 0000, RO Protocol Selection Bits:
Link Partner's binary encoded protocol selector.

DP83867CS, DP83867IS, DP83867E
9.6.7 Auto-Negotiate Expansion Register (ANER)

This register contains additional Local Device and Link Partner status information.
Table 17. Auto-Negotiate Expansion Register (ANER), Address 0x0006

15:7 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
6 RX_NEXT_PAGE_LOC_ABLE 1, RO Receive Next Page Location Able:
1 = Received Next Page storage location is specified by bit 6.5.
0 = Received Next Page storage location is not specified by bit 6.5.
5 RX_NEXT_PAGE_STOR_LOC 1, RO Receive Next Page Storage Location:
1 = Link Partner Next Pages are stored in register 8.
0 = Link Partner Next Pages are stored in register 5.
4 PDF 0, RO Parallel Detection Fault:
1 = A fault has been detected via the Parallel Detection function.
0 = A fault has not been detected.
3 LP_NP_ABLE 0, RO Link Partner Next Page Able:
1 = Link Partner does support Next Page.
0 = Link Partner does not support Next Page.
2 NP_ABLE 1, RO/P Next Page Able:
1 = Indicates local device is able to send additional Next Pages.
1 PAGE_RX 0, RO/COR Link Code Word Page Received:
1 = Link Code Word has been received, cleared on a read.
0 = Link Code Word has not been received.
0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able:
1 = Indicates that the Link Partner supports Auto-Negotiation.
0 = Indicates that the Link Partner does not support Auto-
Negotiation.

DP83867CS, DP83867IS, DP83867E
9.6.8 Auto-Negotiation Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.
Table 18. Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x0007
0 = No other Next Page Transfer desired.
1 = Another Next Page desired.
1 = Acknowledge reception of link code word
0 = Do not acknowledge of link code word.
13 MP 1, RW Message Page:
1 = Current page is a Message Page.
0 = Current page is an Unformatted Page.
12 ACK2 0, RW Acknowledge2:
1 = Will comply with message.
0 = Cannot comply with message.
Acknowledge2 is used by the next page function to indicate that
Local Device has the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word
was 0.
was 1.
Toggle is used by the Arbitration function within Auto-Negotiation to
ensure synchronization with the Link Partner during Next Page
exchange. This bit shall always take the opposite value of the
Toggle bit in the previously exchanged Link Code Word.
10:0 CODE 000 0000 0001, Code:
RW
This field represents the code field of the next page transmission. If
the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a "Message Page”, as defined in Annex 28C of IEEE
802.3u. Otherwise, the code shall be interpreted as an "Unformatted
Page”, and the interpretation is application specific.
The default value of the CODE represents a Null Page as defined in
Annex 28C of IEEE 802.3u.

DP83867CS, DP83867IS, DP83867E
9.6.9 Auto-Negotiation Next Page Receive Register (ANNPRR)

This register contains the next page information sent by the Link Partner during Auto-Negotiation.
Table 19. Auto-Negotiation Next Page Transmit Register (ANNPTR), Address 0x0008
0 = No other Next Page Transfer desired by the link partner.
1 = Another Next Page desired by the link partner.
1 = Acknowledge reception of link code word by the link partner.
0 = Link partner does not acknowledge reception of link code word.
13 MP 1, RW Message Page:
1 = Received page is a Message Page.
0 = Received page is an Unformatted Page.
12 ACK2 0, RW Acknowledge2:
1 = Link partner sets the ACK2 bit.
0 = Link partner coes not set the ACK2 bit.
Acknowledge2 is used by the next page function to indicate that link
partner has the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:
was 0.
was 1.
Toggle is used by the Arbitration function within Auto-Negotiation to
ensure synchronization with the Link Partner during Next Page
exchange. This bit shall always take the opposite value of the
Toggle bit in the previously exchanged Link Code Word.
10:0 CODE 000 0000 0001, Code:
RW
This field represents the code field of the next page transmission. If
the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a "Message Page”, as defined in Annex 28C of IEEE
802.3u. Otherwise, the code shall be interpreted as an "Unformatted
Page”, and the interpretation is application specific.
The default value of the CODE represents a Null Page as defined in
Annex 28C of IEEE 802.3u.

DP83867CS, DP83867IS, DP83867E
9.6.10 1000BASE-T Configuration Register (CFG1)
Table 20. Configuration Register 1 (CFG1), Address 0x0009

15:13 TEST MODE 000, RW Test Mode Select:
111 = Test Mode 7 - Repetitive {Pulse, 63 zeros}
110 = Test Mode 6 - Repetitive 0001 sequence
101 = Test Mode 5 - Scrambled MLT3 Idles
100 = Test Mode 4 - Transmit Distortion Test
011 = Test Mode 3 - Transmit Jitter Test (Slave Mode)
010 = Test Mode 2 - Transmit Jitter Test (Master Mode)
001 = Test Mode 1 - Transmit Waveform Test
000 = Normal Mode
12 MASTER / SLAVE MANUAL 0, RW Enable Manual Master / Slave Configuration:
CONFIGURATION
1 = Enable Manual Master/Slave Configuration control.
0 = Disable Manual Master/Slave Configuration control.
Using the manual configuration feature may prevent the PHY from
establishing link in 1000Base-T mode if a conflict with the link
partner’s setting exists.
11 MASTER / SLAVE 0, RW Manual Master / Slave Configuration Value:
CONFIGURATION VALUE
1 = Set PHY as MASTER when register 09h bit 12 = 1.
0 = Set PHY as SLAVE when register 09h bit 12 = 1.
Using the manual configuration feature may prevent the PHY from
establishing link in 1000Base-T mode if a conflict with the link
partner’s setting exists.
10 PORT TYPE 0, RW Advertise Device Type: Multi or single port:
1 = Multi-port device.
0 = Single-port device.
9 100BASE-T FULL DUPLEX 0, RW Advertise 1000BASE-T Full Duplex Capable:
1 = Advertise 1000Base-T Half Duplex ability.
0 = Do not advertise 1000Base-T Half Duplex ability.
8 1000BASE-T HALF DUPLEX 0, RW Advertise 1000BASE-T Half Duplex Capable:
1 = Advertise 1000Base-T Half Duplex ability.
0 = Do not advertise 1000Base-T Half Duplex ability.
7 TDR AUTO RUN 0, RW Automatic TDR on Link Down:
1 = Enable execution of TDR procedure after link down event.
0 = Disable automatic execution of TDR.
6:0 RESERVED 000 0000, RO RESERVED: Write ignored, read as 0.

DP83867CS, DP83867IS, DP83867E
9.6.11 Status Register 1 (STS1)
Table 21. Status Register 1 (STS1) Address 0x000A

15 MASTER / SLAVE 0, RO, LH, COR Master / Slave Manual Configuration Fault Detected:
CONFIGURATION FAULT
1 = Manual Master/Slave Configuration fault detected.
0 = No Manual Master/Slave Configuration fault detected.
14 MASTER / SLAVE 0, RO Master / Slave Configuration Results:
CONFIGURATION
1 = Configuration resolved to MASTER.
RESOLUTION
0 = Configuration resolved to SLAVE.
13 LOCAL RECEIVER STATUS 0, RO Local Receiver Status:
1 = Local receiveris OK.
0 = Local receiveris not OK.
12 REMOTE RECEIVER STATUS 0, RO Remote Receiver Status:
1 = Remote receiver is OK.
0 = Remote receiver is not OK.
11 100BASE-T FULL DUPLEX 0, RO Link Partner 1000BASE-T Full Duplex Capable:
1 = Link Partner capable of 1000Base-T Full Duplex.
0 = Link partner not capable of 1000Base-T Full Duplex.
10 1000BASE-T HALF DUPLEX 0, RO Link Partner 1000BASE-T Half Duplex Capable:
1 = Link Partner capable of 1000Base-T Half Duplex.
0 = Link partner not capable of 1000Base-T Half Duplex.
9:8 RESERVED 00, RO RESERVED by IEEE: Writes ignored, read as 0.
7:0 IDLE ERROR COUNTER 0000 0000, RO, 1000BASE-T Idle Error Counter
COR
9.6.12 Extended Register Addressing

REGCR (0x000D) and ADDAR (0x000E) allow read/write access to the extended register set (addresses above
0x001F) using indirect addressing.
• REGCR [15:14] = 00: A write to ADDAR modifies the extended register set address register. This address
register must be initialized in order to access any of the registers within the extended register set.
• •REGCR [15:14] = 01: A read/write to ADDAR operates on the register within the extended register set
selected (pointed to) by the value in the address register. The address register contents (pointer) remain
unchanged.
• REGCR [15:14] = 10: A read/write to ADDAR operates on the register within the extended register set
selected (pointed to) by the value in the address register. After that access is complete, for both reads and
writes, the value in the address register is incremented.
• REGCR [15:14] = 11: A read/write to ADDAR operates on the register within the extended register set
selected (pointed to) by the value in the address register. After that access is complete, for write accesses
only, the value in the address register is incremented. For read accesses, the value of the address register
remains unchanged.

DP83867CS, DP83867IS, DP83867E
9.6.12.1 Register Control Register (REGCR)

This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device
address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate MMD. REGCR
also contains selection bits for auto increment of the data register. This register contains the device address to
be written to access the extended registers. Write 0x1F into bits 4:0 of this register. REGCR also contains
selection bits (15:14) for the address auto-increment mode of ADDAR.
Table 22. Register Control Register (REGCR), address 0x000D

15:14 Function 0, RW 00 = Address
01 = Data, no post increment
10 = Data, post increment on read and write
11 = Data, post increment on write only
13:5 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
4:0 DEVAD 0, RW Device Address: In general, these bits [4:0] are the device address
DEVAD that directs any accesses of ADDAR register (0x000E) to
the appropriate MMD. Specifically, the DP83867 uses the vendor
specific DEVAD [4:0] = “11111” for accesses. All accesses through
registers REGCR and ADDAR should use this DEVAD.
Transactions with other DEVAD are ignored.
9.6.12.2 Address or Data Register (ADDAR)

This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register (0x000D) to
provide the access by indirect read/write mechanism to the extended register set.
Table 23. Address or Data Register (ADDAR) address 0x000E

15:0 Address / Data 0, RW If REGCR register 15:14 = 00, holds the MMD DEVAD's address
register, otherwise holds the MMD DEVAD's data register
9.6.13 1000BASE-T Status Register (1KSCR)
Table 24. 1000BASE-T Status Register (1KSCR) address 0x000F

15 1000BASE-X FULL DUPLEX 0, RO/P 1000BASE-X Full Duplex Support:
1 = 1000BASE-X Full Duplex is supported by the local device.
0 = 1000BASE-X Full Duplex is not supported by the local device.
14 1000BASE-X HALF DUPLEX 1000BASE-X Half Duplex Support:
0, RO/P 1 = 1000BASE-X Half Duplex is supported by the local device.
0 = 1000BASE-X Half Duplex is not supported by the local device.
13 1000BASE-T FULL DUPLEX 1000BASE-T Full Duplex Support:
1, RO/P 1 = 1000BASE-T Full Duplex is supported by the local device.
0 = 1000BASE-T Full Duplex is not supported by the local device.
12 1000BASE-T HALF DUPLEX 1000BASE-T Half Duplex Support:
1, RO/P 1 = 1000BASE-T Half Duplex is supported by the local device.
0 = 1000BASE-T Half Duplex is not supported by the local device.
11:0 RESERVED 00, RO RESERVED by IEEE: Writes ignored, read as 0.

DP83867CS, DP83867IS, DP83867E
9.6.14 PHY Control Register (PHYCR)
Table 25. PHY Control Register (PHYCR), Address 0x0010

15:14 TX FIFO Depth 1, RW TX FIFO Depth:
11 = 8 bytes/nibbles (1000Mbps/Other Speeds)
Note: FIFO is enabled only in the following modes:
1000BaseT + GMII
10BaseT/100BaseTX/1000BaseT + SGMII
13:12 RX FIFO Depth 1, RW RX FIFO Depth:
Note: FIFO is enabled only in SGMII
11 SGMI_EN 0, RW SGMII Enable:
1 = Enable SGMII
0 = Disable SGMII
10 FORCE_LINK_GOOD 0, RW Force Link Good:
1 = Force link good according to the selected speed.
0 = Normal operation
9:8 POWER_SAVE_MODE 0, RW Power Saving Modes:
11 = Passive Sleep mode: Power down all digital and analog
blocks.
10 =Active Sleep mode: Power down all digital and analog blocks.
Automatic power-up is performed when link partner is detected. Link
pulses are transmitted approximately once per 1.4 Sec in this mode
to wake up any potential link partner.
01 = IEEE mode: power down all digital and analog blocks.
Note: If DISABLE_CLK_125 (bit [4]of this register) is set to zero, the
PLL is also powered down.
00 = Normal mode
7 DEEP_POWER_DOWN_EN 0, RW Deep power down mode enable
1 = When power down is initiated via assertion of the external
Power Down pin or via the POWER_DOWN bit in the BMCR, the
device will enter a deep power down mode.
6:5 MDI_CROSSOVER 11, RO MDI Crosssover Mode:
1x = Enable automatic crossover
1 = Manual MDI-X configuration
0 = Manual MDI configuration
4 DISABLE_CLK_125 0, RW Disable 125MHz Clock:
This bit may be used in conjunction with POWER_SAVE_MODE
(bits 9:8 of this register).
1 = Disable CLK125.
0 = Enable CLK125.
3 RESERVED 1, RO RESERVED: Writes ignored, read as 1.
2 STANDBY_MODE 0, RW Standby Mode:

DP83867CS, DP83867IS, DP83867E
Table 25. PHY Control Register (PHYCR), Address 0x0010 (continued)

1 = Enable standby mode. Digital and analog circuitry are powered
up, but no link can be established.
1 LINE_DRIVER_INV_EN 0, RW Line Driver Inversion Enable:
1 = Invert Line Driver Transmission.
0 DISABLE_JABBER 0, RW Disable Jabber
1 = Disable Jabber function.
0 = Enable Jabber function.

DP83867CS, DP83867IS, DP83867E
9.6.15 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed
information.
Table 26. PHY Status Register (PHYSTS), Address 0x0011

15:14 SPEED SELECTION 0, RO Speed Select Status:
These two bits indicate the speed of operation as determined by
Auto-negotiation or as set by manual configuration.
11 = Reserved
10 = 1000 Mbps
01 = 100 Mbps
00 = 10 Mbps
13 DUPLEX MODE 0, RO Duplex Mode Status:
1 = Full Duplex
0 = Half Duplex.
12 PAGE RECEIVED 0, RO, LH, COR Page Received:
This bit is latched high and will be cleared upon a read.
1 = Page received.
0 = No page received.
11 SPEED DUPLEX RESOLVED 0, RO Speed Duplex Resolution Status:
1 = Auto-Negotiation has completed or is disabled.
0 = Auto-Negotiation is enabled and has not completed.
10 LINK_STATUS 0, RO Link Status:
1 = Link is up.
0 = Link is down.
9 MDI_X_MODE_CD 0, RO MDI/MDIX Resolution Status for C and D Line Driver Pairs:
1 = Resolved as MDIX
0 = Resolved as MDI.
8 MDI_X_MODE_AB 0, RO MDI/MDIX Resolution Status for A and B Line Driver Pairs:
1 = Resolved as MDIX
0 = Resolved as MDI.
7 SPEED_OPT_STATUS 0, RO Speed Optimization Status:
1 = Auto-Negotiation is currently being performed with Speed
Optimization masking 1000BaseT abilities (Valid only during Auto-
Negotiation).
0 = Auto-Negotiation is currently being performed without Speed
Optimization.
6 SLEEP_MODE 0, RO Sleep Mode Status:
1 = Device currently in sleep mode.
0 = Device currently in active mode.
5:2 WIRE_CROSS 0, RO Crossed Wire Indication:
Indicates channel polarity in 1000BASE-T linked status. Bits [5:2]
correspond to channels [D,C,B,A], respectively.
1 = Channel polarity is reversed.
0 = Channel polarity is normal.

DP83867CS, DP83867IS, DP83867E
Table 26. PHY Status Register (PHYSTS), Address 0x0011 (continued)

1 POLARITY STATUS 0, RO Polarity Status:
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
0 JABBER DETECT 0, RO Jabber Detect: This bit only has meaning in 10 Mbps mode.
This bit is a duplicate of the Jabber Detect bit in the BMSR register,
except that it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.

DP83867CS, DP83867IS, DP83867E
9.6.16 MII Interrupt Control Register (MICR)

This register implements the Interrupt PHY Specific Control register. The individual interrupt events must be
enabled by setting bits in the Interrupt Status and Event Control Register (ISR).
Table 27. MII Interrupt Control Register (MICR), Address 0x0012

15 AUTONEG_ERR_INT_EN 0, RW Enable Auto-Negotiation Error Interrupt:
1 = Enable Auto-Negotiation Error interrupt.
0 = Disable Auto-Negotiation Error interrupt.
14 SPEED_CHNG_INT_EN 0, RW Enable Speed Change Interrupt:
1 = Enable Speed Change interrupt.
0 = Disable Speed Change interrupt.
13 DUPLEX_MODE_CHNG_INT_E 0, RW Enable Duplex Mode Change Interrupt:
N
1 = Enable Duplex Mode Change interrupt.
0 = Disable Duplex Mode Change interrupt.
12 PAGE_RECEIVED_INT_EN 0, RW Enable Page Received Interrupt:
1 = Enable Page Received Interrupt.
0 = Disable Page Received Interrupt.
11 AUTONEG_COMP_INT_EN 0, RW Enable Auto-Negotiation Complete Interrupt:
1 = Enable Auto-Negotiation Complete Interrupt.
0 = Disable Auto-Negotiation Complete Interrupt.
10 LINK_STATUS_CHNG_INT_EN 0, RW Enable Link Status Change Interrupt:
1 = Enable Link Status Change interrupt.
0 = Disable Link Status Change interrupt.
9 RESERVED 0, RO RESERVED
8 FALSE_CARRIER_INT_EN 0, RW Enable False Carrier Interrupt:
1 = Enable False Carrier interrupt.
0 = Disable False Carrier interrupt.
6 MDI_CROSSOVER_CHNG_INT 0, RW Enable MDI Crossover Change Interrupt:
_EN
1 = Enable MDI Crossover Change interrupt.
0 = Disable MDI Crossover Change interrupt.
5 SPEED_OPT_EVENT_INT_EN 0, RW Enable Speed Optimization Event Interrupt:
1 = Enable Speed Optimization Event Interrupt.
0 = Disable Speed Optimization Event Interrupt.
4 SLEEP_MODE_CHNG_INT_EN 0, RW Enable Sleep Mode Change Interrupt:
1 = Enable Sleep Mode Change Interrupt.
0 = Disable Sleep Mode Change Interrupt.
3 WOL_INT_EN 0, RW Enable Wake on LAN Interrupt:
1 = Enable Wake on LAN Interrupt.
0 = Disable Wake on LAN Interrupt.

DP83867CS, DP83867IS, DP83867E
Table 27. MII Interrupt Control Register (MICR), Address 0x0012 (continued)
2 XGMII_ERR_INT_EN 0, RW Enable xGMII Error Interrupt:
1 = Enable xGMII Error Interrupt.
0 = Disable xGMII Error Interrupt.
1 POLARITY_CHNG_INT_EN 0, RW Enable Polarity Change Interrupt:
1 = Enable Polarity Change interrupt.
0 = Disable Polarity Change interrupt.
0 JABBER_INT_EN 0, RW Enable Jabber Interrupt:
1 = Enable Jabber interrupt.
0 = Disable Jabber interrupt.

DP83867CS, DP83867IS, DP83867E
9.6.17 Interrupt Status Register (ISR)

This register contains event status for the interrupt function. If an event has occurred since the last read of this
register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt
will be generated if the event occurs. The ICR register controls must also be set to allow interrupts. The status
indications in this register will be set even if the interrupt is not enabled.
Table 28. Interrupt Status Register (ISR), Address 0x0013

15 AUTONEG_ERR_INT 0, RO, LH, COR Auto-Negotiation Error Interrupt:
1 = Auto-Negotiation Error interrupt is pending and is cleared by the
current read.
0 = No Auto-Negotiation Error interrupt.
14 SPEED_CHNG_INT 0, RO, LH, COR Speed Change Interrupt:
1 = Speed Change interrupt is pending and is cleared by the current
read.
0 = No Speed Change interrupt.
13 DUPLEX_MODE_CHNG_INT 0, RO, LH, COR Duplex Mode Change Interrupt:
1 = Duplex Mode Change interrupt is pending and is cleared by the
current read.
0 = No Duplex Mode Change interrupt.
12 PAGE_RECEIVED_INT 0, RO, LH, COR Page Received Interrupt:
1 = Page Received Interrupt is pending and is cleared by the
current read.
0 = No Page Received Interrupt is pending.
11 AUTONEG_COMP_INT 0, RO, LH, COR Auto-Negotiation Complete Interrupt:
1 = Auto-Negotiation Complete Interrupt is pending and is cleared
by the current read.
0 = No Auto-Negotiation Complete Interrupt is pending.
10 LINK_STATUS_CHNG_INT 0, RO, LH, COR Link Status Change Interrupt:
1 = Link Status Change interrupt is pending and is cleared by the
current read.
0 = No Link Status Change interrupt is pending.
8 FALSE_CARRIER_INT 0, RO, LH, COR False Carrier Interrupt:
1 = False Carrier interrupt is pending and is cleared by the current
read.
0 = No False Carrier interrupt is pending.
6 MDI_CROSSOVER_CHNG_INT 0, RO, LH, COR MDI Crossover Change Interrupt:
1 = MDI Crossover Change interrupt is pending and is cleared by
the current read.
0 = No MDI Crossover Change interrupt is pending.

DP83867CS, DP83867IS, DP83867E
Table 28. Interrupt Status Register (ISR), Address 0x0013 (continued)

5 SPEED_OPT_EVENT_INT 0, RO, LH, COR Speed Optimization Event Interrupt:
1 = Speed Optimization Event Interrupt is pending and is cleared by
the current read.
0 = No Speed Optimization Event Interrupt is pending.
4 SLEEP_MODE_CHNG_INT 0, RO, LH, COR Sleep Mode Change Interrupt:
1 = Sleep Mode Change Interrupt is pending and is cleared by the
current read.
0 = No Sleep Mode Change Interrupt is pending.
3 WOL_INT 0, RO, LH, COR Wake on LAN Interrupt:
1 = Wake on LAN Interrupt is pending.
0 = No Wake on LAN Interrupt is pending.
2 XGMII_ERR_INT 0, RO, LH, COR xGMII Error Interrupt:
(1)
1 = xGMII Error Interrupt is pending and is cleared by the current
read.
0 = No xGMII Error Interrupt is pending.
1 POLARITY_CHNG_INT 0, RO, LH, COR Polarity Change Interrupt:
1 = Polarity Change interrupt is pending and is cleared by the
current read.
0 = No Polarity Change interrupt is pending.
0 JABBER_INT 0, RO, LH, COR Jabber Interrupt:
1 = Jabber interrupt is pending and is cleared by the current read.
0 = No Jabber interrupt is pending.
(1) xGMII: RGMII or SGMII

DP83867CS, DP83867IS, DP83867E
9.6.18 Configuration Register 2 (CFG2)

13 INTERRUPT_POLARITY 1, RW Configure Interrupt Polarity:
1 = Interrupt pin is active low.
0 = Interrupt pin is active high.
11:10 SPEED_OPT_ATTEMPT_CNT 10, RO Speed Optimization Attempt Count:
Selects the number of 1000BASE-T link establishment attempt
failures prior to performing Speed Optimization.
11 = 8
10 = 4
01 = 2
00 = 1
9 SPEED_OPT_EN 1, RW Speed Optimization Enable:
1 = Enable Speed Optimization.
0 = Disable Speed Optimization.
8 SPEED_OPT_ENHANCED_EN 1, RW Speed Optimization Enhanced Mode Enable:
In enhanced mode, speed is optimized if energy is not detected in
channels C and D.
1 = Enable Speed Optimization enhanced mode.
0 = Disable Speed Optimization enhanced mode.
7 SGMII_AUTONEG_EN 1, RW SGMII Auto-Negotiation Enable:
1 = Enable SGMII Auto-Negotaition.
0 = Disable SGMII Auto-Negotaition.
6 SPEED_OPT_10M_EN 1, RW Enable Speed Optimization to 10BASE-Te:
1 = Enable speed optimization to 10BASE-Te if link establishment
fails in 1000BASE-T and 100BASE-TX .
0 = Disable speed optimization to 10BASE-Te.
5:0 RESERVED 0, RO RESERVED
9.6.19 Receiver Error Counter Register (RECR)
Table 30. Receiver Error Counter Register (RECR), Address 0x0015

15:0 RXERCNT[15:0] 0, RO, WSC RX_ER Counter:
Receive error counter. This register saturates at the maximum value
of 0xFFFF. It is cleared by dummy write to this register.

DP83867CS, DP83867IS, DP83867E
9.6.20 BIST Control Register (BISCR)

This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random
Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact
loopback point in the signal chain is also done in this register.
Table 31. BIST Control Register (BISCR), Address 0x0016

15 PRBS_COUNT_MODE 0, RW PRBS Continuous Mode:
1 = Continuous mode enabled. When one of the PRBS counters
reaches the maximum value, a pulse is generated and the counter
starts counting from zero again. This bit must be set for proper
PRBS operation.
0 = PRBS continuous mode disabled. PRBS operation is not
supported for this setting.
14 GEN_PRBS_PACKET 0, RW Generated PRBS Packets:
1 = When the packet generator is enabled, it will generate
continuous packets with PRBS data. When the packet generator is
disabled, the PRBS checker is still enabled.
0 = When the packet generator is enabled, it will generate a single
packet with constant data. PRBS generation and checking is
disabled.
13 PACKET_GEN_64BIT_MODE 0, RW BIST Packet Size:
1 = Transmit 64 byte packets in packet generation mode.
0 = Transmit 1518 byte packets in packet generation mode
12 PACKET_GEN_EN 0, RW Packet BIST Enable:
1 = Enable packet/PRBS generator
0 = Disable packet/PRBS generator
7 REV_LOOP_RX_DATA_CTRL 0, RW Reverse Loopback Receive Data Control:
This bit may only be set in reverse loopback mode.
1 = Send RX packets to MAC in reverse loop
0 = Suppress RX packets to MAC in reverse loop
6 MII_LOOP_TX_DATA_CTRL 0, RW MII Loopback Transmit Data Control:
This bit may only be set in MII loopback mode.
1 = Transmit data to MDI in MII loop
0 = Suppress data to MDI in MII loop
5:2 LOOPBACK_MODE 0, RW Loopback Mode Select:
PCS Loopback must be disabled (Bits [1:0] =00) prior to selecting
the loopback mode.
1000: Reverse loop
0100: External loop
0010: Analog loop
0001: Digital loop

DP83867CS, DP83867IS, DP83867E
Table 31. BIST Control Register (BISCR), Address 0x0016 (continued)

1:0 PCS_LOOPBACK 0, RW PCS Loopback Select:
When configured for 100Base-TX:
11: Loop after MLT3 encoder (full TX/RX path)
10: Loop after scrambler, before MLT3 encoder
01: Loop before scrambler
When configured for 1000Base-T:
x1: Loop before 1000Base-T signal processing.

DP83867CS, DP83867IS, DP83867E
9.6.21 Status Register 2 (STS2)
Table 32. Status Register 2 (STS2), Address 0x0017

11 PRBS_LOCK 0, RO PRBS Lock Status:
1 = PRBS checker is locked to the received byte stream.
0 = PRBS checker is not locked.
10 PRBS_LOCK_LOST 0, RO, LH, COR PRBS Lock Lost:
1 = PRBS checker has lost lock.
0 = PRBS checker has not lost lock.
9 PKT_GEN_BUSY 0, RO Packet Generator Busy:
1 = Packet generation is in process.
0 = Packet generation is not in process.
8 SCR_MODE_MASTER_1G 0, RO Gigabit Master Scramble Mode:
1 = 1G PCS (master) is in legacy encoding mode.
0 = 1G PCS (master) is in normal encoding mode..
7 SCR_MODE_MASTER_1G 0, RO Gigabit Slave Scramble Mode:
1 = 1G PCS (slave) is in legacy encoding mode.
0 = 1G PCS (slave) is in normal encoding mode..
6 CORE_PWR_MODE 0, RO Core Power Mode:
1 = Core is in normal power mode.
0 = Core is power down mode or in sleep mode.

DP83867CS, DP83867IS, DP83867E
9.6.22 LED Configuration Register 1 (LEDCR1)

This register maps the LED functions to the corresponding pins.
Table 33. LED Configuration Register 1 (LEDCR1), Address 0x0018

15:12 LED_GPIO_SEL RW, 0110 Source of the GPIO LED:
1111: Reserved
1110: Receive Error
1101: Receive Error or Transmit Error
1100: RESERVED
1011: Link established, blink for transmit or receive activity
1010: Full duplex
1001: 100/1000BT link established
0111: 10BT link established
0110: 100 BTX link established
0100: Collision detected
0011: Receive activity
0010: Transmit activity
0001: Receive or Transmit activity
0000: Link established
11:8 LED_2_SEL RW, 0001 Source of LED_2:
1111: Reserved
1110: Receive Error
1100: RESERVED
1010: Full duplex

DP83867CS, DP83867IS, DP83867E
Table 33. LED Configuration Register 1 (LEDCR1), Address 0x0018 (continued)

1111: Reserved
1110: Receive Error
1100: RESERVED
1010: Full duplex
1111: Reserved
1110: Receive Error
1100: RESERVED
1010: Full duplex

DP83867CS, DP83867IS, DP83867E
9.6.23 LED Configuration Register 2 (LEDCR2)

This register provides the ability to directly control any or all LED outputs.
Table 34. LED Configuration Register 2 (LEDCR2), Address 0x0019

14 LED_GPIO_POLARITY 1, RW GPIO LED Polarity:
1 = Active high
0 = Active low
13 LED_GPIO_DRV_VAL 0, RW GPIO LED Drive Value:
Value to force on GPIO LED
This bit is only valid if enabled via LED_GPIO_DRV_EN.
12 LED_GPIO_DRV_EN 0, RW GPIO LED Drive Enable:
1 = Force the value of the LED_GPIO_DRV_VAL bit onto the GPIO
LED.
10 LED_2_POLARITY 1, RW LED_2 Polarity:
1 = Active high
0 = Active low
9 LED_2_DRV_VAL 0, RW LED_2 Drive Value:
Value to force on LED_2
This bit is only valid if enabled via LED_2_DRV_EN.
8 LED_2_DRV_EN 0, RW LED_2 Drive Enable:
1 = Force the value of the LED_2_DRV_VAL bit onto LED_2.
1 = Active high
0 = Active low
1 = Active high
0 = Active low

DP83867CS, DP83867IS, DP83867E
9.6.24 LED Configuration Register (LEDCR3)

This register controls the LED blink rate and stretching.
Table 35. LED Configuration Register 3 (LEDCR3), Address 0x001A

2 LEDS_BYPASS_STRETCHING 0, RW Bypass LED Stretching:
1 = Bypass LED Stretching
1:0 LEDS_BLINK_RATE 10, RW LED Blink Rate:
11: 2Hz (500mSec)
10: 5Hz (200mSec)
01: 10Hz (100mSec)
00 = 20Hz (50mSec)
Table 36. Configuration Register 3 (CFG3), Address 0x001E

15 Fast Link-Up in Parallel Detect 0, RW Fast Link-Up in Parallel Detect Mode:
1 = Enable Fast Link-Up time During Parallel Detection
0 = Normal Parallel Detection link establishment
In Fast Auto MDI-X this bit is automatically set.
14 Fast AN Enable 0, RW Fast Auto-Negotiation Enable:
1 = Enable Fast Auto-Negotiation mode – The PHY auto-
negotiates using Timer setting according to Fast AN Sel bits
0 = Disable Fast Auto-Negotiation mode – The PHY auto-
negotiates using normal Timer setting
Adjusting these bits reduces the time it takes to Auto-negotiate
between two PHYs. Note: When using this option care must be
taken to maintain proper operation of the system. While shortening
these timer intervals may not cause problems in normal operation,
there are certain situations where this may lead to problems.
13:12 Fast AN Sel 0, RW Fast Auto-Negotiation Select bits:
Fast AN Break Link Fall Auto-Neg
Select Link Inhibit Wait
Timer(ms) Timer(ms) Timer(ms)
<00> 80 50 35
<01> 120 75 50
<10> 240 150 100
<11> NA NA NA
Adjusting these bits reduces the time it takes to Auto-negotiate
between two PHYs. In Fast AN mode, both PHYs should be
configured to the same configuration. These 2 bits define the
duration for each state of the Auto Negotiation process according
to the table above. The new duration time must be enabled by
setting “Fast AN En” - bit 4 of this register. Note: Using this mode
in cases where both link partners are not configured to the same
Fast Auto-negotiation configuration might produce scenarios with
unexpected behavior.

DP83867CS, DP83867IS, DP83867E
Table 36. Configuration Register 3 (CFG3), Address 0x001E (continued)

11 Extended FD Ability 0, RW Extended Full-Duplex Ability:
1 = Force Full-Duplex while working with link partner in forced
100B-TX. When the PHY is set to Auto-Negotiation or Force 100B-
TX and the link partner is operated in Force 100B-TX, the link is
always Full Duplex
0 = Disable Extended Full Duplex Ability. Decision to work in Full
Duplex or Half Duplex mode follows IEEE specification.
9 Robust Auto-MDIX 0, RW Robust Auto-MDIX:
1 =Enable Robust Auto MDI/MDIX resolution
0 = Normal Auto MDI/MDIX mode
If link partners are configured to operational modes that are not
supported by normal Auto MDI/MDIX mode (like Auto-Neg versus
Force 100Base-TX or Force 100Base-TX versus Force 100Base-
TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX
resolution and prevents deadlock.
8 Fast Auto-MDIX 0, RW Fast Auto MDI/MDIX:
1 = Enable Fast Auto MDI/MDIX mode
0 = Normal Auto MDI/MDIX mode
If both link partners are configured to work in Force 100Base-TX
mode (Auto-Negotiation is disabled), this mode enables Automatic
MDI/MDIX resolution in a short time.
7 INT_OE 0, RW Interrupt Output Enable:
1 = INTN/PWDNN Pad is an Interrupt Output.
0 = INTN/PWDNN Pad in a Power Down Input.
6 FORCE_INTERRUPT 0, RW Force Interrupt:
1 = Assert interrupt pin.
0 = Normal interrupt mode.
2 TDR_FAIL 0, RO TDR Failure:
1 = TDR failed.
0 = Normal TDR operation.
1 TDR_DONE 1, RO TDR Done:
1 = TDR has completed.
0 = TDR has not completed.
0 TDR_START 0, RW TDR Start:
1 = Start TDR.

DP83867CS, DP83867IS, DP83867E
9.6.26 Control Register (CTRL)
Table 37. Control Register (CTRL), Address 0x001F

15 SW_RESET 0, RW, SC Software Reset:
1 = Perform a full reset, including registers.
14 SW_RESTART 0, RW, SC Software Restart:
1 = Perform a full reset, not including registers. .
9.6.27 Testmode Channel Control (TMCH_CTRL)
Table 38. Testmode Channel Control (TMCH_CTRL), Address 0x0025

15:8 RESERVED 0x04 RESERVED
7:5 TM_CH_SEL 0x0 Test mode Channel Select.
If bit 7 is set then Test mode is driven on all 4 channels. If bit 7 is
cleared then test modes are driven according to bits 6:5 as follows:
00: Channel A
01: Channel B
10: Channel C
11: Channel D
4:0 RESERVED 0x00 RESERVED

6:5 SGMII_AUTONEG_TIMER 01, RW SGMII Auto-Negotiation Timer Duration:
11: 11ms
10: 800us
01: 2us
00: 16ms
0 PORT_MIRROR_EN 0, RW Port Mirror Enable:
1 = Enable port mirroring.
9.6.29 RGMII Control Register (RGMIICTL)

This register provides access to the RGMII controls.
Table 40. RGMII Control Register (RGMIICTL), Address 0x0032

7 RGMII_EN 1, RW RGMII Enable:
1 = Enable RGMII interface.

DP83867CS, DP83867IS, DP83867E
Table 40. RGMII Control Register (RGMIICTL), Address 0x0032 (continued)

0 = Disable RGMII interface.
6:5 RGMII_RX_HALF_FULL_THR 10, RW RGMII Receive FIFO Half Full Threshold:
This field controls the RGMII receive FIFO half full threshold.
4:3 RGMII_TX_HALF_FULL_THR 10, RW RGMII Transmit FIFO Half Full Threshold:
This field controls the RGMII transmit FIFO half full threshold.
1 RGMII_TX_CLK_DELAY 0, RW RGMII Transmit Clock Delay:
1 = RGMII transmit clock is shifted relative to transmit data.
0 = RGMII transmit clock is aligned to transmit data.
0 RGMII_RX_CLK_DELAY 0, RW RGMII Receive Clock Delay:
1 = RGMII receive clock is shifted relative to receive data.
0 = RGMII receive clock is aligned to receive data.
9.6.30 RGMII Control Register 2 (RGMIICTL2)
Table 41. RGMII Control Register 2 (RGMIICTL2), Address 0x0033

4 RGMII_AF_BYPASS_EN 0, RW RGMII Async FIFO Bypass Enable:
1 = Enable RGMII Async FIFO Bypass.
3 RGMII_AF_BYPASS_DLY_EN 0, RW RGMII Async FIFO Bypass Delay Enable:
1 = Delay RX_CLK when operating in 10/100 with RGMII.
2 LOW_LATENCY_10_100_EN 0, RW Low Latency 10/100 Enable:
1 = Enable low latency in 10/100 operation.
9.6.31 SGMII Auto-Negotiation Status (SGMII_ANEG_STS)
Table 42. SGMII Auto-Negotiation Status (SGMII_ANEG_STS)), address 0x0037

1 SGMII_PAGE_RX 0, RO SGMII Page Received:
1 = SGMII page has been received.
0 = SGMII page has not been received.
0 SGMII_AUTONEG_COMPLETE 0, RO SGMII Auto-Negotiation Complete:
1 = SGMII Auto-Negotiation process complete.
0 = SGMII Auto-Negotiation process not complete.

DP83867CS, DP83867IS, DP83867E
9.6.32 100BASE-TX Configuration (100CR)
Table 43. 100BASE-TX Configuration Register (100CR), Address 0x0043

11 DESCRAM_TIMEOUT_DIS 0, RW Disable 100Base-TX Descrambler Timeout:
1 = Disable packet reception when received packet violates the
descrambler timeout. This occurs when the packet is longer than
1.5ms.
0 = Stops packet reception when received packet violates the
descrambler timeout. This occurs when the packet is longer than
1.5ms.
10:7 DESCRAM_TIMEOUT 1111, RW Descrambler Timeout:
Adjust the descrambler time out value. This value refers to the
recovery time due to descrambler un-lock. Timer is in 'ms' units.
6 FORCE_100_OK 0, RW Force 100Mbps Good Link:
1 = Forces 100 Mbps good link.
5 ENH_MLT3_DET_EN 1, RW Enhanced MLT-3 Detection Enable:
1 = Enable enhanced MLT-3 Detection.
4 ENH_IPG_DET_EN 0, RW Enhanced Interpacket Gap Detection Enable:
1 = Enable enhanced interpacket gap detection.
2 SCR_DIS 0, RW Disable Scrambler:
1 = Disable scrambler.
1 ODD_NIBBLE_DETECT 0, RW Enable Odd Nibble Detection:
1 = Detect when an odd number of nibbles is received.
0 FAST_RX_DV 0, RW Fast RX_DV Enable:
1 = Enable fast RX_DV.

DP83867CS, DP83867IS, DP83867E
9.6.33 Strap Configuration Status Register 1 (STRAP_STS1)
Table 44. Strap Configuration Status Register 1 (STRAP_STS1), Address 0x006E

15 STRAP_MIRROR_EN Strap, RO Mirror Enable Strap:
1 = Port mirroring strapped to enable.
0 = Port mirroring strapped to disable.
14 STRAP_LINK_DOWNSHIFT_EN Strap, RO Link Downshift Enable Strap:
1 = Link Downshift strapped to enable.
0 = Link Downshift strapped to disable.
13 STRAP_CLK_OUT_DIS Strap, RO Clock Output Disable Strap:
1 = Clock output strapped to disable.
0 = Clock output strapped to enable.
12 STRAP_RGMII_DIS Strap, RO RGMII Disable Strap:
1 = RGMII strapped to disable.
0 = RGMII strapped to enable.
11 STRAP_SGMII_EN Strap, RO SGMII Enable Strap:
1 = SGMII strapped to enable.
0 = SGMII strapped to disable.
10 STRAP_AMDIX_DIS Strap, RO Auto-MDIX Disable Strap:
1 = Auto-MDIX strapped to disable.
0 = Auto-MDIX strapped to enable.
9 STRAP_FORCE_MDI_X Strap, RO Force MDI/X Strap:
1 = Force MDIX strapped to enable.
0 = Force MDI strapped to enable.
8 STRAP_HD_EN Strap, RO Half Duplex Enable Strap:
1 = Half Duplex strapped to enable.
0 = Full Duplex strapped to enable.
7 STRAP_ANEG_DIS Strap, RO Auto-Negotiation Disable Strap:
1 = Auto-Negotiation strapped to disable.
0 = Auto-Negotiation strapped to enable.
5 STRAP_SPEED_SEL Strap, RO SPEED_SEL value from strap.
See Speed Select Strap Details table.
3:0 STRAP_PHY_ADD Strap, RO PHY Address Strap:
PHY address value from straps.

DP83867CS, DP83867IS, DP83867E
9.6.34 Strap Configuration Status Register 2 (STRAP_STS2)
Table 45. Strap Configuration Status Register 2 (STRAP_STS2), Address 0x006F

10 STRAP_ FLD Strap, RO Fast Link Detect (FLD) Enable Strap:
1 = FLD strapped to enable.
0 = FLD strapped to disable.
6:4 STRAP_GMII_CLK_SKEW_TX Strap, RO RGMII Transmit Clock Skew Strap:
RGMII_TX_DELAY_CTRL[2:0] values from straps.
See RGMII Transmit Clock Skew Details table for more information.
2:0 STRAP_GMII_CLK_SKEW_RX Strap, RO RGMII Receive Clock Skew Strap:
RGMII_RX_DELAY_CTRL[2:0] values from straps.
See RGMII Transmit Clock Skew Details table for more information.

DP83867CS, DP83867IS, DP83867E
9.6.35 BIST Control and Status Register 1 (BICSR1)
Table 46. BIST Control and Status Register 1 (BICSR1), Address 0x0071
15:0 PRBS_BYTE_CNT 0x0000, RO Holds the number of total bytes received by the PRBS checker.
Value in this register is locked when write is done to register
BICSR2 bit[0] or bit[1].
The count stops at 0xFFFF when PRBS_COUNT_MODE in BISCR
register (0x0016) is set to 0.
9.6.36 BIST Control and Status Register 2 (BICSR2)
Table 47. BIST Control and Status Register 2 (BICSR2), Address 0x0072
15:11 Reserved 0x00, RO Ignored on Read
PRBS Checker Packet Count Overflow
10 PRBS_PKT_CNT_OVF 0, RO If set, PRBS Packet counter has reached overflow. Overflow is
cleared when PRBS counters are cleared by setting bit #1 of this
register.
PRBS Byte Count Overflow
9 PRBS_BYTE_CNT_OVF 0, RO If set, PRBS Byte counter has reached overflow. Overflow is cleared
when PRBS counters are cleared by setting bit #1 of this register.
8 Reserved 0,RO Ignore on Read
Holds number of error bytes that are received by PRBS checker.
Value in this register is locked when write is done to bit[0] or bit[1]
When PRBS Count Mode set to zero, count stops on 0xFF (see
7:0 PRBS_ERR_CNT 0x00, RO register 0x0016)
Notes: Writing bit 0 generates a lock signal for the PRBS counters.
Writing bit 1 generates a lock and clear signal for the PRBS
counters

DP83867CS, DP83867IS, DP83867E
9.6.37 RGMII Delay Control Register (RGMIIDCTL)

This register provides access to the RGMII delay controls.
Table 48. RGMII Delay Control Register (RGMIIDCTL), Address 0x0086

7:4 RGMII_TX_DELAY_CTRL RW, 0111 RGMII Transmit Clock Delay:
1111: 4.00 ns
1110: 3.75 ns
1101: 3.50 ns
1100: 3.25 ns
1011: 3.00 ns
1010: 2.75 ns
1001: 2.50 ns
1000: 2.25 ns
0111: 2.00 ns
0110: 1.75 ns
0101: 1.50 ns
0100: 1.25 ns
0011: 1.00 ns
0010: 0.75 ns
0001: 0.50 ns
0000: 0.25 ns
3:0 RGMII_RX_DELAY_CTRL RW, 0111 RGMII Receive Clock Delay:
1111: 4.00 ns
1110: 3.75 ns
1101: 3.50 ns
1100: 3.25 ns
1011: 3.00 ns
1010: 2.75 ns
1001: 2.50 ns
1000: 2.25 ns
0111: 2.00 ns
0110: 1.75 ns
0101: 1.50 ns
0100: 1.25 ns
0011: 1.00 ns
0010: 0.75 ns
0001: 0.50 ns
0000: 0.25 ns

DP83867CS, DP83867IS, DP83867E
9.6.38 SGMII Control Register 1 (SGMIICTL1)
Table 49. SGMII Control Register 1 (SGMIICTL1), Address 0x00D3

14 SGMII_TYPE 0, RW SGMII Configuration:
1 = 6-wire mode. Enable differential SGMII clock to MAC.
0 = 4-wire mode

DP83867CS, DP83867IS, DP83867E
9.6.39 Loopback Configuration Register (LOOPCR)
Table 50. Loopback Configuration Register (LOOPCR), Address 0x00FE

15:0 LOOP_CFG_VAL 1110 0111 0010 Loopback Configuration Value:
0001, RW
1110 0111 0010 000: Configuration for loopback modes.
A software reset via bit 14 of the Control Register (CTRL), address
0x001F, is required after changes to this register value.
Other values for this register are not recommended.

DP83867CS, DP83867IS, DP83867E
9.6.40 Receive Configuration Register (RXFCFG)

This register provides receive configuration for Wake on LAN (WoL).
Table 51. Receive Configuration Register (RXFCFG), Address 0x0134

11 WOL_OUT_CLEAR 0, RW, SC Clear Wake on LAN Output:
This bit is only applicable when configured for level mode.
1 = Clear Wake on LAN output
10:9 WOL_OUT_STRETCH 00, RW Wake on LAN Output Stretch:
If WoL out is configured for pulse mode, the pulse length is defined
as the following number of 125MHz clock cycles:
11 = 64 clock cycles
00 = 8 clock cycles
8 WOL_OUT_MODE 0, RW Wake on LAN Output Mode:
1 = Level Mode. WoL is cleared by a write to WOL_OUT_CLEAR
(bit 11).
0 = Pulse Mode. Pulse width is configured via
WOL_OUT_STRETCH (bits 10:9).
7 ENHANCED_MAC_SUPPORT 0, RW Enable Enhanced Receive Features:
1 = Enable for Wake on LAN, CRC check, and Receive 1588
indication.
5 SCRON_EN 0, RW Enable SecureOn Password:
1 = SecureOn Password enabled.
0 = SecureOn Password disabled.
4 WAKE_ON_UCAST 0, RW Wake on Unicast Packet:
1 = Issue an interrupt upon reception of Unicast packet.
0 = Do not issue an interrupt upon reception of Unicast packet.
2 WAKE_ON_BCAST 1, RW Wake on Broadcast Packet:
1 = Issue an interrupt upon reception of Broadcast packet.
0 = Do not issue an interrupt upon reception of Broadcast packet.
1 WAKE_ON_PATTERN 0, RW Wake on Pattern Match:
1 = Issue an interrupt upon pattern match.
0 = Do not issue an interrupt upon pattern match.
0 WAKE_ON_MAGIC 0, RW Wake on Magic Packet:
1 = Issue an interrupt upon reception of Magic packet.
0 = Do not issue an interrupt upon reception of Magic packet.

DP83867CS, DP83867IS, DP83867E
9.6.41 Receive Status Register (RXFSTS)

This register provides status for receive functionality.
Table 52. Receive Status Register (RXFSTS), Address 0x0135

7 SFD_ERR 0, R0, LH, SC SFD Error:
1 = Packet with SFD error (without an 0x5D SFD byte) received.
0 = No SFD error seen.
6 BAD_CRC 0, R0, LH, SC Bad CRC:
1 = A packet with a bad CRC was received.
0 = No bad CRC seen.
5 SCRON_HACK 0, R0, LH, SC SecureOn Hack Attempt Flag:
1 = SecureOn Hack attempt seen.
0 = No SecureOn Hack attempt seen.
4 UCAST_RCVD 0, R0, LH, SC Unicast Packet Received:
1 = A valid Unicast packet was received.
0 = No valid Unicast packet was received.
2 BCAST_RCVD 0, R0, LH, SC Broadcast Packet Received:
1 = A valid Broadcast packet was received.
0 = No valid Broadcast packet was received.
1 PATTERN_RCVD 0, R0, LH, SC Pattern Match Received:
1 = A valid packet with the configured pattern was received.
0 = No valid packet with the configured pattern was received.
0 MAGIC_RCVD 0, R0, LH, SC Magic Packet Received:
1 = A valid Magic packet was received.
0 = No valid Magic packet was received.

DP83867CS, DP83867IS, DP83867E
9.6.42 Pattern Match Data Register 1 (RXFPMD1)
Table 53. Pattern Match Data Register 1 (RXFPMD1), Address 0x0136

15:0 PMATCH_DATA_15_0 0, RW Bits 15:0 of Perfect Match Data - used for DA (destination address)
match
Table 54. Pattern Match Data Register 2 (RXFPMD2), address 0x0137

15:0 PMATCH_DATA_31_16 0, RW Bits 31:16 of Perfect Match Data - used for DA (destination address)
match
Table 55. Pattern Match Data Register 3 (RXFPMD3), address 0x0138

15:0 PMATCH_DATA_ 47_32 0, RW Bits 47:32 of Perfect Match Data - used for DA (destination address)
match
9.6.45 SecureOn Pass Register 2 (RXFSOP1)
Table 56. SecureOn Pass Register 1 (RXFSOP1), Address 0x0139

15:0 SCRON_PASSWORD _15_0 0, RW Bits 15:0 of secure-on password for magic packet)
Table 57. SecureOn Pass Register 2 (RXFSOP2), Address 0x013A

15:0 SCRON_PASSWORD _31_16 0, RW Bits 31:16 of secure-on password for magic packet
Table 58. SecureOn Pass Register 3 (RXFSOP3), Address 0x013B

15:0 SCRON_PASSWORD _ 47_32 0, RW Bits 47:32 of secure-on password for magic packet
9.6.48 Receive Pattern Register 1 (RXFPAT1)
Table 59. Receive Pattern Register 1 (RXFPAT1), Address 0x013C

15:0 PATTERN_BYTES_0_1 0, RW Bytes 0 (LSbyte) + 1 of the configured pattern. Each byte can be
masked separately via the RXF_PATTERN_BYTE_MASK registers.
Table 60. Receive Pattern Register 2 (RXFPAT2), Address 0x013D

15:0 PATTERN_BYTES_2_3 0, RW Bytes 2 + 3 of the configured pattern. Each byte can be masked
separately via the RXF_PATTERN_BYTE_MASK registers.

DP83867CS, DP83867IS, DP83867E
Table 61. Receive Pattern Register 3 (RXFPAT3), Address 0x013E

Table 62. Receive Pattern Register 4 (RXFPAT4), Address 0x013F

Table 63. Receive Pattern Register 5 (RXFPAT5), Address 0x0140




15:0 PATTERN_BYTES_14_15 0, RW Bytes 0 14 + 15 of the configured pattern. Each byte can be
masked separately via the RXF_PATTERN_BYTE_MASK registers.

15:0 PATTERN_BYTES_16_17 0, RW. Bytes 16 + 17 of the configured pattern. Each byte can be masked

DP83867CS, DP83867IS, DP83867E





Table 73. Receive Pattern Register 15 (RXFPAT15), address 0x014A

Table 74. Receive Pattern Register 16 (RXFPAT16), Address 0x014B


DP83867CS, DP83867IS, DP83867E
Table 75. Receive Pattern Register 17 (RXFPAT17), Address 0x014C

Table 76. Receive Pattern Register 18 (RXFPAT18), Address 0x014D

Table 77. Receive Pattern Register 19 (RXFPAT19), Address 0x014E

Table 78. Receive Pattern Register 20 (RXFPAT20), Address 0x014F





DP83867CS, DP83867IS, DP83867E








DP83867CS, DP83867IS, DP83867E
Table 89. Receive Pattern Register 31 (RXFPAT31), Address 0x015A

Table 90. Receive Pattern Register 32 (RXFPAT32), Address 0x015B

Bytes 62 + 63 of the configured pattern. Each byte can be masked
15:0 PATTERN_BYTES_62_63 0, RW
9.6.80 Receive Pattern Byte Mask Register 1 (RXFPBM1)
Table 91. Receive Pattern Byte Mask Register 1 (RXFPBM1), Address 0x015C
15:0 PATTERN_BYTES_ 0, RW Masks for bytes 0 to 15 of the pattern. A '1' indicates a mask for the
MASK_0_15 associated byte.
Table 92. Receive Pattern Byte Mask Register 2 (RXFPBM2), Address 0x015D
15:0 PATTERN_BYTES_ 0, RW Masks for bytes 16 to 31 of the pattern. A '1' indicates a mask for
MASK_16_31 the associated byte.
Table 93. Receive Pattern Byte Mask Register 3 (RXFPBM3), Address 0x015E
Table 94. Receive Pattern Byte Mask Register 4 (RXFPBM4), Address 0x015F
9.6.84 Receive Pattern Control (RXFPATC)
Table 95. Receive Status Register (RXFSTS), Address 0x0161

5:0 PATTERN_START_POINT 0, RW Number of bytes after SFD where comparison of the RX packet to
the configured pattern begins:
111111 - Start compare in the 64th byte after SFD
000000 - Start compare in the 1st byte after SFD

DP83867CS, DP83867IS, DP83867E
9.6.85 10M SGMII Configuration (10M_SGMII_CFG)
Table 96. 10M SGMII Configuration (10M_SGMII_CFG), Address 0x016F

15:8 RESERVED 0000 0000, RO RESERVED
7 10M_SGMII_RATE_ADAPT 1, RW Clear this bit for enabling 10M SGMII Operation.
6:0 RESERVED 001 0101, RO RESERVED

DP83867CS, DP83867IS, DP83867E
9.6.86 I/O Configuration (IO_MUX_CFG)
Table 97. I/O Configuration (IO_MUX_CFG), Address 0x0170

12:8 CLK_O_SEL 0 0110, RW Clock Output Select:
01101 - 11111: RESERVED
01100: Reference clock (synchronous to X_I input clock)
01011: Channel D transmit clock
01010: Channel C transmit clock
01001: Channel B transmit clock
01000: Channel A transmit clock
00111: Channel D receive clock divided by 5
00110: Channel C receive clock divided by 5
00101: Channel B receive clock divided by 5
00100: Channel A receive clock divided by 5
00011: Channel D receive clock
00010: Channel C receive clock
00001: Channel B receive clock
00000: Channel A receive clock
6 CLK_O_DISABLE Strap, RW Clock Output Disable:
1 = Disable clock output on CLK_OUT pin.
0 = Enable clock output on CLK_OUT pin.
4:0 IO_IMPEDANCE_CTRL 10000, RW Impedance Control for MAC I/Os:
11100: I/O adjustment for external loopback testing on the MAC
interface.
Other values for this register are not recommended.

DP83867CS, DP83867IS, DP83867E
9.6.87 GPIO Mux Control Register (GPIO_MUX_CTRL)
Table 98. GPIO Mux Control Register (GPIO_MUX_CTRL), Address 0x0172

7:4 GPIO_1_CTRL RW, 0000 GPIO_1 Control:
1010 - 1111: RESERVED
1001: Constant '1'
1000: Constant '0'
0111: PRBS Errors / Loss of Sync
0110: LED 4
0101: LPI On
0100: Energy Detect (1000Base-T and 100Base-TX only)
0011: WOL
0010: 1588 RX SFD
0001: 1588 TX SFD
0000: COL
3:0 GPIO_0_CTRL RW, 0000 GPIO_0 Control:
1010 - 1111: RESERVED
1001: Constant '1'
1000: Constant '0'
0111: PRBS Errors / Loss of Sync
0110: LED 4
0101: LPI On
0100: Energy Detect (1000Base-T and 100Base-TX only)
0011: WOL
0010: 1588 RX SFD
0001: 1588 TX SFD
0000: RX_ER

DP83867CS, DP83867IS, DP83867E
9.6.88 TDR General Configuration Register 1 (TDR_GEN_CFG1)
Table 99. TDR General Configuration Register 1 (TDR_GEN_CFG1), Address 0x0180

12 TDR_CH_CD_BYPASS 0, RW TDR Bypass for Channel C and D:
1 = Bypass channel C and D in TDR tests.
11 TDR_CROSS_MODE_DIS 0, RW Disable TDR Cross Mode:
1 = Disable cross mode option. Do not check cross channels. Only
listen to the channel being used for transmit.
10 TDR_NLP_CHECK 1, RW TDR NLP Check:
1 = Check for NLPs during silence.
9:7 TDR_AVG_NUM 110, RW Number Of TDR Cycles to Average:
111: RESERVED: Writes ignored, read as 0.
110: 64 TDR cycles
101: 32 TDR cycles
100: 16 TDR cycles
011: 8 TDR cycles
010: 4 TDR cycles
001: 2 TDR cycles
000: 1 TDR cycle
6:4 TDR_SEG_NUM 101, RW Set the number of TDR segments to check.
3:0 TDR_CYCLE_TIME 010, RW Set the time for each TDR cycle. Value is measured in
microseconds.

DP83867CS, DP83867IS, DP83867E
9.6.89 Advanced Link Cable Diagnostics Control Register (ALCD_CTRL)
Table 100. Advanced Link Cable Diagnostics Control Register (ALCD_CTRL), Address 0x01A7
15:8 ALCD_SUM 0000 0000, RO ALCD result
5 ALCD_SUM_DONE 0, RO ALCD Complete:
1 = ALCD process has completed.
0 = ALCD process has not completed.
4 ALCD_CLEAR 0, RW, SC Clear ALCD:
1 = Reset the ALCD results.
9.6.90 MMD3 PCS Control Register (MMD3_PCS_CTRL)

This register is accessed via indirect register access. See Extended Address Space Access for details
Table 101. MMD3 PCS Control Register (MMD3_PCS_CTRL), MMD3 Address 0x0000
15 PCS_RESET 0, RW, SC MMD3 / MMD7 PCS Reset:
1 = Reset the MMD3 and MMD7 registers. Note: Setting this bit will
subsequently cause a soft reset via the BMCR RESET bit (bit 15 of
register address 0x0000).

DP83867CS, DP83867IS, DP83867E
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information

The DP83867 is a single port 10/100/1000 Ethernet PHY. It supports connections to an Ethernet MAC via SGMII
or RGMII. Connections to the Ethernet media are made via the IEEE 802.3 defined Media Dependent Interface.
When using the device for Ethernet application, it is necessary to meet certain requirements for normal operation
of the device. The following typical application and design requirements can be used for selecting appropriate
component values for DP83867.
10.2 Typical Application

10BASE-Te
RGMII
100BASE-TX
SGMII
1000BASE-T
DP83867
Ethernet MAC 10/100/1000 Mbps Magnetics RJ-45
Ethernet Physical Layer
25 MHz Status
Crystal or Oscillator LEDs
Figure 22. Typical DP83867 Application
10.2.1 Design Requirements

The design requirements for the DP83867 are:
• VDDA2P5 = 2.5 V
• VDD1P0 = 1.0 V
• VDDIO = 3.3 V, 2.5 V, or 1.8 V
• Clock Input = 25 MHz

DP83867CS, DP83867IS, DP83867E
Typical Application (continued)

10.2.1.1 Cable Line Driver
The line driver implementation is designed to support simple connections to the transformer and the connector.
The DP83867 includes integrated terminations so no external termination resistors are required.
The connection diagram for the cable line driver is shown in Figure 23.
TD_P_A
TD_M_A
TD_P_B
TD_M_B
TD_P_C
TD_M_C
TD_P_D
TD_M_D
1:1 Transformer RJ-45 Connector
Figure 23. Magnetics Connections
10.2.1.2 Clock In (X_I) Recommendation

If an external clock source is used, X_O should be left floating. For a 1.8-V clock source, X_I should be tied to
the clock source. For a 3.3V or 2.5V clock source, a capacitor divder is recommended as shown in Figure 24.
The recommended values for the C1 and C2 capacitors is 27pF.
X_I X_O
3.3V or 2.5V
Clock Source
CD1
CD2
Figure 24. Clock Divider

DP83867CS, DP83867IS, DP83867E
Typical Application (continued)

The CMOS 25-MHz oscillator specifications are listed in Table 102.
Table 102. 25MHz Oscillator Specifications

PARAMETER MIN TYP MAX UNITS CONDITION
Frequency 25 MHz
Frequency Operational
+/- 50 ppm
Tolerance Temperature
Frequency Stability +/- 50 ppm 1 year aging
Rise / Fall Time 5 nsec 20% - 80%
Symmetry 40 60 % Duty Cycle
10.2.1.3 Crystal Recommendations

A 25-MHz, parallel, 18-pF load crystal resonator should be used if a crystal source is desired. Figure 25 shows a
typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors;
check with the vendor for the recommended loads.
X_I X_O
R1
CL1 CL2
Figure 25. Crystal Oscillator Circuit
As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1 and
CL2 should be set at 27 pF, and R1 should be set at 0 Ω.
Specification for 25-MHz crystal are listed in Table 103.
Table 103. 25MHz Crystal Specifications

PARAMETER MIN TYP MAX UNITS CONDITION
Frequency 25 MHz
Frequency Operational
+/- 50 ppm
Tolerance Temperature
Frequency Stability +/- 50 ppm 1 year aging

DP83867CS, DP83867IS, DP83867E
10.2.2 Detailed Design Procedure
10.2.2.1 MAC Interface

The Media Independent Interface (SGMII / RGMII) connects the DP83867 to the Media Access Controller (MAC).
The MAC may in fact be a discrete device, integrated into a microprocessor, CPU or FPGA.
10.2.2.1.1 SGMII Layout Guidelines

• All SGMII connections should be AC coupled via an 0.1µF capacitor. Series capacitors should be 0.1uF and
the size should be 0402 or smaller.
• SGMII signals are differential signals.
• Traces should be routed with 100-Ω differential impedance.
• Skew matching within a pair should be less than 5pS, which correlates to 30mil for standard FR4.
• There is no requirement to match the TX pair to the RX pair.
• SGMII signals should be routed on the same layer.
• Pairs should be referenced to parallel ground plane.
• When operating in 6-wire mode, the RX pair must match the Clock pair to within 5pS, which correlates to
30mil for standard FR4.
10.2.2.1.2 RGMII Layout Guidelines

• RGMII signals are single-ended signals.
• Traces should be routed with impedance of 50 Ω to ground.
• Skew between TXD[3:0] lines should be less than 11ps, which correlates to 60mil for standard FR4.
• Skew between RXD[3:0] lines should be less than 11ps, which correlates to 60mil for standard FR4.
• Keep trace lengths as short as possible, less than 2 inches recommended, less than 6 inches maximum
length.
• Configurable clock skew for GTX_CLK and RX_CLK.
– Clock skew for RX and TX paths can be optimized independently.
– Clock skew is adjustable in 0.25ns increments (via register).
10.2.2.2 Media Dependent Interface (MDI)

The Media Dependent Interface (MDI) connects the DP83867 to the transformer and the Ethernet network.
10.2.2.2.1 MDI Layout Guidelines

• MDI traces should be 50 Ω to ground or 100 Ω differential controlled impedance.
• Route MDI traces to transformer on the same layer.
• Use a metal shielded RJ-45 connector, and connect the shield to chassis ground.
• Use magnetics with integrated common mode choking devices.
• Void supplies and ground beneath magnetics.
• Do not overlap the circuit and chassis ground planes, keep them isolated. Instead, make chassis ground an
isolated island and make a void between the chassis and circuit ground. Connecting circuit and chassis
planes using a size 1206 resistor and capacitor on either side of the connector is a good practice.

DP83867CS, DP83867IS, DP83867E
11 Power Supply Recommendations

The DP83867 is capable of operating with as few as two or three supplies. The I/O power supply can also be
operated independently of the main device power supplies in order to provide flexibility for the MAC interface.
When operating in 3 supply mode, the 2.5-V VDDA2P5 can come up with or after the 1.8-V VDDA1P8 but not
before it. It is highly recommended that the 1.8-V VDDA1P8 supplies be powered first. There is no sequencing
requirement for other supplies when operating in 3 supply mode.
There is no requirement for the sequence of the supplies when operating in 2 supply mode.
The connection diagrams for the two supply and three supply configurations are shown in and .
VDDIO VDD1P0
VDDIO 1.0V
Supply 0.1 PF 1 PF 1 PF 0.1 PF Supply
VDDIO VDD1P0
10 PF 10 nF 0.1 PF 1 PF 1 PF 0.1 PF 10 nF 10 PF
VDDIO VDD1P0
0.1 PF 1 PF 1 PF 0.1 PF
VDD1P0
1 PF 0.1 PF
VDDA2P5 VDDA1P8
2.5V
Supply 0.1 PF 1 PF
VDDA2P5 VDDA1P8
10 PF 10 nF 0.1 PF 1 PF
GND
(Die Attach Pad
For two supply configuration, both VDDA1P8 pins must be left unconnected.
Place 1µF & 0.1µF decoupling capacitors as close as possible to component VDD pins.
VDDIO may be 3.3 V or 2.5 V or 1.8 V.
No Components should be connected to VDDA1P8 pins in Two Supply Configuration.
Figure 26. Two Supply Configuration

DP83867CS, DP83867IS, DP83867E
VDDIO VDD1P0
VDDIO 1.0V
VDDIO VDD1P0
VDDIO VDD1P0
0.1 PF 1 PF 1 PF 0.1 PF
VDD1P0
1 PF 0.1 PF
VDDA2P5 VDDA1P8
2.5V 1.8V
VDDA2P5 VDDA1P8
GND
(Die Attach Pad
Place 1µF & 0.1µF decoupling capacitors as close as possible to component VDD pins.
Note: VDDIO may be 3.3 V or 2.5 V or 1.8 V.
Figure 27. Three Supply Configuration

DP83867CS, DP83867IS, DP83867E
12 Layout
12.1 Signal Traces

PCB traces are lossy and long traces can degrade the signal quality. Traces should be kept short as possible.
Unless mentioned otherwise, all signal traces should be 50Ω single ended impedance. Differential traces should
be 50Ω single ended and 100Ω differential. Care should be taken that the impedance is constant throughout.
Impedance discontinuities will cause reflections leading to EMI & signal integrity problems. Stubs should be
avoided on all signal traces, especially the differential signal pairs. See Figure 28
Within the differential pairs, the trace lengths should be run parallel to each other and matched in length.
Matched lengths minimize delay differences, avoiding an increase in common mode noise and increased EMI.
Length matching is also important on MAC interface. All Transmit signal traces should be length matched to each
other and all Receive signal traces should be length matched to each other.
Ideally, there should be no crossover or via on the signal paths. Vias present impedance discontinuities and
should be minimized. Route an entire trace pair on a single layer if possible.
Figure 28. Avoiding Stubs in a Differential Signal Pair
Signals on different layers should not cross each other without at least one return path plane between them.
Coupling between traces is also an important factor. Unwanted coupling can cause cross talk problems.
Differential pairs on the other hand, should have a constant coupling distance between them.
For convenience & efficient layout process, start by routing the critical signals first.
12.2 Return path

A general best practice is to have a solid return path beneath all signal traces. This return path can be a
continuous ground or DC power plane. Reducing the width of the return path width can potentially affect the
impedance of the signal trace. This effect is more prominent when the width of the return path is comparable to
the width of the signal trace. Breaks in return path beneath the signal traces should be avoided at all cost. A
signal crossing a plane split may cause unpredictable return path currents and would likely impact signal quality
as well, potentially creating EMI problems. See Figure 29

DP83867CS, DP83867IS, DP83867E
Return path (continued)
Figure 29. Differential Signal Pair-Plane Crossing
12.3 Transformer Layout

There should be no metal layer running beneath the transformer. Transformers can inject noise in metal beneath
them which can affect the performance of the system.
12.4 Metal Pour

All metal pours which are not signals or power should be tied to ground. There should be no floating metal on the
system. There should be no metal between the differential traces.
12.5 PCB Layer Stacking

To meet signal integrity and performance requirements, at minimum a four-layer PCB should be used. However
a 6 layer board is recommended. See Figure 30 for the recommended layer stack ups for 4, 6 and 8-layer
boards. These are recommendations not requirements, other configurations can be used as per system
requirements.
xxx
Legend
Ground
xxx
High-speed signal
VDD supply
xxx
xx xxxxx
4-Layer 6-Layer 8-Layer
Figure 30. Recommended Layer Stack Up
Within a PCB, it may be desirable to run traces using different methods, microstrip vs. stripline, depending on the
location of the signal on the PCB. For example, it may be desirable to change layer stacking where an isolated
chassis ground plane is used. Figure 31 illustrates alternative PCB stacking options.

DP83867CS, DP83867IS, DP83867E
PCB Layer Stacking (continued)
xxx
Legend
Chassis ground
xxxxxx
High-speed signal
VDD supply
xxx
Figure 31. Alternative Layer Stack Up
12.6 Layout Example
Plane Coupling
Component
Transformer
(if not RJ45
PHY
Component Integrated in Connector
RJ45)
Plane Coupling
Note: Power/Ground Planes
Component
Voided under Transformer
System Power/Ground Chassis Ground

Planes Plane
Figure 32. Layout Example

DP83867CS, DP83867IS, DP83867E
13 Device and Documentation Support
13.1 Documentation Support

13.1.1 Related Documentation
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application
report, SPRA953.
13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 104. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
DP83867CS Click here Click here Click here Click here Click here
DP83867IS Click here Click here Click here Click here Click here
DP83867E Click here Click here Click here Click here Click here
13.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 28-Oct-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
DP83867CSRGZR PREVIEW VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 DP83867CS
& no Sb/Br)
DP83867CSRGZT PREVIEW VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 DP83867CS
& no Sb/Br)
DP83867ERGZR PREVIEW VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 DP83867E
& no Sb/Br)
DP83867ERGZT PREVIEW VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 DP83867E
& no Sb/Br)
DP83867ISRGZR PREVIEW VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 DP83867IS
& no Sb/Br)
DP83867ISRGZT PREVIEW VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 DP83867IS
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 28-Oct-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
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Table 1. Device Features Comparison

7 Pin Configuration and Functions

TD_P_C 7 48-pin QFN Package 30 VDDIO

TD_M_C 8 DAP = GND 29 GTX_CLK

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Table 2. Pin Functions

(1) The definitions below define the functionality of each pin.

Table 2. Pin Functions (continued)

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Table 2. Pin Functions (continued)

7.1 Unused Pins

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8.2 ESD Ratings

8.3 Recommended Operating Conditions

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8.4 Thermal Information

8.5 Electrical Characteristics

(1) Ensured by production test, characterization, or design.

Electrical Characteristics (continued)

(2) Power consumption represents total operational power for 1000BASE-T.

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(1) Ensured by production test, characterization, or design.

Dual Function Pins

Figure 1. Powerup Timing

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8.7 Reset Timing (1)

(1) Ensured by production test, characterization, or design.

Dual F unction Pins

Figure 2. Reset Timing

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8.8 MII Serial Management Timing (1)

(1) Ensured by production test, characterization, or design.

MDIO (input) Valid Data

Figure 3. MII Serial Management Timing

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8.9 SGMII Timing (1)

(1) Ensured by production test, characterization, or design.

Figure 4. SGMII Timing

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8.10 RGMII Timing (1)

(1) Ensured by production test, characterization, or design.

TXD [8:5][3:0] TXD [8:5]

TXD [4] TXD [9]

Figure 5. RGMII Transmit Multiplexing and Timing Diagram

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RXC RXC with Internal

RXD [8:5][3:0] RXD [8:5]

RXD [4] RXD [9]

Figure 6. RGMII Receive Multiplexing and Timing Diagram

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8.11 Typical Characteristics

1000Base-T Signaling 100Base-TX Signaling

Figure 7. 1000Base-T Signaling Figure 8. 100Base-TX Signaling

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