Distinction between analog and digital signal

Difference between the Analog signals and

Digital signals
Analog signals Digital signals
Analog signals are difficult to get analysed at
Digital signals are easy to analyse.
first.
Analog signals are more accurate than digital
Digital signals are less accurate.
signals.
Analog signals take time to be stored. It has
Digital signals can be easily stored.
infinite memory.
To record an analog signal, the technique In recording digital signal, the sample
used, preserves the original signals. signals are taken and preserved.
There is a continuous representation of signals There is a discontinuous representation of
in analog signals. signals in digital signals.
Analog signals produce too much noise. Digital signals do not produce noise.
Examples of analog signals are Human voice, Examples of digital signals are Computers,
Thermometer, Analog phones etc. Digital Phones, Digital pens, etc.

Advantages

The advantages of a digital signal processor include the following.

• Overall noise is less.

• Possibility of error detection & correction.
• Simple data storage.
• Digital signals are simple to encrypt.
• Transmission of more data is possible.
• In digital processing systems, modifying a few commands otherwise change a few code lines
is easy to modify.
• DSP systems work through a broader range of frequencies.
• In a digital system, the DSP can be cascaded without any loading issues.
• The operations of DSP can be simply changed by altering the program within a digital
programmable system.
• By using the DSP method, a complicated signal processing algorithm can be simply
implemented.
• DSPs are lightweight & more compact.
• DSP systems are upgradeable because they are controlled by software.

Disadvantages

The disadvantages of a digital signal processor include the following.

 • Digital communications need high bandwidth to transmit the data as compared to analog.
• Most of the digital signal processors are expensive.
• The DSP system complexity will be increased due to the usage of additional components.
• Digital signal processor uses several transistors which consume more power as compared to
analog signal processors.
• The hardware architecture & software instructions of each DSP are different so required
highly skilled engineers to program the device.

some important applications of digital signal

• It is used in seismic data processing.

• It is used in statistical signal processing.

• It is used in voice recognition systems.
• It is used in digital images (HD).
• It is used as filter design for receiver applications.
• It is used in radar, sonar signal analysis and processing.
• All the processes done in mobile communication have DSP in them.
• It is used in biometric systems such as ECG, EEG, MRI and CT scan.
• It is used in video compression and speech compression.
• It is used in hi-fi loudspeakers crossovers and equalization.

Q2

Digital logic circuits can be classified into “combinational” and “sequential”. A

combinational logic circuit is one whose output solely depends on its current inputs.
sequential circuits, on the other hand, are built using combinational circuits and memory
elements called “flip-flops”. These circuits generate output that depends on the current and
previous states. A Digital logic (or Switching) circuit has voltage levels to be switched from
one value to another but has a finite number of distinct values (generally 0 for false and 1 for
true). These circuits operate a definite set of logic rules so it is also known as Logic circuits.
These are basic circuits that are used in mobile phones, calculators, computers, etc.

Types of Logic Circuits: There are two types of Digital circuits depending on their output
and memory used:

(i) Combinational circuit, and

(ii) Sequential circuit

A combinational circuit consists of logic gates whose outputs at any time are determined
from only the present combination of inputs and they have no memory. A sequential circuit
consists of logic gates whose outputs at any time are determined from both the present
combination of inputs and previous output. That means sequential circuits use memory
elements to store the value of previous output.

1. Combinational Circuits: These circuits are developed using AND, OR, NOT, NAND,
and NOR logic gates. These logic gates are building blocks of combinational circuits. A
combinational circuit consists of input variables and output variables. Since these circuits are
not dependent upon previous input to generate any output, so are combinational logic circuits.
A combinational circuit can have an n number of inputs and m number of outputs. In
combinational circuits, the output at any time is a direct function of the applied external
inputs.

2. Sequential circuits: A sequential circuit is specified by a time sequence of inputs, outputs,

and internal states. The output of a sequential circuit depends not only on the combination of
present inputs but also on the previous outputs. Unlike combinational circuits, sequential
circuits include memory elements with combinational circuits. Some examples are counters

and shift registers.

1’s Complement Subtraction Explained

with Examples

1’s complement subtraction is a method to subtract two binary numbers. This

method allows subtraction of two binary numbers by addition. The 1’s complement of
a binary number can be obtained by replacing all 0 to 1 and all 1 to 0. This article
discusses steps involved in 1’s complement subtraction of a smaller number from a
larger number & the steps for subtracting a smaller number from a larger number
with example.

Steps for 1’s Complement Subtraction:

Subtraction of Smaller Number from Larger Number:

The steps for 1’s complement subtraction of a smaller number from a larger binary
number are as follows:

Step-1: Determine the 1’s complement of the smaller number.

Step-2: Add this to the larger number.

Step-3: Remove the carry and add it to the result. This carry is called end-around-
carry.

Following examples illustrates the septs involved in 1’s complement subtraction of a

smaller number from larger number.

Example-1: Subtract (1010)2 from (1111)2 using 1’s complement method.

Step-1: Find the 1’s complement of 1010. It will be found by replacing all 0 to 1 and
all 1 to 0. In this way, the required 1’s complement will be 0101.

Step-2: In this step, we need to add the vale calculated in step-1 to 1111. This is
shown below.

For your reference, addition of binary digits 1 + 1 = 10. Also, note that carry 1 has
been added to the addition to get the subtraction of the binary numbers. Thus, the
subtraction is done by actually adding two binary numbers.

Subtraction of Larger Number from Smaller Number:

The steps involved in 1’s complement subtraction of a larger number from a smaller
number are as follows:
Step-1: Determine the 1’s complement of the larger number.

Step-2: Add this to the smaller number.

Step-3: The answer is the 1’s complement of the true result and opposite in sign.
There is no carry.

Following examples illustrates the application of above mentioned septs for

subtraction of a larger number from smaller number.

Example: Subtract (1010)2 from (1000)2 using 1’s complement method.

The 1’s complement of (1010)2 is (0101)2. Now, we will add this with the smaller
number and finally take 1’s complement of the result to get the answer. This is
shown below.

Mind that, no carry has been obtained while subtracting a larger number from a
smaller number. Further, a minus sign has been put.

’s Complement Subtraction of Binary

Numbers
September 23, 2020 by admin
2’s complement subtraction method is a way to subtract two binary numbers by
actually adding one number with the 2’s complement of another number. In this
article, the method of binary subtraction using 2’s complement is elaborated with
examples.

Method of 2’s Complement Subtraction:

To implement this method for subtracting two binary numbers, the very first step is
find the 2’s complement of the number which is to be subtracted from another
number. To get the 2’s complement, first of all 1’s complement is find and then 1 is
added to this. The addition is the required 2’s complement.

Suppose, we need to find the 2’s complement of binary number 10010. First, find 1’s
complement. To find this, replace all 1 to 0 and all 0 to 1. Therefore, 1’s complement
of 10010 will be 01101. Now, add 1 to this as shown below.

Steps for 2’s Complement Subtraction:

Subtraction of Smaller Number from Larger Number:

To subtract a smaller number from a larger number using 2’s complement

subtraction, following steps are to be followed:

Step-1: Determine the 2’s complement of the smaller number

Step-2: Add this to the larger number.

Step-3: Omit the carry. Note that, there is always a carry in this case.

Following example illustrate the above mentioned steps:

Exampe-1: Subtract (1010)2 from (1111)2 using 2’s complement method.

Solution:

Step-1: 2’s complement of (1010)2 is (0110)2.

Step-2: Add (0110)2 to (1111)2. This is shown below.

Subtraction of Larger Number from Smaller Number:

To subtract a larger number from a smaller number using 2’s complement

subtraction, following steps are to be followed:

Step-1: Determine the 2’s complement of the smaller number

Step-2: Add this to the larger number.

Step-3: There is no carry in this case. The result is in 2’s complement form and is
negative.

Step-4: To get answer in true form, take 2’s complement and change its sign.

Following example will definitely help you to understand the above steps:

Example-2: Subtract (1010)2 from (1000)2 using 2’s complement.

Solution:

Step-1: Find the 2’s complement of (1010)2. It is (0110)2.

Step-2: Add (0110)2 to (1000)2.

Step-3 and Step-4 has been explained in the above difference calculation.

Advantages:

Though both 1’s and 2’s complement method for subtracting binary numbers seems
to be complicated when compared with direct method of subtraction of two binary
numbers, both have some distinct advantage when applied using logic circuits,
because they allow subtraction to be done using only addition. The ‘s and 2’s
complement of a binary number can easily be arrived at using logic circuits; the
advantage in 2’s complement subtraction is that the end-around-carry operation
present in 1’s complement method is not involved here.

What is Binary Coded Decimal Number?

Binary Coded Decimal number system is system in which decimal numbers from 0 to
9 are represented by four bit binary number. It is often called BCD number system.

Each bit of BCD number has a positional weight. The weights are assigned as per
the position occupied by these digits. The weight of the first position (right most) is
20(1), the second 21(2), the third 22 (4) and the fourth 23(8). Reading from left to right,
the weights are 8-4-2-1, and hence binary coded decimal number system is also
called 8421 code.

The binary conversion of 7 is (111)2, but the same number is represented in Binary
Coded Decimal system in four bit form as (0111). Also, the numbers from 0 to 9 are
represented in the same way as in binary system but after 9 the representation in
BCD are different. For example, the decimal number 12 in binary system is (1100) 2
but the same number in BCD is represented as [0001 0010]. Note that each digit (1
& 2 separately) has been replaced by its equivalent 4-bit binary form.

The representation of decimal numbers from 0 to 15 in binary and equivalent binary

coded decimal system is tabulated below:

Binary Coded Decimal

Decimal Number Binary Number
(BCD)

0 0000 0000

1 0001 0001

2 0010 0010

3 0011 0011

4 0100 0100

5 0101 0101

6 0110 0110

7 0111 0111

8 1000 1000

9 1001 1001

10 1010 0001 0000

11 1011 0001 0001

12 1100 0001 0010

13 1101 0001 0011

14 1110 0001 0100

15 1111 0001 0101

Method for Converting Decimal to Binary Coded Decimal (BCD):

To convert a decimal number into its equivalent binary coded decimal (BCD) form,
each digit of the decimal number should be replaced by its equivalent four-bit binary
form. The number so obtained is the BCD form. Let us make this clear using some
examples.

Example-1: Give the BCD code for the decimal number 874.

Solution: Replace all digits i.e. 8, 7 and 4 by its equivalent 4-bit binary form. The 4-bit
binary form of 8, 7 and 4 are (1000), (0111) and (0100) respectively. Refer table for
getting the 4-bit binary form. Now, we will combine all these to get the BCD form.

So, the BCD equivalent of decimal number 874 is [1000 0111 0100]. (Answer)

Example-2: Give BCD code equivalent for the decimal number 96.42.

Solution: Replace all digits i.e. 9, 6, 4 & 2 by its equivalent 4-bit binary form. The
conversion is shown below.

Rule for BCD Addition:

BCD is a numerical code. Many applications require arithmetic operations. Addition

is the most important of theses because the other operation, namely subtraction,
multiplication and division, can be done using addition.

The rule for addition of two binary coded decimal (BCD) numbers is given below.

• Add the two numbers using the rules for binary addition.
• If a four-bit sum is equal to or less than 9, it is a valid BCD number.
• If a four-bit sum is greater than 9, or if a carry-out of the group is generated, it is
invalid result. Add 6 (0110)2 to the four-bit sum in order to skip he six invalid states
and return the code to BCD. If a carry results when 6 is added, add the carry to the
next four-bit group.
Example below illustrates the addition of two binary coded decimal (BCD) numbers.
You can corelate the steps mentioned.

Example-3: Add the BCD numbers 1001 and 0100.

Solution:

If you have any doubt, kindly write in comment box. Your voice will never be lost
here .

What is Hexadecimal Number System?

Hexadecimal number system is a system which uses 16 digits. Unlike decimal

numbering system, this system uses digits 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E &F to
represent a number. Digits A,B,C,D,E&F represents 10,11,12,13,14,15 and 16
respectively.

In Hexadecimal number system, each significant position has a positional weight.

The least significant position has a weight of 160 i.e. 1; the higher significant
positions are given weights in the ascending powers of sixteen i.e. 16 1, 162, 163 etc.
respectively.

The hexadecimal equivalent of a decimal number can be obtained by dividing the

given decimal number by 16 repeatedly until quotient of zero is obtained.
Decimal to Hex Conversion:

To convert a decimal number into Hex, the number is divided by 16 progressively till
quotient zero is reached. The equivalent Hex for the given decimal is the remainders
obtained in reverse order.

Let us consider an example to better understand decimal to hex conversion.

Example-1: Suppose, we need to convert (115)10 into its equivalent Hex.

Division Generated Remainder

16) 115

16) 7 3

16) 0 7

Reading remainders from bottom to top is the equivalent Hexadecimal number i.e.
(73)16 is the equivalent hex for decimal number 115.

Example-2: Suppose, we need to convert (235)10 into its equivalent Hex.

Reading remainders from bottom to top is the equivalent Hexadecimal number i.e.
(EB)16 is the equivalent hex for decimal number 235.

Hex to Decimal Conversion:

The conversion from a hex to decimal number can be carried out by multiplying each
significant digit of the hex number by its respective weight and adding the products.
This is illustrated in the following example:
Example-1: Convert hex (A3BH)16 into equivalent decimal number.

A3BH

= Ax162+3×161+Bx160

= Ax256 + 3×16 + B

= 10×256 + 48 + 11

= (2619)10 Answer

Hex to Binary Conversion:

Conversion from hexadecimal (hex) to binary and vice versa can easily be carried
out. For arriving at the binary equivalent of a hex number, each significant digit in a
given number is replaced by its 4-bit binary equivalent. Example shown below
illustrate the process of conversion from hex to binary:

The binary equivalent of hex number (2D5)16 is (001011010101)2. Answer

Binary to Hex Conversion:

To convert a binary number into its equivalent hex number, a group of 4-bit is made
starting from the least significant digit. Each group of 4-bit is then replaced by its
equivalent hex number. Example below illustrate the process.

The hex equivalent is (7B5)16. Answer

What is Octal Number System?

A number system which uses only eight digits viz. 0, 1, 2, 3, 4, 5, 6 to 7 is called

Octal Number System. The base or radix of this number system is 8. All the digits
from 0 to 7 in octal system has the same meaning as in decimal system. However,
the decimal numbers from 8 to 15 are represented as 10, 11, 12, 13, 14, 15, 16 & 17
respectively in octal system.

In Octal Number System, each significant position has a positional weight. The least
significant position has a weight of 80 i.e. 1; the higher significant positions are given
weight in the ascending powers of 8 i.e. 81, 82, 83, etc. respectively.

Decimal to Octal Conversion:

To convert a decimal into octal, the decimal number is divided by 8 progressively

until a quotient of 0 is obtained. The remainder in each step of division when read in
reverse order gives the equivalent octal number. This procedure to convert a decimal
into octal number is similar to the double-dabble method.

The method to convert a decimal into octal is explained in the following example.

Suppose, the given decimal number is (444.456)10 and we need to convert this into
its equivalent octal number. As a very first step, we will separate the integer and
fraction part of the decimal number.

To convert integer part of decimal into octal, we will divide the integer by 8
repeatedly till quotient zero is obtained. Record the remainder in each step of
division and arrange them in reverse order. This is shown below.

Division Generated Remainder

8) 444

8) 55 4

8) 6 7

8) 0 6

Reading the remainders from bottom to top, the decimal number (444)10 is equivalent
to octal (674)8.

To convert the fraction part of decimal into octal, multiply the fraction by 8
continuously. Record the carry in the integer position in each multiplication. The
process of multiplication is terminated when the significant digits are obtained. The
carry when read in forward order gives the octal form of the fraction decimal. This is
shown below.
 Multiplication Generated Carry at Integer Position

8×0.456 = 3.648 3

8×0.648 = 5.184 5

8×0.184 = 1.472 1

8×0.472 = 3.776 3

8×0.776 = 6.208 6

Reading the carry from top to bottom gives the equivalent octal number. Therefore,
the decimal (0.456)10 is equivalent to octal (.35136)8.

Thus, the decimal number (444.456)10 is equivalent to octal (674.35136)8.

Octal to Decimal Conversion:

Each significant position in octal has a positional weight. The least significant
position has a weight of 80 i.e. 1; the higher significant positions are given weight in
the ascending powers of 8 i.e. 81, 82, 83, etc. respectively. However, the digits after
the octal point has weight of 8-1, 8-2, 8-3 etc.

Let us consider an octal number (237.45)8. Let us convert this into decimal. First of
all, assigning respective weight; multiply the digits with their positional weight and
add them together. This is shown below.
Thus, the decimal no. is 159.578125 corresponding to octal number (237.45)8.

What is a Karnaugh map (K-map)?

A Karnaugh map (K-map) is a visual method used to simplify the algebraic expressions in
Boolean functions without having to resort to complex theorems or equation manipulations.
A K-map can be thought of as a special version of a truth table that makes it easier to map out
parameter values and arrive at a simplified Boolean expression.

A K-map is best suited for functions with two to four variables. Although K-maps can be
used for functions with five or six variables, the process is more difficult. Using K-maps for
functions with seven or more variables is extremely difficult -- if not impossible.

What is a Karnaugh map example?

The best way to understand how a K-map works is to see one in action, and the place to start
is with a Boolean function. The following function defines a basic Boolean expression that
incorporates the function's four variables:

f(A, B, C, D) = A̅BC̅D + ABC̅D̅ + ABC̅D + ABCD + ABCD̅ + AB̅CD + AB̅CD̅

The expression includes seven products -- based on parameter input -- that are added together
to produce a single binary value. Several of the parameters are shown with a bar over them.
The bar is a logical NOT operator. Like other logical operators in Boolean expressions, the
NOT operator helps to control an expression's logic. When the operator is used, it indicates
that the input value should be inverted to produce a different output value. In other words, if
the input is 0, the output should be 1, or vice versa.

One way to help better understand this expression is to break it down into a truth table.
Because there are four parameters, the table includes a column for each one. The table also
contains a row for each possible combination of parameter values. The last column lists the
function's returned value for each combination.

Decimal A B C D f

0 0 0 0 0 0

1 0 0 0 1 0

2 0 0 1 0 0

3 0 0 1 1 0

4 0 1 0 0 0

5 0 1 0 1 1

6 0 1 1 0 0

7 0 1 1 1 0

8 1 0 0 0 0

9 1 0 0 1 0

10 1 0 1 0 1

11 1 0 1 1 1

12 1 1 0 0 1

13 1 1 0 1 1

14 1 1 1 0 1

15 1 1 1 1 1

The table also includes a column that shows the decimal equivalent for each row -- when
treating the parameters as a single binary value. For example, the value for each parameter in
the last row is 1, so the binary value of the four parameters is 1111, which is equivalent to a
decimal value of 15. The decimal values can make it easier to track and reference the various
combinations, as well as verify a K-map based on the same equation.

Advantages of Karnaugh Map

1. K-map simplification does not demand for the knowledge of Boolean algebraic theorems.
2. Usually it requires less number of steps when compared to algebraic minimization technique.

Disadvantages of Karnaugh Map

1. Complexity of K-map simplification process increases with the increase in the number of
variables
2. The minimum expression obtained might not be unique

What is Gray Code?

Gray code – also known as Cyclic Code, Reflected Binary Code (RBC), Reflected Binary
(RB) or Grey code – is defined as an ordering of the binary number system such that each
incremental value can only differ by one bit. In gray code, while traversing from one step to
another step only one bit in the code group changes. That is to say that two adjacent code
numbers differ from each other by only one bit.

Gray code is the most popular of the unit distance codes, but it is not suitable for arithmetic
operations. Gray code has some applications in analog to digital converters, as well as being
used for error correction in digital communication. Gray code can be difficult to understand
initially, but becomes much easier to understand when looking at the gray code tables below.

Gray Code Table

A table showing the conversion between binary code to gray code and decimal to gray code is
shown below:
Binary to Gray Code Converter

The logical circuit which converts the binary code to equivalent gray code is known as
binary to gray code converter. An n-bit gray code can be obtained by reflecting an n-1 bit
code about an axis after 2n-1 rows and putting the MSB (Most Significant Bit) of 0 above the
axis and the MSB of 1 below the axis. Reflection of Gray codes is shown below.

The 4 bit binary to gray code conversion table is given below:

That means, in 4-bit gray code, (4-1) or 3-bit code is reflected against the axis drawn after the
(24-1)th or 8th row.

The binary to gray code converter circuit is shown below:

How to Convert Binary to Gray Code

1. The MSB (Most Significant Bit) of the gray code will be exactly equal to the first bit of the
given binary number.
2. The second bit of the code will be exclusive-or (XOR) of the first and second bit of the given
binary number, i.e if both the bits are same the result will be 0 and if they are different the
result will be 1.
3. The third bit of gray code will be equal to the exclusive-or (XOR) of the second and third bit
of the given binary number. Thus the binary to gray code conversion goes on. An example is
given below to illustrate these steps.

Laws of Boolean Algebra

Boolean Algebra uses a set of Laws and Rules to define the operation of a digital logic circuit

A set of rules or Laws of Boolean Algebra expressions have been invented to help reduce the
number of logic gates needed to perform a particular logic operation resulting in a list of
functions or theorems known commonly as the Laws of Boolean Algebra.

As well as the logic symbols “0” and “1” being used to represent a digital input or output, we
can also use them as constants for a permanently “Open” or “Closed” circuit or contact
respectively.

Boolean Algebra is the mathematics we use to analyse digital gates and circuits. We can use
these “Laws of Boolean” to both reduce and simplify a complex Boolean expression in an
attempt to reduce the number of logic gates required. Boolean Algebra is therefore a system
of mathematics based on logic that has its own set of rules or laws which are used to define
and reduce Boolean expressions.
The variables used in Boolean Algebra only have one of two possible values, a logic “0” and
a logic “1” but an expression can have an infinite number of variables all labelled
individually to represent inputs to the expression, For example, variables A, B, C etc, giving
us a logical expression of A + B = C, but each variable can ONLY be a 0 or a 1.

Examples of these individual laws of Boolean, rules and theorems for Boolean Algebra are
given in the following table.

Truth Tables
Boolean Equivalent Boolean Algebra
Description
Expression Switching Circuit Law or Rule

A in parallel with
A+1=1 Annulment
closed = “CLOSED”

A in parallel with
A+0=A Identity
open = “A”

A in series with
A.1=A Identity
closed = “A”

A in series with
A.0=0 Annulment
open = “OPEN”

A in parallel with
A+A=A Idempotent
A = “A”

A in series with
A.A=A Idempotent
A = “A”

NOT NOT A
NOT A = A Double Negation
(double negative) = “A”

A in parallel with
A+A=1 Complement
NOT A = “CLOSED”

A in series with
A.A=0 Complement
NOT A = “OPEN”
 A in parallel with B =
A+B = B+A Commutative
B in parallel with A

A in series with B =
A.B = B.A Commutative
B in series with A

invert and replace OR with

A+B = A.B de Morgan’s Theorem
AND

invert and replace AND with

A.B = A+B de Morgan’s Theorem
OR

The basic Laws of Boolean Algebra that relate to the Commutative Law allowing a change
in position for addition and multiplication, the Associative Law allowing the removal of
brackets for addition and multiplication, as well as the Distributive Law allowing the
factoring of an expression, are the same as in ordinary algebra.

Each of the Boolean Laws above are given with just a single or two variables, but the number
of variables defined by a single law is not limited to this as there can be an infinite number of
variables as inputs too the expression. These Boolean laws detailed above can be used to
prove any given Boolean expression as well as for simplifying complicated digital circuits.

A brief description of the various Laws of Boolean are given below with A representing a
variable input.

Description of the Laws of Boolean Algebra

• Annulment Law – A term AND‘ed with a “0” equals 0 or OR‘ed with a “1” will equal 1
•
o A . 0 = 0 A variable AND’ed with 0 is always equal to 0
o A + 1 = 1 A variable OR’ed with 1 is always equal to 1
•
• Identity Law – A term OR‘ed with a “0” or AND‘ed with a “1” will always equal that term
•
o A + 0 = A A variable OR’ed with 0 is always equal to the variable
o A . 1 = A A variable AND’ed with 1 is always equal to the variable
•
• Idempotent Law – An input that is AND‘ed or OR´ed with itself is equal to that input
•
o A + A = A A variable OR’ed with itself is always equal to the variable
o A . A = A A variable AND’ed with itself is always equal to the variable
•
• Complement Law – A term AND‘ed with its complement equals “0” and a term OR´ed with its
complement equals “1”
•
o A . A = 0 A variable AND’ed with its complement is always equal to 0
o A + A = 1 A variable OR’ed with its complement is always equal to 1
 •
• Commutative Law – The order of application of two separate terms is not important
•
o A . B = B . A The order in which two variables are AND’ed makes no difference
o A + B = B + A The order in which two variables are OR’ed makes no difference
•
• Double Negation Law – A term that is inverted twice is equal to the original term
•
o A =A A double complement of a variable is always equal to the variable
•
• de Morgan’s Theorem – There are two “de Morgan’s” rules or theorems,
•
• (1) Two separate terms NOR‘ed together is the same as the two terms inverted
(Complement) and AND‘ed for example: A+B = A . B
•
• (2) Two separate terms NAND‘ed together is the same as the two terms inverted
(Complement) and OR‘ed for example: A.B = A + B

Other algebraic Laws of Boolean not detailed above include:

• Boolean Postulates – While not Boolean Laws in their own right, these are a set of
Mathematical Laws which can be used in the simplification of Boolean Expressions.
•
o 0 . 0 = 0 A 0 AND’ed with itself is always equal to 0
o 1 . 1 = 1 A 1 AND’ed with itself is always equal to 1
o 1 . 0 = 0 A 1 AND’ed with a 0 is equal to 0
o 0 + 0 = 0 A 0 OR’ed with itself is always equal to 0
o 1 + 1 = 1 A 1 OR’ed with itself is always equal to 1
o 1 + 0 = 1 A 1 OR’ed with a 0 is equal to 1
o 1 = 0 The Inverse (Complement) of a 1 is always equal to 0
o 0 = 1 The Inverse (Complement) of a 0 is always equal to 1
•
• Distributive Law – This law permits the multiplying or factoring out of an expression.
•
o A(B + C) = A.B + A.C (OR Distributive Law)
o A + (B.C) = (A + B).(A + C) (AND Distributive Law)
•
• Absorptive Law – This law enables a reduction in a complicated expression to a simpler one
by absorbing like terms.
•
o A + (A.B) = (A.1) + (A.B) = A(1 + B) = A (OR Absorption Law)
o A(A + B) = (A + 0).(A + B) = A + (0.B) = A (AND Absorption Law)
•
• Associative Law – This law allows the removal of brackets from an expression and regrouping
of the variables.
•
o A + (B + C) = (A + B) + C = A + B + C (OR Associate Law)
o A(B.C) = (A.B)C = A . B . C (AND Associate Law)
Boolean Algebra Functions

Using the information above, simple 2-input AND, OR and NOT Gates can be represented by
16 possible functions as shown in the following table.

Function Description Expression

1. NULL 0

2. IDENTITY 1

3. Input A A

4. Input B B

5. NOT A A

6. NOT B B

7. A AND B (AND) A.B

8. A AND NOT B A.B

9. NOT A AND B A.B

10. NOT AND (NAND) A.B

11. A OR B (OR) A+B

12. A OR NOT B A+B

13. NOT A OR B A+B

14. NOT OR (NOR) A+B

15. Exclusive-OR A.B+A.B

16. Exclusive-NOR A.B+A.B

Laws of Boolean Algebra Example No1

Using the above laws, simplify the following expression: (A + B)(A + C)

Q = (A + B).(A + C)

A.A + A.C + A.B + B.C – Distributive law

A + A.C + A.B + B.C – Idempotent AND law (A.A = A)

A(1 + C) + A.B + B.C – Distributive law

 A.1 + A.B + B.C – Identity OR law (1 + C = 1)

A(1 + B) + B.C – Distributive law

A.1 + B.C – Identity OR law (1 + B = 1)

Q = A + (B.C) – Identity AND law (A.1 = A)

Then the expression: (A + B)(A + C) can be simplified to A + (B.C) as in the Distributive

law.

DeMorgan’s Theorem
DeMorgan´s Theorem and Laws can be used to to find the equivalency of the NAND and
NOR gates

DeMorgan’s Theorem uses two sets of rules or laws to solve various Boolean algebra
expressions by changing OR’s to AND’s, and AND’s to OR’s

Boolean Algebra uses a set of laws and rules to define the operation of a digital logic circuit
with “0’s” and “1’s” being used to represent a digital input or output condition. Boolean
Algebra uses these zeros and ones to create truth tables and mathematical expressions to
define the digital operation of a logic AND, OR and NOT (or inversion) operations as well as
ways of expressing other logical operations such as the XOR (Exclusive-OR) function.

While George Boole’s set of laws and rules allows us to analyise and simplify a digital
circuit, there are two laws within his set that are attributed to Augustus DeMorgan (a
nineteenth century English mathematician) which views the logical NAND and NOR
operations as separate NOT AND and NOT OR functions respectively.

But before we look at DeMorgan’s Theory in more detail, let’s remind ourselves of the basic
logical operations where A and B are logic (or Boolean) input binary variables, and whose
values can only be either “0” or “1” producing four possible input combinations, 00, 01, 10,
and 11.

Truth Table for Each Logical Operation

Input Variable Output Conditions

A B AND NAND OR NOR

0 0 0 1 0 1
0 1 0 1 1 0

1 0 0 1 1 0

1 1 1 0 1 0

The following table gives a list of the common logic functions and their equivalent Boolean
notation where a “.” (a dot) means an AND (product) operation, a “+” (plus sign) means an
OR (sum) operation, and the complement or inverse of a variable is indicated by a bar over
the variable.

Logic Function Boolean Notation

AND A.B

OR A+B

NOT A

NAND A .B

NOR A+B

DeMorgan’s Theory

DeMorgan’s Theorems are basically two sets of rules or laws developed from the Boolean
expressions for AND, OR and NOT using two input variables, A and B. These two rules or
theorems allow the input variables to be negated and converted from one form of a Boolean
function into an opposite form.

DeMorgan’s first theorem states that two (or more) variables NOR´ed together is the same as
the two variables inverted (Complement) and AND´ed, while the second theorem states that
two (or more) variables NAND´ed together is the same as the two terms inverted
(Complement) and OR´ed. That is replace all the OR operators with AND operators, or all
the AND operators with an OR operators.

DeMorgan’s First Theorem

DeMorgan’s First theorem proves that when two (or more) input variables are AND’ed and
negated, they are equivalent to the OR of the complements of the individual variables. Thus
the equivalent of the NAND function will be a negative-OR function, proving that
A.B = A+B. We can show this operation using the following table.

Verifying DeMorgan’s First Theorem using Truth Table

Inputs Truth Table Outputs For Each Term

B A A.B A.B A B A+B

0 0 0 1 1 1 1

0 1 0 1 0 1 1

1 0 0 1 1 0 1

1 1 1 0 0 0 0

We can also show that A.B = A+B using logic gates as shown.

DeMorgan’s First Law Implementation using Logic Gates

The top logic gate arrangement of: A.B can be implemented using a standard NAND gate
with inputs A and B. The lower logic gate arrangement first inverts the two inputs producing
A and B. These then become the inputs to the OR gate. Therefore the output from the OR
gate becomes: A+B

Then we can see here that a standard OR gate function with inverters (NOT gates) on each of
its inputs is equivalent to a NAND gate function. So an individual NAND gate can be
represented in this way as the equivalency of a NAND gate is a negative-OR.

DeMorgan’s Second Theorem

DeMorgan’s Second theorem proves that when two (or more) input variables are OR’ed and
negated, they are equivalent to the AND of the complements of the individual variables. Thus
the equivalent of the NOR function is a negative-AND function proving that A+B = A.B, and
again we can show operation this using the following truth table.
Verifying DeMorgan’s Second Theorem using Truth Table
Inputs Truth Table Outputs For Each Term

B A A+B A+B A B A.B

0 0 0 1 1 1 1

0 1 1 0 0 1 0

1 0 1 0 1 0 0

1 1 1 0 0 0 0

We can also show that A+B = A.B using the following logic gates example.

DeMorgan’s Second Law Implementation using Logic Gates

The top logic gate arrangement of: A+B can be implemented using a standard NOR gate
function using inputs A and B. The lower logic gate arrangement first inverts the two inputs,
thus producing A and B. Thus then become the inputs to the AND gate. Therefore the output
from the AND gate becomes: A.B

Then we can see that a standard AND gate function with inverters (NOT gates) on each of its
inputs produces an equivalent output condition to a standard NOR gate function, and an
individual NOR gate can be represented in this way as the equivalency of a NOR gate is a
negative-AND.

Although we have used DeMorgan’s theorems with only two input variables A and B, they
are equally valid for use with three, four or more input variable expressions, for example:
For a 3-variable input

A.B.C = A+B+C

and also

A+B+C = A.B.C

For a 4-variable input

A.B.C.D = A+B+C+D

and also

A+B+C+D = A.B.C.D

and so on.

DeMorgan’s Equivalent Gates

We have seen here that by using DeMorgan’s Theorems we can replace all of the AND (.)
operators with an OR (+) and vice versa, and then complements each of the terms or variables
in the expression by inverting it, that is 0’s to 1’s and 1’s to 0’s before inverting the entire
function.

Thus to obtain the DeMorgan equivalent for an AND, NAND, OR or NOR gate, we simply
add inverters (NOT-gates) to all inputs and outputs and change an AND symbol to an OR
symbol or change an OR symbol to an AND symbol as shown in the following table.

DeMorgan’s Equivalent Gates

Standard Logic Gate DeMorgan’s Equivalent Gate
Then we have seen in this tutorial about DeMorgan’s Thereom that the complement of two
(or more) AND’ed input variables is equivalent to the OR of the complements of these
variables, and that the complement of two (or more) OR’ed variables is equivalent to the
AND of the complements of the variables as defined by DeMorgan.

CLASSIFICATIOPN OF LOGIC FAMILY

The two basic techniques for manufacturing ICs are:

1. Bipolar Technology
2. Metal oxide semiconductor (MOS) technology.

Bipolar Families:

• The bipolar families of logic circuits construct, especially from components fabricate bipolar
transistors on the chip.
• In the bipolar category, there are three basic families called Diode transistor logic(DTL),
Transistor Transistor Logic(TTL), and Emitter Coupled Logic (ECL).
• DTL uses diodes and transistors, TTL uses transistors almost exclusively, TTL has become the
most popular family in SSI (Small scale integration) and MSI(medium-scale integration) chips,
while ECL is the fastest logic family which is used for high-speed applications.
MOS Families:

• The MOS family fabricates the MOS field effect transistors (MOSFETs).
• In the MOS category, there are three logic families namely PMOS(p-channel MOSFETs) family,
NMOS(n-channel MOSFET) family, and CMOS(Complementary MOSFET) family.
• PMOS is the oldest and slowest type. NMOS is used for LSI(large-scale integration) field for
microprocessors and memories.
• CMOS which uses a push-pull arrangement of n-channel and p-channel MOSFETs is
extensively used where low power consumption is needed such as in pocket calculators.

In the “Bipolar saturated” logic families, the bipolar transistors are used as the main device. It
is used at the switch and operated in the saturation and cutoff regions.

TTL is an example of saturated bipolar logic.

In the unsaturated bipolar logic, the bipolar transistor is not driven into hard saturation. This
increases the speed of operation.

So, the unsaturated bipolar ICs such as Schottky TTL and ECL are much faster as
compared to TTL.

All these ICs are fabricated on silicon chips using different fabrication technologies.

Characteristics of the digital logic family

Propagation delay

It is the time interval between the application of the input pulse and the occurrence of the
output. It is an important characteristic of the digital logic family. If the propagation delay is
less, then the speed at which the IC operates will be faster.

Let THL is the propagation delay when the output changes from logic 0 to 1 and TLH is the
delay when the output changes from logic 1 to 0. The maximum value of THL and TLH is
considered as the propagation delay for that logic gate.

Fan in and Fan out

Fan-in refers to the number of inputs in a digital logic gate family. For the example given in
the figure below, the EX-OR gate has three inputs. So fan-in for the given EX-OR gate is 3.

Fan-out refers to the number of inputs that is driven by the output of another logic gates. For
example, the following circuit has an EX-OR gate, which drives 4 NOT gates. So fan-out of
EX-OR gate is 4.
Both fan-in and fan-out values are given by the manufacturer at the time of designing and the
data is specified in the datasheet. When the number of inputs or outputs are changed, it may
cause some malfunction to the device.

Power dissipation

It is the amount of power that the digital circuit dissipates. The power dissipated is
determined by the average current, that is drawn from the supply voltage.

The average current is the average value of the current at LOW gate output(logic ‘o’) and the
current at HIGH gate output(logic ‘1’).

Noise Immunity and Noise margin

What is Noise?

It is an unwanted signal that is superimposed on the normal operating signal. Noise may be
due to various factors like operating environment, radiations, stray electrical and magnetic
fields.

In digital logic circuits, the binary values 0 and 1 represent the LOW and HIGH voltage
levels. Due to the interference of the noises, the voltage levels may increase or decrease. This
may lead to the wrong operation of the device.

The noise immunity is the ability of the logic device to tolerate the noise without causing
spurious change to the output voltage. Noise margin allows the logic device to function
properly within the specified limits.

Figure of merit

For an efficient operation of any device, whether it may be digital or analog, the power
dissipation and the speed are notable characteristics. Achieving a higher speed with less
power dissipation is a highly challenging task.
In the digital logic circuit, a trade-off exists between these two characteristics. That is, for
higher speed, the power dissipation will be more.

The figure of merit or Speed Power Product is a common means of measuring the
performance of circuits in the digital logic family.

Flip flops can be used to store a single bit of binary data (1 or 0). However, in order to store
multiple bits of data, we need multiple flip-flops. N flip flops are to be connected in order to
store n bits of data. A Register is a device that is used to store such information. It is a group
of flip-flops connected in series used to store multiple bits of data. The information stored
within these registers can be transferred with the help of shift registers.

Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in such
registers can be made to move within the registers and in/out of the registers by applying clock
pulses. An n-bit shift register can be formed by connecting n flip-flops where each flip-flop
stores a single bit of data. The registers which will shift the bits to the left are called “Shift left
registers”. The registers which will shift the bits to the right are called “Shift right registers”.
Shift registers are basically of following types.

Types of Shift Registers

• Serial In Serial Out shift register

• Serial In parallel Out shift register
• Parallel In Serial Out shift register
• Parallel In parallel Out shift register
• Bidirectional Shift Register
• Universal Shift Register
• Shift Register Counter

Serial-In Serial-Out Shift Register (SISO)

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as a Serial-In Serial-Out shift register. Since there is only
one output, the data leaves the shift register one bit at a time in a serial pattern, thus the name
Serial-In Serial-Out Shift Register. The logic circuit given below shows a serial-in serial-out
shift register. The circuit consists of four D flip-flops which are connected in a serial manner.
All these flip-flops are synchronous with each other since the same clock signal is applied to
each flip-flop.
Serial-In Serial-Out Shift Register (SISO)

The above circuit is an example of a shift right register, taking the serial data input from the
left side of the flip flop. The main use of a SISO is to act as a delay element.

Serial-In Parallel-Out Shift Register (SIPO)

The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as the Serial-In Parallel-Out shift register. The logic
circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four D
flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock
signal to all 4 flip flops in order to RESET them. The output of the first flip-flop is connected
to the input of the next flip flop and so on. All these flip-flops are synchronous with each other
since the same clock signal is applied to each flip-flop.

Serial-In Parallel-Out shift Register (SIPO)

The above circuit is an example of a shift right register, taking the serial data input from the
left side of the flip-flop and producing a parallel output. They are used in communication lines
where demultiplexing of a data line into several parallel lines is required because the main use
of the SIPO register is to convert serial data into parallel data.

Parallel-In Serial-Out Shift Register (PISO)

The shift register, which allows parallel input (data is given separately to each flip flop and in
a simultaneous manner) and produces a serial output is known as a Parallel-In Serial-Out shift
register. The logic circuit given below shows a parallel-in-serial-out shift register. The circuit
consists of four D flip-flops which are connected. The clock input is directly connected to all
the flip-flops but the input data is connected individually to each flip-flop through a multiplexer
at the input of every flip-flop. The output of the previous flip-flop and parallel data input are
connected to the input of the MUX and the output of MUX is connected to the next flip-flop.
All these flip-flops are synchronous with each other since the same clock signal is applied to
each flip-flop.
Parallel-In Serial-Out Shift Register (PISO)

A Parallel in Serial Out (PISO) shift register is used to convert parallel data to serial data.

Parallel-In Parallel-Out Shift Register (PIPO)

The shift register, which allows parallel input (data is given separately to each flip flop and in
a simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-
Out shift register. The logic circuit given below shows a parallel-in-parallel-out shift register.
The circuit consists of four D flip-flops which are connected. The clear (CLR) signal and clock
signals are connected to all 4 flip-flops. In this type of register, there are no interconnections
between the individual flip-flops since no serial shifting of the data is required. Data is given
as input separately for each flip flop and in the same way, output is also collected individually
from each flip flop.
Parallel-In Parallel-Out Shift Register (PIPO)

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like
SISO Shift register it acts as a delay element.

Bidirectional Shift Register

If we shift a binary number to the left by one position, it is equivalent to multiplying the number
by 2 and if we shift a binary number to the right by one position, it is equivalent to dividing the
number by 2. To perform these operations we need a register which can shift the data in either
direction. Bidirectional shift registers are the registers that are capable of shifting the data either
right or left depending on the mode selected. If the mode selected is 1(high), the data will be
shifted toward the right direction and if the mode selected is 0(low), the data will be shifted
towards the left direction. The logic circuit given below shows a Bidirectional shift register.
The circuit consists of four D flip-flops which are connected. The input data is connected at
two ends of the circuit and depending on the mode selected only one gate is in the active state.

Bidirectional Shift Register

Universal Shift Register

Universal Shift Register is a type of register that contains the both right shift and the left shift.
It has also parallel load capabilities. Generally, these types of registers are taken as memory
elements in computers. But, the problem with this type of register is that it shifts only in one
direction. In simple words, you mean that the universal shift register is a combination of the
bidirectional shift register and the unidirectional shift register.
Universal Shift Register

N-bit universal shift register consists of flip-flops and multiplexers. Both are N in size. In this,
all the n multiplexers share the same select lines and this select input selects the suitable input
for flip-flops.

Universal gates - NAND and NOR.

• NAND Gate: The NAND gate represents the complement of the AND operation.
• Its name is an abbreviation of NOT AND.
• The graphic symbol for the NAND gate consists of an AND symbol with a bubble on
the output, denoting that a complement operation is performed on the output of the
AND gate.
• The truth table and the graphic symbol of NAND gate is shown in the figure.
The truth table clearly shows that the NAND operation is the complement of the AND.

• NOR Gate: The NOR gate represents the complement of the OR operation.
• Its name is an abbreviation of NOT OR.
• The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the
output, denoting that a complement operation is performed on the output of the OR
gate.
• The truth table and the graphic symbol of NOR gate is shown in the figure.

NAND Gate is a Universal Gate: To prove that any Boolean function can be implemented
using only NAND gates, we will show that the AND, OR, and NOT operations can be
performed using only these gates. Implementing an Inverter Using only NAND Gate The
figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).

1. All NAND input pins connect to the input signal A gives an output A’.

1. One NAND input pin is connected to the input signal A while all other input pins are
connected to logic 1. The output will be A’.

Implementing AND Using only NAND Gates

An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced
by a NAND gate with its output complemented by a NAND gate inverter).
Implementing OR Using only NAND Gates

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced
by a NAND gate with all its inputs complemented by NAND gate inverters).

Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT
functions.

NAND Gate is a Universal Gate: To prove that any Boolean function can be implemented
using only NOR gates, we will show that the AND, OR, and NOT operations can be
performed using only these gates. Implementing an Inverter Using only NOR Gate

The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).

1. All NOR input pins connected to the input signal A gives an output A’.

1. One NOR input pin is connected to the input signal A while all other input pins are
connected to logic 0. The output will be A’.

Implementing OR Using only NOR Gates

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a
NOR gate with its output complemented by a NOR gate inverter)
Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT
functions.

Ripple counters are also known as asynchronous counters because each flipflop is triggered
by the output of the previous flipflop.

• A ripple counter with n flipflops can have 2n states

• The clock pulse which we give externally is fed into flipflop and is rippled or moved
throough the other counters after some propagation delays, like ripplr on the water,
hence the name ripple counter.

3-bit Up Down Counter

• The inputs of the flipflop has set to high

• Based on the control signals UP and DOWN, the counter performs its operation

Case-1:

If UP=1 and DOWN=0, then

the NAND network between FF0 and FF1 will give the non-inverted output "Q" of FF0 as the
clock input of FF1.

Similarly, the output Q of FF1 will be given through other NAND network into the clock
input of FF2. Thus the counter will count "UP".

Case-2:

If UP=0 and DOWN=1, then

the inverted outputs of FF0 and FF1 (i.e. Q' and Q1') are given as the clock inputs of FF1 and
FF2 respectively.

If the flipflops are originally reset to zeros, then the counter will count downwards as input
pulses are applied.

Table:
Q2 Q1 Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Note:

• An UP counter using n flifpflops counts upward from a minimum count i.e. from 0 to
2n-1
• A DOWN counter using n flipflops counts downwards from a maximum of 2n-1 to 0

DIGITAL ELECTRONICS

Q1. Attempt any three questions. 3x5=15

i. What the combinational and sequential circuits? Differentiate them.
ii. Subtract 14 from 25 using the 1’s complement method of subtraction.
iii. Explain ASCII code and convert a binary 1000011 to gray code.
iv. Discuss De Morgan’s theorem with suitable example.
v. Discuss the characteristics of Logic Families.
vi. Determine the single error correcting code for the BCD number1001 (information bits)
using even
parity.
vii. Explain Serial to Parallel Shift Register.
SECTION-B
Attempt any one question. 1x10=10
Q2. a) Explain the universal property of NAND gate.
b) Design 3-bit ripple counters.
Q3. Draw the Karnaugh Map for the following of four variables
a. F(A,B,C,D)=∑m(1,2,,4,5,8,10,11,14)
b. Differences between an analog and a digital signal.
Q4. Write a short note on any two
(a) Full Subtractor b) 4: 1 MUX c) Successive approximation A/D Converter.
Q5. Difference between Latch and flip flop. Explain the working principle of any two flip flops
and its truth table.