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Department of Electronics and Communication Engineering

University Questions Topic-wise
I
Unit-3
I
(ASSIGNMENTS- 5 & 6)

Date of issue: 22-10-2020

Dat e of sub mission: 31-10-2020

ASSIGNMENTS- 5: Synchronous and Asynchronous Sequential Circuit, Latch,

Flip-flops, Race around condition, Analysis and Design of clocked Sequential
Circuit, State Reduction & Assignments, FSM.

ASSIGNMENTS- 6: Shift Registers, Counters

- ··-

~-
No.
Latch, Flip-flops, Race around conditL.> n Marks Year l
\t- - - --
~ ompare sy nchronous and Asy nchronous seq uenti a l circuit. 2 20 I 6-1 7
Write the truth ta bl e of th e SR, D & T flip-Jlops . 10 2019-20
'-v Write the truth table of the SR, JK, D & T ilip-Jl ops. 7 2018- 19
--•--
With the help of logic diagram, explain work ing of Master sla ve JK Flip-
J-~ Flop along wi th wa ve fo rms. Explain race aro und condition . How is it 10 2019-20
elim inated ? . ------·-- - - - ---
~ - What are the applications of Flip-Flops? 2 2018 - 19
- What do you mea n by race around condition in JK Fli p F lop? 2 2019-20
What do yo u mean by race around condition? 2 20 18-19
··-- -
\. ✓ What do you mean by race around condition in JK Fl ip Flo1t 2 2018-19
_What do youmean by race around condition? -
' .
.
2 20 18-19
Wha~ do yo u m ean b~ race around condition?
1 2 20 17-18 ..
·/ Disting ui sh b~twce n Leach and Flie Flo2. 2 2019-20
6 2
Distingui sh_betwee n Leach and F lip Flop. 2016-17
~ - --

Convert SR to JK l·'F. 7 2018-19

. - - ·------- --- ------- --
a) Con ve rt an SR nip flop into ( i) T-flip flop (ii) JK flip fl o p? 5 20 18- 19
y ----- - ·- - - -- -· -- -- - -- ----·---- · -- ·---
Convert a D fl ip flu p into (i ) T-flip flop (ii) JK !lip !l o p'? 10 2018 - 19
--- -- .. ·------- - - -· ---- -- · --------- . .
Differentiate be tween Flip flop and latch ? Convert SR Flip fl op in to
10 2018-19
-- -------
_p flip flop . -------- ... -- -- -- - - - -- - - -- --
V Write excitation table and char eqn of JK Flip flop . 2 2017-18
8
------ -
f - - ··

Express the characteristic equation for the JK flipflop .

---- - - ---- -· ---
2 2016- 17 J
1,1)--- What arc the di!Tcrcnt types of FFs?
-- --- - --- ---- -- - - -- -·· ·-·· -
Give the function table of SR latch.
- - - -- . -
2
2
2016-17
- - -- ---
20 16-17
--
Explain JfCi=F-:-what is race around condition in JK FF ancTwhat is its 2015-16
v ]\ 10

Q.
remedy? ---
Design of clocked Sequential Circuit Marks Year
No.
For the given state diagram design the circuit using T flip flop

, -t.,11 111..t_,.,
I ,' 11 11·7, l ',,
10 2019-20
1 / \y ,
,., ;.\'.no),
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. _)- \
(~ ,/ - Hll)
,..'...,
~ ·----..__ ,.--- /
.· I:

():'0 ' \ J()!))·· ~

0 0,1,
Design a sequential circuit with two Flip Flops, A & B and one
inp ut x. When x "u, the State of the circuit remains the same when
0

10 2019-20
2
x= 1 the circuit pas~es through the state t~ansitions from 00 to 0 i to
l f to IO b~ck t~, _00 & repeat. ·___ · · · '
The Boolean functions for the inputs of an SR latcb are
--
S = .\"1 .Y -, .\".. +..r1 :r -:_X
. :,,
,.,
.)
R -- -r ,·
-
-- ,.- . IO 2018-19
1 - ~'l T .•i ' .
·. - ·'
.
-
Obtain the circuit diagr~rn , using a minimum number ofNAND
gates?
A sequential circuit has two JK flip-flops A and B, two
inputs, x and y and one output, z. The flip-flop input
equations are :

JA =Bx+
,,.
B'y'
.,
KA=~' xy'
,,

4 JI) =A'x KB=A +xy' 10 2015-16

Z=Ax.y+Bx'y' 1/
Obtain the Jogic diagram, state table, state diagram and
state equations.

-- - ---·---- ----- - ·--- - ----- - - --- - - --- -----,---,---:--- : - - -- - - - - - - -- -+-- - - --+-- - ---1
Design a clocked sequential circug that operates
s according to the smte·diagrain shown:
10 2015-16
--- --- ---~ -- ~ - -- - ~ ~ - -- - - - -- - -- - - - -...L......--- -'-- - - _ _ J
 -- --- -- . -- -- - --c - - - - - - --

lmp lem ent the circ uit using D Flip-Flop . •

~-- -- -- A sequential circ uit has two JK flip-
flops A and B, two inpu ts X and
Y, and one outp ut Z. The flip-flop input
equations are:
JA= BX+ B'Y '
KA= B'X 'Y
6 JB= A'X
10 2015-16
KB= A+X Y'
Z=A XY +BX 'Y'
a) Dra w the logic diag ram
b) Der ive the state equ atio ns.
c) Obt ain the state table, state diagram.
Q.
No. Analysis of clocked Sequential Circuit, Sta
te Reduction Ma rks Yea r
Derive state table and state diagram .
.. )

..>
I ) '
.

7 20 18-1 9
J. -
--- t> ,.

Cf'
 SC

I n,
•O

Q.
No. FSM Marks Year
Construct Moore and Mealy state diagram that will detect input sequence
10110, when input pattern is ~ete~ted, z is asserted_high . Give state 10 2019-20
dia ram for each state. ~

Compare n~ealy and Moore model of finite state machine. 2 2016-17

Shift Register Marks Year

What is Shift R~gister? Why its needed? Discus$ bidirectional Shift
Register? 7 2018-19
.__
2 · Draw and explain Pl?O and Pl(>O regi ster. 7 2017-18
Draw an1 exp lain lJ.niversal shift n:;gister. 7 2017-18
v 3
Draw and expl~in 4-bit Univers~l shif'.t Register. 2016-17,
10
2015-16
v/ 4 Discuss the
.. application
. of Shift register? 2 2017-18
. ~

The contents of a f9ur ~it r~gist~r are initially l 0 1.1 . The register is
shifted six_tirn~s to ~the right wi_th serial input bei_ng 101111.. What 2 2016-17
are the contents of the register after eac h shift ·
Write the steps, ·that must be taken for the purpose of transferring a
new word to be s!ored into memory. 2 2016-17

What is Shift Register? Explain in detail.

• f
10 2015 -16
' • •

Q.
Counter Marks Year
No.
-~~ hat is the difference between Synchronous and Asynchronou s Counters? 2 20 18-1 9
 I
I De·sign a BCD counter with JK flip flops. 10 2019-20
i 2 2018-19
Design a BCD counter with JK flip flops. 7
-
Design a ripple decade counter. 7 2018-19
3 What is 1nodulus of a counter? 2 2018-19
4 Design MOD 11 synchronous counter using T flip flop. 10 2019-20
Differentiate between asynchronou s and synchronous sequential
5 circuit. Also design MOD 5 asynchronou s counter using JK flip 10 2018-19
I flop.
What is asynchronous counter? How would you design asynchronous 7 2018-19
6
counter?
How many FFs required mod 5 Ring counter and mod 5 Johnson 2 2018-19
7
counter? --
Describe the operation of fo~tr bit synchronous 10 2016-17
8
binary counter with neat sketch.
How many flip fl op will be complemented in an 8-bit ripple counter to 2 2018-19
9 reach the next count after the fol lowing count 10110111?
Differentiate between asynchronous counter and synchronous
10 counter? Design and implement Two-Bit-Rip ple up-counter using 10 2018-19
positive edge-triggere d J-K Flip-flop.
11 Design Mod 3 up/down counter. 7 2018-19
12 Design and i1nple1nent 3-Bit-Ripple up-down counter 7 2017-18
What is the difference betwaeen Synchronous and
13 Asynchronou s Counters? Explain in detail Design a 4- 10 2015-16
bit Synchronous UP/DOWN Counter.
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