HI-3582A, HI-3583A

ARINC 429
July 2013
3.3V Terminal IC with High-Speed Interface
GENERAL DESCRIPTION APPLICATIONS
The HI-3582A/HI-3583A from Holt Integrated Circuits are • Avionics data communication
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The • Serial to parallel conversion
HI-3582A/HI-3583A design offers a high-speed host CPU • Parallel to serial conversion
interface compared with the earlier HI-3582/HI-3583
products. The device provides two receivers each with
label recognition, 32 by 32 FIFO, and analog line receiver. PIN CONFIGURATIONS (Top View)
Up to 16 labels may be programmed for each receiver. (See page 14 for additional pin configuration)

The independent transmitter has a 32 X 32 FIFO and a See Note below

52 - TXCLK
built-in line driver. The status of all three FIFOs can be

63 - RIN2B
62 - RIN2A
61 - RIN1B
60 - RIN1A

54 - TEST

50 - RSR
56 - VDD
58 - VDD
57 - VDD

51 - CLK

49 - N/C
55 - N/C
59 - N/C
64 - N/C

53 - MR
monitored using the external status pins, or by polling the
HI-3582A/HI-3583A status register. Other features include
a programmable option of data or parity in the 32nd bit, N/C - 1
D/R1 - 2
48 - CWSTR
47 - ENTX
FF1 - 3 HI-3582APCI 46 - N/C
and the ability to unscramble the 32 bit word. Also, HF1 - 4 45 - V+
D/R2 - 5 HI-3582APCT 44 - TXBOUT
versions are available with different values of input FF2 - 6
HF2 - 7 HI-3582APCM 43 - TXAOUT
42 - V-
resistance and output resistance to allow users to more SEL - 8
EN1 - 9 & 41 - N/C
40 - FFT
easily add external lightning protection circuitry. EN2 - 10
N/C - 11 HI-3583APCI 39 - HFT
38 - TX/R
BD15 - 12 37 - PL2
The 16-bit parallel data bus exchanges the 32-bit ARINC BD14 - 13 HI-3583APCT 36 - PL1
BD13 - 14 35 - BD00
BD12 - 15 HI-3583APCM 34 - BD01
data word in two steps when either loading the transmitter BD11 - 16 33 - N/C

or interrogating the receivers. The databus and all control

N/C - 32
BD03 - 30
BD02 - 31
N/C - 27
BD05 - 28
BD04 - 29
N/C - 24
N/C - 25
N/C - 26
BD06 - 22
GND - 23
BD07 - 21
N/C - 17
BD10 - 18
BD09 - 19
BD08 - 20
signals are 3.3V CMOS compatible.
The HI-3582A/HI-3583A apply the ARINC protocol to the (Note: All 3 VDD pins must be connected to the same 3.3V supply)
receivers and transmitter. Timing is based on a 1 Mega-
64 - Pin Plastic 9mm x 9mm
hertz clock. Chip-Scale Package
43 - TXCLK
48 - RIN1A
49 - RIN1B
50 - RIN2A
51 - RIN2B

45 - TEST
52 - D/R1

41 - RSR
47 - VDD

42 - CLK

40 - N/C
46 - N/C

44 - MR

FEATURES
· ARINC specification 429 compatible
· High-speed 3.3V logic interface
· Dual receiver and transmitter interface
FF1 - 1 39 - N/C
· Analog line driver and receivers connect directly to HF1 - 2 38 - CWSTR
ARINC bus D/R2 - 3 HI-3582APQI 37 - ENTX
· Programmable label recognition FF2 - 4 HI-3582APQT 36 - V+
HF2 - 5 35 - TXBOUT
· On-chip 16 label memory for each receiver SEL - 6 HI-3582APQM 34 - TXAOUT
· 32 x 32 FIFOs each receiver and transmitter EN1 - 7 & 33 - V-
· Independent data rate selection for transmitter and EN2 - 8 HI-3583APQI 32 - FFT
BD15 - 9 31 - HFT
each receiver BD14 - 10 HI-3583APQT 30 - TX/R
· Status register BD13 - 11 HI-3583APQM 29 - PL2
· Data scramble control BD12 - 12 28 - PL1
BD11 - 13 27 - BD00
· 32nd transmit bit can be data or parity
· Self test mode
· Low power
BD01 - 26
BD02 - 25
BD03 - 24
BD04 - 23
BD05 - 22
N/C - 21
GND - 20
N/C - 19
BD06 - 18
BD07 - 17
BD08 - 16
BD09 - 15
BD10 - 14

· Industrial & extended temperature ranges

52 - Pin Plastic Quad Flat Pack (PQFP)

HOLT INTEGRATED CIRCUITS

((DS3582A Rev. C) www.holtic.com 07/13
 HI-3582A, HI-3583A

PIN DESCRIPTIONS

SIGNAL FUNCTION DESCRIPTION

VDD POWER +3.3V power supply pin
RIN1A INPUT ARINC receiver 1 positive input
RIN1B INPUT ARINC receiver 1 negative input
RIN2A INPUT ARINC receiver 2 positive input
RIN2B INPUT ARINC receiver 2 negative input
D/R1 OUTPUT Receiver 1 data ready flag
FF1 OUTPUT FIFO full Receiver 1
HF1 OUTPUT FIFO Half full, Receiver 1
D/R2 OUTPUT Receiver 2 data ready flag
FF2 OUTPUT FIFO full Receiver 2
HF2 OUTPUT FIFO Half full, Receiver 2
SEL INPUT Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1 INPUT Data Bus control, enables receiver 1 data to outputs
EN2 INPUT Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15 I/O Data Bus
BD14 I/O Data Bus
BD13 I/O Data Bus
BD12 I/O Data Bus
BD11 I/O Data Bus
BD10 I/O Data Bus
BD09 I/O Data Bus
BD08 I/O Data Bus
BD07 I/O Data Bus
BD06 I/O Data Bus
GND POWER 0V
BD05 I/O Data Bus
BD04 I/O Data Bus
BD03 I/O Data Bus
BD02 I/O Data Bus
BD01 I/O Data Bus
BD00 I/O Data Bus
PL1 INPUT Latch enable for byte 1 entered from data bus to transmitter FIFO.
PL2 INPUT Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
TX/R OUTPUT Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
HFT OUTPUT Transmitter FIFO Half Full
FFT OUTPUT Transmitter FIFO Full
V- POWER -9.5V to -10.5V
TXAOUT OUTPUT Line driver output - A side
TXBOUT OUTPUT Line driver output - B side
V+ POWER +9.5V to +10.5V
ENTX INPUT Enable Transmission
CWSTR INPUT Clock for control word register
RSR INPUT Read Status Register if SEL=0, read Control Register if SEL=1
CLK INPUT Master Clock input
TX CLK OUTPUT Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
MR INPUT Master Reset, active low
TEST INPUT Disable Transmitter output if high (pull-down)

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 HI-3582A, HI-3583A

FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER STATUS REGISTER
The HI-3582A/HI-3583A contain a 16-bit control register which is The HI-3582A/HI-3583A contain a 9-bit status register which can
used to configure the device. The control register bits CR0 - CR15 be interrogated to determine the status of the ARINC receivers,
are loaded from BD00 - BD15 when CWSTR is pulsed low. The data FIFOs and transmitter. The contents of the status register are
control register contents are output on the databus when SEL = 1 output on BD00 - BD08 when the RSR pin is taken low and
and RSR is pulsed low. Each bit of the control register has the SEL = 0. Unused bits are output as Zeros. The following table
following function: defines the status register bits.

CR SR
Bit FUNCTION STATE DESCRIPTION FUNCTION STATE DESCRIPTION
Bit

CR0 Receiver 1 0 Data rate = CLK/10 SR0 Data ready 0 Receiver 1 FIFO empty
Data clock (Receiver 1)
Select 1 Data rate = CLK/80 1 Receiver 1 FIFO contains valid data
Resets to zero when all data has
CR1 Label Memory 0 Normal operation been read. D/R1 pin is the inverse of
Read / Write this bit
1 Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2 SR1 FIFO half full 0 Receiver 1 FIFO holds less than 16
(Receiver 1) words
CR2 Enable Label 0 Disable label recognition
Recognition 1 Receiver 1 FIFO holds at least 16
(Receiver 1) 1 Enable label recognition words. HF1 pin is the inverse of
this bit.
CR3 Enable Label 0 Disable Label Recognition
Recognition SR2 FIFO full 0 Receiver 1 FIFO not full
(Receiver 2) 1 Enable Label recognition (Receiver 1)
1 Receiver 1 FIFO full. To avoid data
CR4 Enable 0 Transmitter 32nd bit is data loss, the FIFO must be read within
32nd bit one ARINC word period. FF1 pin is
as parity 1 Transmitter 32nd bit is parity the inverse of this bit

CR5 Self Test 0 The transmitter’s digital SR3 Data ready 0 Receiver 2 FIFO empty
outputs are internally connected (Receiver 2)
to the receiver logic inputs 1 Receiver 2 FIFO contains valid data
Resets to zero when all data has
1 Normal operation been read. D/R2 pin is the inverse of
this bit
CR6 Receiver 1 0 Receiver 1 decoder disabled
decoder SR4 FIFO half full 0 Receiver 2 FIFO holds less than 16
1 ARINC bits 9 and 10 must match (Receiver 2) words
CR7 and CR8
1 Receiver 2 FIFO holds at least 16
CR7 - - If receiver 1 decoder is enabled, words. HF2 pin is the inverse of
the ARINC bit 9 must match this bit this bit.

CR8 - - If receiver 1 decoder is enabled, SR5 FIFO full 0 Receiver 2 FIFO not full
the ARINC bit 10 must match this bit (Receiver 2)
1 Receiver 2 FIFO full. To avoid data
CR9 Receiver 2 0 Receiver 2 decoder disabled loss, the FIFO must be read within
Decoder one ARINC word period. FF2 pin is
1 ARINC bits 9 and 10 must match the inverse of this bit
CR10 and CR11
SR6 Transmitter FIFO 0 Transmitter FIFO not empty
CR10 - - If receiver 2 decoder is enabled, empty
the ARINC bit 9 must match this bit 1 Transmitter FIFO empty.

CR11 - - If receiver 2 decoder is enabled, SR7 Transmitter FIFO 0 Transmitter FIFO not full
the ARINC bit 10 must match this bit full
1 Transmitter FIFO full. FFT pin is the
CR12 Invert 0 Transmitter 32nd bit is Odd parity inverse of this bit.
Transmitter
parity 1 Transmitter 32nd bit is Even parity SR8 Transmitter FIFO 0 Transmitter FIFO contains less than
half full 16 words
CR13 Transmitter 0 Data rate=CLK/10, O/P slope=1.5us
data clock 1 Transmitter FIFO contains at least
select 1 Data rate=CLK/80, O/P slope=10us 16 words.HFT pin is the
inverse of this bit.
CR14 Receiver 2 0 Data rate=CLK/10
data clock
select 1 Data rate=CLK/80

CR15 Data 0 Scramble ARINC data

format
1 Unscramble ARINC data

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 HI-3582A, HI-3583A

FUNCTIONAL DESCRIPTION (cont.)

The HI-3582A/HI-3583A guarantee recognition of these levels with a
ARINC 429 DATA FORMAT common mode Voltage with respect to GND less than ±4V for the
worst case condition (3.0V supply and 13V signal level).
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3582A/ The tolerances in the design guarantee detection of the above
HI-3583A data bus during data read or write operations. The levels, so the actual acceptance ranges are slightly larger. If the
following table describes this mapping: ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
BYTE 1
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD RECEIVER LOGIC OPERATION
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

ARINC 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8 Figure 2 shows a block diagram of the logic section of each receiver.
Parity

BIT
Label

Label
Label

Label

Label
Label
Label

Label
SDI

SDI

CR15=0 BIT TIMING

ARINC 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 The ARINC 429 specification contains the following timing specifi-
BIT cation for the received data:
Label

Label
Label

Label

Label
Label
Label

Label
SDI

SDI

CR15=1
HIGH SPEED LOW SPEED
BYTE 2 BIT RATE 100K BPS ± 1% 12K -14.5K BPS
PULSE RISE TIME 1.5 ± 0.5 µsec 10 ± 5 µsec
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD PULSE FALL TIME 1.5 ± 0.5 µsec 10 ± 5 µsec
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PULSE WIDTH 5 µsec ± 5% 34.5 to 41.7 µsec
ARINC 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BIT
CR15=0 The HI-3582A/HI-3583A accept signals that meet these specifica-
tions and rejects signals outside the tolerances. The way the logic
ARINC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 operation achieves this is described below:
Parity

BIT
CR15=1 1. Key to the performance of the timing checking logic is an
accurate 1MHz clock source. Less than 0.1% error is recom-
mended.
THE RECEIVERS 2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ARINC BUS INTERFACE ered valid data. Additionally, for data bits, the One or Zero in
the upper bits of the sampling shift registers must be followed
Figure 1 shows the input circuit for each receiver. The ARINC 429 by a Null in the lower bits within the data bit time. For a Null in
specification requires the following detection levels: the word gap, three consecutive Nulls must be found in both
the upper and lower bits of the sampling shift register. In this
STATE DIFFERENTIAL VOLTAGE manner the minimum pulse width is guaranteed.
ONE +6.5 Volts to +13 Volts
NULL +2.5 Volts to -2.5 Volts 3. Each data bit must follow its predecessor by not less than
ZERO -6.5 Volts to -13 Volts 8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:

vDD DIFFERENTIAL COMPARATORS HIGH SPEED LOW SPEED

AMPLIFIERS

DATA BIT RATE MIN 83K BPS 10.4K BPS

RIN1A
ONES DATA BIT RATE MAX 125K BPS 15.6K BPS
OR
RIN2A

GND NULL
vDD 4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
RIN1B ZEROES valid reception. If the Null is present, the Word Gap counter
OR is incremented. A count of 3 will enable the next reception.
RIN2B

GND

FIGURE 1. ARINC RECEIVER INPUT

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 HI-3582A, HI-3583A

FUNCTIONAL DESCRIPTION (cont.)

RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO ARINC words which do not meet the necessary 9th and 10th
is used as a Parity Flag indicating whether good Odd parity is ARINC bit or label matching are ignored and are not loaded into
received from the incoming ARINC word. the receive FIFO. The following table describes this operation.
Odd Parity Received CR2(3) ARINC word CR6(9) ARINC word FIFO
The parity bit is reset to indicate correct parity was received matches bits 9,10
and the resulting word is then written to the receive FIFO. label match
CR7,8 (10,11)
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error 0 X 0 X Load FIFO
and the resulting word is then written to the receive FIFO.
1 No 0 X Ignore data
Therefore, the 32nd bit retrieved from the receiver FIFO will 1 Yes 0 X Load FIFO
always be “0” when valid (odd parity) ARINC 429 words are
received. 0 X 1 No Ignore data
RETRIEVING DATA 0 X 1 Yes Load FIFO

Once 32 valid bits are recognized, the receiver logic generates an 1 Yes 1 No Ignore data
End of Sequence (EOS). Depending upon the state of control 1 No 1 Yes Ignore data
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being 1 No 1 No Ignore data
loaded into the 32 x 32 receive FIFO. 1 Yes 1 Yes Load FIFO

TO PINS

SEL MUX CONTROL

32 TO 16 DRIVER R/W
CONTROL CONTROL BITS
EN

HF
FF

D/R
32 X 32
FIFO
LOAD FIFO
CONTROL

CONTROL
BIT / LABEL /
DECODE
COMPARE CONTROLBITS CLOCK
CLK
CR0, CR14 OPTION

CLOCK

16 x 8
LABEL BIT
MEMORY COUNTER
32ND AND
DATA PARITY BIT END OF
32 BIT SHIFT REGISTER CHECK SEQUENCE

BIT CLOCK

EOS

WORD GAP
WORD GAP TIMER
ONES SHIFT REGISTER
BIT CLOCK

START END
NULL SEQUENCE
SHIFT REGISTER CONTROL

ZEROS SHIFT REGISTER ERROR

ERROR
DETECTION CLOCK

FIGURE 2. RECEIVER BLOCK DIAGRAM

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 HI-3582A, HI-3583A

FUNCTIONAL DESCRIPTION (cont.)

Once a valid ARINC word is loaded into the FIFO, then EOS READING LABELS
clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both)
will go low. The data flag for a receiver will remain low until both After the write that changes CR1 from 0 to 1, the next 16 data
ARINC bytes from that receiver are retrieved and the FIFO is reads of the selected receiver (EN taken low) are labels. EN1 is
empty. This is accomplished by first activating EN with SEL, the used to read labels for receiver 1, and EN2 to read labels for
byte selector, low to retrieve the first byte and then activating EN receiver 2. Label data is presented on BD0-BD7.
with SEL high to retrieve the second byte. EN1 retrieves data
from receiver 1 and EN2 retrieves data from receiver 2. When writing to, or reading from the label memory, SEL must be a
one, all 16 locations should be accessed, and CR1 must be
Up to 32 ARINC words may be loaded into each receiver’s FIFO. written to zero before returning to normal operation. Label
The FF1 (FF2) pin will go low when the receiver 1 (2) FIFO is full. recognition must be disabled (CR2/3=0) during the label read
Failure to retrieve data from a full FIFO will cause the next valid sequence.
ARINC word received to overwrite the existing data in FIFO
location 32. A FIFO half full flag HF1 (HF2) goes low if the FIFO
contains 16 or more received ARINC words. The HF1 (HF2) pin is TRANSMITTER
intended to act as an interrupt flag to the system’s external
microprocessor, allowing a 16 word data retrieval routine to be FIFO OPERATION
performed, without the user needing to continually poll the
HI-3582A/HI-3583A status register bits. The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word (or 32 bit word if CR4=0) in the next available
LABEL RECOGNITION position of the FIFO. If TX/R, the transmitter ready flag is high
(FIFO empty), then up to 32 words, each 31 or 32 bits long, may
The chip compares the incoming label to the stored labels if label be loaded. If TX/R is low, then only the available positions may be
recognition is enabled. If a match is found, the data is processed. loaded. If all 32 positions are full, the FFT flag is asserted and the
If a match is not found, no indicators of receiving ARINC data are FIFO ignores further attempts to load data.
presented. Note that 00(Hex) is treated in the same way as any
other label value. Label bit significance is not changed by the A transmitter FIFO half-full flag HFT is provided. When the
status of control register bit CR15. Label bits BD00 - BD07 are transmit FIFO contains less than 16 words, HFT is high,
always compared to received ARINC bits 1 - 8 respectively. indicating to the system microprocessor that a 16 ARINC word
block write sequence can be initiated.
LOADING LABELS
In normal operation (CR4=1), the 32nd bit transmitted is a parity
After a write that takes CR1 from 0 to 1, the next 16 writes of bit. Odd or even parity is selected by programming control
data (PL pulsed low) load label data into each location of the register bit CR12 to a zero or one. If Cr4 is programmed to a 0,
label memory from the BD00 - BD07 pins. The PL1 pin is used to then all 32-bits of data loaded into the transmitter FIFO are
write label data for receiver 1 and PL2 for receiver 2. Note that treated as data and are transmitted.
ARINC word reception is suspended during the label memory
write sequence.
CR4,12

BIT CLOCK DATA AND TXAOUT

32 BIT PARALLEL PARITY NULL TIMER LINE DRIVER
LOAD SHIFT REGISTER GENERATOR SEQUENCER TXBOUT

TEST

BIT
AND
WORD CLOCK WORD GAP
COUNTER

START
SEQUENCE
32 x 32 FIFO ADDRESS TX/R
WORD COUNTER HFT
AND
LOAD FIFO CONTROL FFT
ENTX
INCREMENT
WORD COUNT

FIFO PL1
LOADING
SEQUENCER PL2
DATA BUS

DATA
CLOCK DATA CLOCK CLK
CR13 DIVIDER TX CLK

FIGURE 3. TRANSMITTER BLOCK DIAGRAM

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 HI-3582A, HI-3583A

FUNCTIONAL DESCRIPTION (cont.)

DATA TRANSMISSION

When ENTX goes high, enabling transmission, the FIFO The HI-3582A has 37.5 ohms in series with each line driver output.
positions are incremented with the top register loading into the The HI-3583A has 10 ohms in series. The HI-3583A is for
data transmission shift register. Within 2.5 data clocks the first applications where external series resistance is needed, typically
data bit appears at TXAOUT and TXBOUT. The 31 or 32 bits in for lightning protection devices.
the data transmission shift register are presented sequentially to
the outputs in the ARINC 429 format with the following timing: REPEATER OPERATION

Repeater mode of operation allows a data word that has been

HIGH SPEED LOW SPEED received by the HI-3582A/HI-3583A to be placed directly into the
ARINC DATA BIT TIME 10 Clocks 80 Clocks transmitter FIFO. Repeater operation is similar to normal receiver
DATA BIT TIME 5 Clocks 40 Clocks operation. In normal operation, either byte of a received data word
NULL BIT TIME 5 Clocks 40 Clocks may be read from the receiver latches first by use of SEL input.
WORD GAP TIME 40 Clocks 320 Clocks During repeater operation however, the lower byte of the data word
must be read first. This is necessary because, as the data is being
The word counter detects when all loaded positions have been read, it is also being loaded into transmitter FIFO which is always
transmitted and sets the transmitter ready flag, TX/R, high. loaded with the lower byte of the data word first. Signal flow for
repeater operation is shown in the Timing Diagrams section.
TRANSMITTER PARITY
HI-3582A-15 and HI-3583A-15
The parity generator counts the Ones in the 31-bit word. If
control register bit CR12 is set low, the 32nd bit transmitted will The HI-3582A-15/HI-3583A-15 options are similar to the HI-3582A/
make parity odd. If the control bit is high, the parity is even. HI-3583A with the exception that they allow an external 15 Kohm
Setting CR4 to a Zero bypasses the parity generator, and allows resistor to be added in series with each ARINC input without affect-
32 bits of data to be transmitted. ing the ARINC input thresholds. This option is especially useful in
applications where lightning protection circuitry is also required.
SELF TEST
Each side of the ARINC bus must be connected through a
If control register bit CR5 is set low, the transmitter serial output 15 Kohm series resistor in order for the chip to detect the correct
data are internally connected to each of the two receivers, ARINC levels. The typical 10 volt differential signal is translated
bypassing the analog interface circuitry. Data is passed and input to a window comparator and latch. The comparator lev-
unmodified to receiver 1 and inverted to receiver 2. Taking TEST els are set so that with the external 15 Kohm resistors, they are
high forces TXAOUT and TXBOUT into the null state regardless just below the standard 6.5 volt minimum ARINC data threshold
of the state of CR5. and just above the standard 2.5 volt maximum ARINC null thresh-
old.
SYSTEM OPERATION
Please refer to the Holt AN-300 Application Note for additional
The two receivers are independent of the transmitter. information and recommendations on lightning protection of Holt
Therefore, control of data exchanges is strictly at the option of line drivers and line receivers.
the user. The only restrictions are:
HIGH SPEED OPERATION
1. The received data will be overwritten if the receiver FIFO
is full and at least one location is not retrieved before the next The HI-3582A and HI-3583A may be operated at clock frequencies
complete ARINC word is received. beyond that required for ARINC compliant operation. For operation
at Master Clock (CLK) frequencies up to 5MHz, please contact
2. The transmitter FIFO can store 32 words maximum and Holt applications engineering.
ignores attempts to load additional data if full.
MASTER RESET (MR)
LINE DRIVER OPERATION
On a Master Reset data transmission and reception are immedi-
The line driver in the HI-3582A/HI-3583A are designed to directly ately terminated, all three FIFOs are cleared as are the FIFO flags
drive the ARINC 429 bus. The two ARINC outputs (TXAOUT at the device pins and in the Status Register. The Control
and TXBOUT) provide a differential voltage to produce a +10 volt Register is not affected by a Master Reset.
One, a -10 volt Zero, and a 0 volt Null. Control register bit CR13
controls both the transmitter data rate, and the slope of the
differential output signal. No additional hardware is required to
control the slope. Programming CR13 to Zero causes a
100 kbits/s data rate and a slope of 1.5 µs on the ARINC outputs;
a One on CR13 causes a 12.5 kbit/s data rate and a slope of
10 µs. Timing is set by on-chip resistor and capacitor and tested
to be within ARINC requirements.

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 HI-3582A, HI-3583A

TIMING DIAGRAMS
DATA RATE - EXAMPLE PATTERN

TXAOUT

ARINC BIT

TXBOUT

DATA NULL DATA NULL DATA NULL

BIT 1
BIT 31 BIT 32 WORD GAP
BIT 30 NEXT WORD

RECEIVER OPERATION

ARINC DATA BIT 31 BIT 32

D/R, HF, FF
tD/R tEND/R

SEL DON'T CARE

tEN
tSELEN tENSEL tSELEN tENSEL tSELEN
EN
tD/REN tENEN tREADEN

CLK
tCLKEN tCLKEN
tDATAEN tDATAEN
DATA BUS BYTE 1 VALID BYTE 2 VALID BYTE 1

tENDATA tENDATA tENDATA

TRANSMITTER OPERATION

DATA BUS BYTE 1 VALID BYTE 2 VALID

tDWSET tDWSET
tDWHLD tDWHLD
PL1

tPL tPL12
tPLCYC
PL2

tPL12 tPL tTX/R

TX/R, FFT

tHFT
HFT

LOADING CONTROL WORD

DATA BUS VALID

tCWSET tCWHLD

CWSTR

tCWSTR

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 HI-3582A, HI-3583A

TIMING DIAGRAMS (cont.)

STATUS REGISTER READ CYCLE

BYTE SELECT SEL DON'T CARE DON'T CARE

tSELEN tENSEL
RSR

tDATAEN
DATA BUS DATA VALID

tENDATA

CONTROL REGISTER READ CYCLE

BYTE SELECT SEL DON'T CARE DON'T CARE

tSELEN tENSEL
RSR

tDATAEN
DATA BUS DATA VALID

tENDATA

LABEL MEMORY LOAD SEQUENCE

tCWSTR

CWSTR

tCWHLD
tCWSET

DATA BUS Set CR1=1 Label #1 Label #2 Label #16 Set CR1=0

tDWSET
tDWHLD
PL1 or PL2
tPL tLABEL

LABEL MEMORY READ SEQUENCE

tCWSTR

CWSTR

tREADEN

EN1 or EN2
tCWHLD
tDATAEN
tCWSET

DATA BUS Set CR1=1 Label #1 Label #2 Label #16 Set CR1=0

tENDATA

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 HI-3582A, HI-3583A

TIMING DIAGRAMS (cont.)

TRANSMITTING DATA
PL2
tDTX/R
tPL2EN
TXR
tENTX/R

ENTX
ARINC BIT ARINC BIT ARINC BIT
tENDAT DATA
DATA
BIT 1 BIT 2 DATA
BIT 32

+5V +5V

TXAOUT

-5V

+5V

TXBOUT

-5V -5V

tfx
+10V +10V
V 90%
DIFF
(TXAOUT) - TXBOUT)
tfx trx
10%

trx 10%

one level zero level 90% null level

-10V

REPEATER OPERATION TIMING

RIN BIT 32

tEND/R
D/R

tD/R tD/REN tEN tENEN tEN

EN

tSELEN tENSEL

SEL DON'T CARE DON'T CARE

tSELEN
tENPL tPLEN tENSEL
PL1

tENPL tPLEN
PL2

tTX/R
TXR

tTX/REN tENTX/R

ENTX
tENDAT tDTX/R
TXAOUT BIT 1 BIT 32
TXBOUT
tNULL

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 HI-3582A, HI-3583A

ABSOLUTE MAXIMUM RATINGS

Supply Voltages VDD ......................................... -0.3V to +4.0V Power Dissipation at 25°C

V+ ......................................................... +11.0V Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C
V- ......................................................... -11.0V Ceramic J-LEAD CERQUAD ...... 1.0 W, derate 7mW/°C

Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B .. -120V to +120V DC Current Drain per pin .............................................. ±10mA

Voltage at any other pin ............................... -0.3V to VDD +0.3V Storage Temperature Range ........................ -65°C to +150°C

Solder temperature (Reflow) ............................................ 260°C Operating Temperature Range (Industrial): .... -40°C to +85°C
(Extended): ....-55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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 HI-3582A, HI-3583A

DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V , V+ = 10V, V- = -10V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).

LIMITS
PARAMETER SYMBOL CONDITIONS UNIT
MIN TYP MAX

ARINC INPUTS - Pins RIN1A, RIN1B, RIN2A, RIN2B

Differential Input Voltage: ONE VIH Common mode voltages 6.5 10.0 13.0 V
(RIN1A to RIN1B, RIN2A to RIN2B) ZERO VIL less than ±4V with -13.0 -10.0 -6.5 V
NULL VNUL respect to GND -2.5 0 2.5 V

Input Resistance: Differential RI 12 80 KW

To GND RG 12 45 KW
To VDD RH 12 40 KW

Input Current: Input Sink IIH 200 µA

Input Source IIL -450 µA

Input Capacitance: Differential CI (RIN1A to RIN1B, RIN2A to RIN2B) 20 pF

(Guaranteed but not tested) To GND CG 20 pF
To VDD CH 20 pF

BI-DIRECTIONAL INPUTS - Pins BD00 - BD15

Input Voltage: Input Voltage HI VIH 70% VDD V

Input Voltage LO VIL 30% VDD V

Input Current: Input Sink IIH 1.5 µA

Input Source IIL -1.5 µA

OTHER INPUTS

Input Voltage: Input Voltage HI VIH 70% VDD V

Input Voltage LO VIL 30% VDD V

Input Current: Input Sink IIH 1.5 µA

Input Source IIL -1.5 µA
Pull-down Current (TEST Pin) IPD 330 µA
Pull-up Current (RSR Pin) IPU -330 µA
ARINC OUTPUTS - Pins TXAOUT, TXBOUT

ARINC output voltage (Ref. To GND) One or zero VDOUT No load and magnitude at pin, 4.50 5.00 5.50 V
Null VNOUT VDD = 3.3 V -0.25 0.25 V

ARINC output voltage (Differential) One or zero VDDIF No load and magnitude at pin, 9.0 10.0 11.0 V
Null VNDIF VDD = 3.3 V -0.5 0.5 V

ARINC output current IOUT 80 mA

OTHER OUTPUTS

Output Voltage: Logic "1" Output Voltage VOH IOH = -100µA VDD - 0.2V V
Logic "0" Output Voltage VOL IOL = 1.0mA 10% VDD V

Output Current: Output Sink IOL VOUT = 0.4V 1.6 mA

(All Outputs & Bi-directional Pins) Output Source IOH VOUT = VDD - 0.4V -1.0 mA

Output Capacitance: CO 15 pF

Operating Voltage Range

VDD 3.15 3.45 V

V+ 9.5 10.5 V

V- -9.5 -10.5 V

Operating Supply Current

VDD IDD1 3.5 7 mA

V+ IDD2 7.5 10 mA

V- IEE1 5.5 10 mA

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 HI-3582A, HI-3583A

AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, V+=10V, V-=-10V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz +0.1% with 60/40 duty cycle

LIMITS
PARAMETER SYMBOL UNITS
MIN TYP MAX
CONTROL WORD TIMING
Pulse Width - CWSTR tCWSTR 25 ns
Setup - DATA BUS Valid to CWSTR HIGH tCWSET 25 ns
Hold - CWSTR HIGH to DATA BUS Hi-Z tCWHLD 5 ns
RECEIVER FIFO AND LABEL READ TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed tD/R 16 µs
Low Speed tD/R 128 µs
Delay - D/R LOW to EN LOW tD/REN 0 ns
Delay - EN HIGH to D/R HIGH tEND/R 25 ns
Setup - SEL to EN LOW tSELEN 0 ns
Hold - SEL to EN HIGH tENSEL 10 ns
Delay - EN LOW to DATA BUS Valid tENDATA 50 ns
Delay - EN HIGH to DATA BUS Hi-Z tDATAEN 20 ns

Pulse Width - EN1 or EN2 tEN 50 ns

Spacing - EN HIGH to next EN LOW (Same ARINC Word) tENEN 70 ns
Spacing -EN HIGH to next EN LOW (Next ARINC Word) tREADEN 70 ns
CLK HIGH separation from second EN pulse HIGH (SEL is HIGH) tCLKEN 25 ns
TRANSMITTER FIFO AND LABEL WRITE TIMING
Pulse Width - PL1 or PL2 tPL 30 ns
Setup - DATA BUS Valid to PL HIGH tDWSET 30 ns
Hold - PL HIGH to DATA BUS Hi-Z tDWHLD 10 ns

Spacing - PL1 or PL2 tPL12 40 ns

Spacing - PL1 rising to PL2 rising tPLCYC tCLK-10 ns
Spacing between Label Write pulses tLABEL 40 ns
Delay - PL2 HIGH to TX/R LOW tTX/R 30 ns
Delay - PL2 HIGH to HFT low tHFT 25 ns
TRANSMISSION TIMING

Spacing - PL2 HIGH to ENTX HIGH tPL2EN 0 ns

Delay - 32nd ARINC Bit to TX/R HIGH tDTX/R 50 ns
Spacing - TX/R HIGH to ENTX LOW tENTX/R 0 ns

LINE DRIVER OUTPUT TIMING

Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed tENDAT 25 µs

Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed tENDAT 200 µs
Line driver transition differential times:
(High Speed, control register CR13 = Logic 0) high to low tfx 1.0 1.5 2.0 µs
low to high trx 1.0 1.5 2.0 µs
(Low Speed, control register CR13 = Logic 1) high to low tfx 5.0 10 15 µs
low to high trx 5.0 10 15 µs

REPEATER OPERATION TIMING

Delay - EN LOW to PL LOW tENPL 0 ns

Hold - PL HIGH to EN HIGH tPLEN 0 ns

Delay - TX/R LOW to ENTX HIGH tTX/REN 0 ns

MASTER RESET PULSE WIDTH tMR 175 ns

ARINC DATA RATE AND BIT TIMING ± 1%

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 HI-3582A, HI-3583A

ADDITIONAL HI-3582A / HI-3583A PIN CONFIGURATIONS

50 - TXCLK
3 - RIN1A
4 - RIN1B
5 - RIN2A
6 - RIN2B

52 - TEST
7 - D/R1

48 - RSR
2 - VDD

49 - CLK

47 - N/C
1 - N/C

51 - MR
FF1 - 8 46 - N/C
HF1 - 9 45 - CWSTR
D/R2 - 10 HI-3582ACJI 44 - ENTX
FF2 - 11 43 - V+
HF2 - 12
HI-3582ACJT 42 - TXBOUT
SEL - 13 HI-3582ACJM 41 - TXAOUT
EN1 - 14 & 40 - V-
EN2 -15 HI-3583ACJI 39 - FFT
BD15 - 16 38 - HFT
BD14 - 17 HI-3583ACJT 37 - TX/R
BD13 - 18 HI-3583ACJM 36 - PL2
BD12 - 19 35 - PL1
BD11 - 20 34 - BD00

BD01 - 33
BD02 - 32
BD03 - 31
BD04 - 30
BD05 - 29
N/C - 28
GND - 27
N/C - 26
BD06 - 25
BD07 - 24
BD08 - 23
BD09 - 22
BD10 - 21

52 - Pin Cerquad J-Lead

(See page 1 for additional pin configuration)

ORDERING INFORMATION
HI - 358xA xx x x - xx
PART INPUT SERIES RESISTANCE
NUMBER BUILT-IN REQUIRED EXTERNALLY
No dash number 35K Ohm 0
-15 20K Ohm 15K Ohm

PART PACKAGE
NUMBER DESCRIPTION
Blank Tin / Lead (Sn / Pb) Solder
F 100% Matte Tin (Pb-free RoHS compliant)

PART TEMPERATURE BURN

NUMBER RANGE FLOW IN
I -40°C TO +85°C I No
T -55°C TO +125°C T No
M -55°C TO +125°C M Yes

PART PACKAGE
NUMBER DESCRIPTION
CJ 52 PIN J-LEAD CERQUAD (52U) not available Pb-free
PC 64 PIN PLASTIC CHIP-SCALE LPCC (64PCS)
PQ 52 PIN PLASTIC QUAD FLAT PACK PQFP (52PTQS)

PART OUTPUT SERIES RESISTANCE

NUMBER BUILT-IN REQUIRED EXTERNALLY
3582A 37.5 Ohms 0
3583A 10 Ohms 27.5 Ohms

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 HI-3582A, HI-3583A

REVISION HISTORY

P/N Rev Date Description of Change

DS3582A NEW 02/12/09 New document
A 04/27/10 Added CLKEN to timing parameters
B 06/29/10 Added PLCYC to timing parameters
C 07/25/13 Updated Receiver Parity function, QFN and PQFP package drawings, timing parameter
tSELEN and solder temperature parameters. Remove note on heat sink connection for QFN
package. Update Voltage at ARINC input pins from +/-115V to +/-120V

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 HI-3582A / HI-3583A PACKAGE DIMENSIONS

52-PIN J-LEAD CERQUAD inches (millimeters)

Package Type: 52U

7 1 52 47

.788 max .720 ±.010

(20.0) SQ. (18.29 ±.25)

.750 ±.007
(19.05 ±.18)
.190 max
.040 ± .005 (4.826)
(1.02 ± .013)
.019 ±.002 .050 BSC BSC = “Basic Spacing between Centers”
(.483 ±.051) (1.27) is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)

52-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters)

Package Type: 52PQS

.0256
BSC
(.65)
.520 .394
BSC SQ BSC SQ
(13.2) (10.0) .012 ± .004
(.310 ± .09)

.035 ± .006
(.88 ± .15)
.063
typ
(1.6)
.008
min
(.20)
See Detail A
.005
.106
MAX. (.13) R min
(2.7) .079 ± .008
(2.0 ± .20)
0° £ Q £ 7°
.005
R min
(.13)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and DETAIL A
has no tolerance. (JEDEC Standard 95)

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 HI-3582A / HI-3583A PACKAGE DIMENSIONS

64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) inches (millimeters)

Package Type: 64PCS
Electrically isolated heat
sink pad on bottom of
package.
Connect to any ground or
power plane for optimum
.354 thermal dissipation.
BSC .268 ± .039
(9.00)
(6.80 ± .05)

.0197
BSC
(0.50)

.354 .268 ± .039

(9.00)
BSC Top View Bottom .010
(6.80 ± .05) typ
View (0.25)

.016 ± .002
(0.40 ± .05)
.008
typ
(0.20)
BSC = “Basic Spacing between Centers”
.039 is theoretical true position dimension and
max
(1.00) has no tolerance. (JEDEC Standard 95)

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