INTERNATIONAL JOURNAL

OF PROFESSIONAL ENGINEERING STUDIES Volume V /Issue 3 /AUG 2015

Analysis of New Three-Phase 9-level Multilevel

Inverter with Reduced Number of Power Electronic
Components
A. Dileshwar Rao P. Praveen Kumar
PG Scholar Assistant Professor
Gokaraju RangaRaju Institute of Engineering Gokaraju RangaRaju Institute of Engineering and
and Technology Technology
JNTU Hyderabad, Telangana, India JNTU Hyderabad, Telangana, India

Abstract—In this paper, a new configuration of a three- topologies are becoming one of the most interested
phase nine-level multilevel voltage-source inverter is research area. In the asymmetrical configurations ,the
introduced. A multilevel dc link using fixed dc voltage magnitudes of dc voltage supplies are unequal. These
supply and cascaded half-bridge is connected in such a topologies reduce the cost and size of the inverter and
way that the proposed inverter outputs the required improve the reliability since minimum number of
output voltage levels. The fundamental frequency power electronic components, capacitors, and dc
staircase modulation technique is easily used to supplies are used. The hybrid multistage converters
generate the appropriate switching gate signals. For the consists of different multilevel configurations with
purpose of increasing the number of voltage levels with unequal dc voltage supplies. With such converters,
fewer number of power electronic components, the different modulation strategies and power electronic
structure of the proposed inverter is extended and components technologies are needed [18]–[26]. On
different methods to determine the magnitudes of the other hand, for the purpose of improving the
utilized dc voltage supplies are suggested. Moreover, the performance of the conventional single- and three-
prototype of the suggested configuration is
phase inverters, different topologies employing
manufactured as the obtained simulation and hardware
different types of bidirectional switches have been
suggested in [27]–[29]. Comparing to the
results ensured the feasibility of the configuration and
unidirectional one, bidirectional switch is able to
the compatibility of the modulation technique is
conduct the current and withstanding the voltage in
accurately noted.
both directions. Bidirectional switches with an
appropriate control technique can improve the
Index Terms— Bidirectional switch, fundamental performance of multilevel inverters in terms of
frequency staircase modulation, multilevel inverter. reducing the number of semiconductor components,
I.INTRODUCTION minimizing the withstanding voltage and achieving
Multilevel inverters consist of a group of the desired output voltage with higher levels [30]–
switching devices and dc voltage supplies, the output [34]. Based on this technical background, this paper
of which produces voltages with stepped waveforms. suggests a novel topology for a three phase nine-level
Multilevel technology has started with the three-level multilevel inverter. The number of switching devices,
converter followed by numerous multilevel converter insulated-gate driver circuits, and installation area
topologies. Different topologies and wide variety of and cost are significantly reduced. The magnitudes of
control methods have been developed in the recent the utilized dc voltage supplies have been selected in
literature [1]–[3]. The most common multilevel a way that brings the high number of voltage level
inverter configurations are neutral point clamped with an effective application of a fundamental
(NPC), the flying capacitor (FC), and the cascaded frequency staircase modulation technique. Extended
H-bridge (CHB). The deviating voltage of neutral- structure for N-level is also presented and compared
point voltage in NPC, the unbalanced voltage in the with the conventional well-known multilevel
dc link of FC, and the large number of separated dc inverters. Simulation and hardware results are given
supplies in CHB are considered the main drawbacks and explained.
of these topologies [4], [5]. Apart from these three
main topologies, other topologies are introduced [6]–
[17]. Recently, asymmetrical and hybrid multistage

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peak voltage rating of 3Vdc. In CHB cells, the peak

voltage rating of second cell switches (T3 and T4) is
2Vdcwhile the peak voltage rating of T1 and T2 in the
first cell is Vdc. By considering phase a, the operating
status of the switches and the inverter line-to-ground
II. PROPOSED TOPOLOGY voltage Vag are given in Table I.
Fig. 1shows the typical configuration of the
proposed three-phase nine-level multilevel inverter.
Three bidirectional switches (S1–S6, Da1–Dc2), two TABLE I
switches–two diodes type, are added to the Switching State Sa and Inverter Line-to-Ground Voltage Vag
conventional three-phase two-level
Q1 S1 S2 Q2 T1 T2 T3 T4
4 on off off Off on off on off +4
3 off on on Off on off on off +3
2 off on on Off off on on off +
1 off on on Off on off off on +
0 off off off On on off off on 0

It is easier to define the inverter line-to-ground

voltages Vag, Vbg, and Vcgi n terms of switching states
Sa, Sb, and Scas

= * (1)

Fig. 1. Circuit diagram of the proposed three-phase 9-level Where N = 5 is the maximum number of voltage
multilevel inverter levels. The balanced load voltages can be achieved if
the proposed inverter operates on the switching states
bridge(Q1–Q6). The function of these bidirectional depicted in Table II. The inverter may have 24
switches is to block the higher voltage and ease different modes within a cycle ofthe output
current flow to and from the midpoint (o). A waveform. According to Table II, it can be noticed
multilevel dc link built by a single dc voltage supply that the bidirectional switches operate in 18 modes.
with fixed magnitude of 4Vdc and CHB having four For each mode, there is no more than one
dc voltage supplies of Vdc, Vdc and 2Vdc, 2Vdcare bidirectional switch in on state. As a result, the load
connected to (+, –, o)bridge terminals. Based on the current commutates over one switch and one diode
desired number of output voltage levels, a number of (for instance: in (410), the load current Ib can flow in
CHB cells are used. Since the proposed inverter is S3 and Db1 or S4 and Db2). Since some insulated
designed to achieve nine voltage levels, the power gate bipolar transistors (IGBTs) share the same
circuit of the CHB makes use of four series cells switching gate signals, the proposed configuration
having two unequal dc voltage supplies. In each cell, significantly contributed in reducing the utilized gate
the two switches are turned ON and OFF under driver circuits and system complexity. The inverter
inverted conditions to output different voltage levels. line-to-line voltage waveforms Vab, Vbc, and Vca with
The first cell dc voltage supply Vdc is added if switch corresponding switching gate signals are depicted in
T1 is turned ON leading to Vmg= +Vdc where Vmg is Fig. 2where Vab ,Vbc, and Vca are related to Vag, Vbg,
the voltage at node (m) with respect to inverter and Vcgby
ground(g) or bypassed if switch T2 is turned ON
leading to Vmg=0. Likewise, the second cell dc 1 −1 0
voltage supply 2Vdc is added when switch T3 is = 0 1 −1 * (2)
turned ON resulting in Vom=+2Vdc where Vom is the −1 0 1
voltage at midpoint (o) with respect to node (m) or
bypassed when switch T4 is turned ON resulting in The inverter line-to-neutral voltages VaN, VbN, and
Vom= 0.The peak voltage rating of the switches of the VcN maybe expressed as
conventional two level bridge (Q1–Q6) is 4Vdc
whereas the bidirectional switches(S1–S6) have a

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2 −1 −1 It is worth noting that all simulated waveforms are

= −1 2 −1 * (3) obtained at t1=t2 = · · · = t24 = 0.02/24 s.
, + + ≤5
−1 −1 2
= 2 , + + =6 (5)
It is useful to recognize that the inverter voltages at 3 , + + ≥7
terminals a,b, and c with respect to the midpoint (o)
are given by
The simulated voltage waveforms of Vag , Vog ,Vao
and VaN based on (1)–(5) are shown in Fig. 3 where,
for instance, 13sequent voltage steps are seen in VaN
= − (4)
waveform as follows:

Where Vog is the voltage at midpoint (o) with respect

to ground(g). Vog routinely fluctuates among three
different voltage values Vdc, 2Vdc, and 3Vdc as
follows: +8Vdc/3, +7Vdc/3, +6Vdc/3, +5Vdc/3, +4Vdc/3,
+2Vdc/3, 0, –2Vdc/3, −4Vdc/3, –5Vdc/3, –
6Vdc/3,−7Vdc/3, and –8Vdc/3.

TABLE II
SWITCHING STATES SEQUENCE OF THE PROPOSED INVERTER WITHIN O NE CYCLE

Period ON switches ON switches ON switches ON switches

T[s] Leg a Leg b Leg c Cascaded
half-bridge
400 t1 Q1 Q4 Q6 T1, T4 4 0 0
410 t2 Q1 S3, S4 Q6 T1, T4 4 0
420 t3 Q1 S3, S4 Q6 T2, T3 4 2 0
430 t4 Q1 S3, S4 Q6 T1, T3 4 3 0
440 t5 Q1 Q3 Q6 T1, T3 4 4 0
340 t6 S1,S2 Q3 Q6 T1, T3 3 4 0
240 t7 S1,S2 Q3 Q6 T2, T3 2 4 0
140 t8 S1,S2 Q3 Q6 T1, T4 4 0
040 t9 Q2 Q3 Q6 T1, T4 0 4 0
041 t10 Q2 Q3 S5, S6 T1, T4 0 4 0
042 t11 Q2 Q3 S5, S6 T2, T3 0 4
043 t12 Q2 Q3 S5, S6 T1, T3 0 4 2
044 t13 Q2 Q3 Q5 T1, T3 0 4 3
034 t14 Q2 S3, S4 Q5 T1, T3 0 3 4
024 t15 Q2 S3, S4 Q5 T2, T3 0 2 4
014 t16 Q2 S3, S4 Q5 T1, T4 0 4
004 t17 Q2 Q4 Q5 T1, T4 0 0 4
104 t18 S1,S2 Q4 Q5 T1, T4 0 4
204 t19 S1,S2 Q4 Q5 T2, T3 2 0 4
304 t20 S1,S2 Q4 Q5 T1, T3 3 0 4
404 t21 Q1 Q4 Q5 T1, T3 4 0 4
403 t22 Q1 Q4 S5, S6 T1, T3 4 0 3
402 t23 Q1 Q4 S5, S6 T2, T3 4 0 2
401 t24 Q1 Q4 S5, S6 T1, T4 4 0

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the undesirable harmonic components from the

output waveforms. Alternative method such as the
Newton–Raphson method is normally used to find
the solutions to (N–1) nonlinear transcendental
equations. The difficult calculations and the need of
high performance controller for the real application
are the main disadvantages of such method.
Therefore, an alternative method is proposed to
generate the inverter’s switching gate signals. It is
easier to control the proposed inverter and achieve
the required output voltage waveforms in terms of Sa,
Sb, and Sc. The basis of the proposed method can be
explained as following: For a given value of
Fig. 2. Simulated waveforms of Vab,Vbc, and Vca with modulation index Ma and within a full cycle of
corresponding switching gate signals for the proposed inverter at
fundamental frequency f = 50 Hz.

In order to plot the space vector diagram of the

proposed inverter in a stationary d–q reference frame,
the following equations can be used to derive d and q
voltage components for all inverter vectors:

Fig. 4.Switching states vectors of the proposed inverter in d–q

reference frame.

the operation of the proposed inverter, the switching

states Sa, Sb, and Scare determined instantaneously.
The on-time calculations of Sa, Sb, and Sc directly
Fig. 3. Simulated waveforms of Vag, Vog, Vao and VaNfor the
proposed inverter f = 50 Hz.
depend on the instantaneous values of the inverter
line-to-ground voltages. It is well known that the
reference values of Vag, Vbg, and Vcg are normally
= (2 − − ) (6) given by
( )

cos ( )
= ( − ) (7) _ 1
√ ( ) ∗
_ = ∗ cos ( − ) + ∗ 1 (9)
_ cos ( + ) 1
V= − (8)

For all switching states presented in Table II, Fig. 4 Where wt is the electrical angle. Or
shows the space vector diagram for the proposed
topology. cos ( )
_
∗
III. SWITCHING ALGORITHM _ = ∗ cos ( − ) + ∗
The staircase modulation can be simply _ cos ( + )
implemented for the proposed inverter. Staircase 1
modulation with selective harmonic is the most 1− cos (3 ) ∗ 1 (10)
common modulation technique used to control the 1
fundamental output voltage as well as to eliminate

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From (10), it can be noticed that the third harmonic Using (9)–(11) and substituting N = 3, the inverter’s
component is added to the three-line-to-ground operating switching states Sa, Sb, and Scat Ma <0.9
voltages. The third harmonic injection may increase can be defined. The operation principle of the
the inverter fundamental voltage without causing proposed inverter at Ma <0.9 is illustrated in Table
over modulation. As a result, Ma can reach to 1.15 III. Fig. 6(a) and (b) shows the inverter line-to-line
and Sa, Sb, and Sc can be simply determined by voltage waveforms at nine different modulation
integrating the reference line-to-ground voltages as indices including the over modulation operation Ma =
0.8,0.9, 1.05, 1.15, and 1.3.
_
= ∗ _ (11) IV. EXTENDED STRUCTURE
_ It is noticeable that there is possibility to
reach an output voltage with higher number of steps
Comparison of the proposed modulation method with in the proposed multilevel inverter by extending the
the staircase modulation with the selective harmonic CHB circuit. Such extending can be done by adding
method shows that the proposed modulation features more half-bridge cells connected in series as shown
less time and needs simple calculations. The in Fig. 7(a) and (b). In order to achieve the desired
inverter’s operating switching states Sa, Sb, and number of voltage levels, three methods can be
Scand corresponding switching gate signals based on followed to determine the magnitudes of utilized dc
the proposed modulation method are shown in Fig. 5. voltage supplies.
It is clear 1) All cells have an equal dc supply in magnitude.

= =…= = (12)

Then, the magnitude of fixed dc supply can be

chosen as

= ( − 1) = (1 + ) (13)

Where n is the number of utilized cells. The

maximum number of voltage steps is related to the
number of utilized cells by

N=n+2 (14)

Fig. 5. Inverter’s operating switching states Sa, Sb, and Sc with The number of operation modes that makes the
corresponding switching gate signals based on the proposed switching states sequence achieves the required
modulation method.
output voltage waveform
TABLE III
SWITCHING STATE Sa1 AND INVERTER LINE-TO-G ROUND M=6(N-1) (15)
VOLTAGE Vag

AT Ma <0.9 (LEG a)

Sa1 Q1 S1 S2 Q2 T1 T2 T3 T4
2 On Off Off Off Off On On Off +4Vdc
1 Off On On Off Off On On Off +2Vdc
0 off off off on Off On On Off 0

that the switching gate signals are generated within

24 different modes starting from (044) to (034).Since
the proposed inverter has been designed to achieve
nine voltage levels, the modulation index must be Fig. 6. Simulated waveforms of Va bat different modulation indices
within range0.9 ≤ Ma ≤ 1.15. For modulation index for the proposed inverter: (a) Ma = 0.9, 1.05, and 1.15 and (b) Ma =
Ma <0.9, only two dc voltage supplies 4Vdc and 2Vdc 0.8 and 1.3. can be expressed as
are utilized and the behavior of the proposed inverter
becomes similar to the three-level multilevel inverter.

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2) The magnitude of dc voltage supply used in each TABLE IV

COMPARISON OF THE MAXIMUM NUMBER OF VOLTAGE
and every cell in a particular inverter is obtained as
LEVELSWITH THE REQUIRED VALUE OF DC VOLTAGE
follows: SUPPLIES AMONGTHE PROPOSED METHODS

= (16) Number 1st Method 2nd Method 3rd Method

of cells
n N M N M N M
=2 (17) 2 4 18 3 5 24 4 5 24 4
3 5 24 4 8 42 7 9 48 8
= (18) 4 6 30 5 12 66 11 17 96 16
5 7 36 6 17 96 16 33 192 32
6 8 42 7 23 132 22 65 384 64
( )
= ( − 1) = 1+ (19)
Based on the comparison carried among the proposed
( )
N=2+ (20) methods, the following are some observations.
1) Comparing to the second and third methods, the
M = 6(N-1) (21) first method has a high modularity degree since the
symmetric structure of CHB makes use of equal dc
3) By making a binary (power of 2) relationship voltage supplies. This method helps the proposed
between thedc supplies of the CHB structure as inverter to reach all maximum number of voltage
follows: levels (4, 5, 6, 7, 8,...,N).

= 2( ) ( ) (22) 2) Since the second and third methods use the

asymmetrical structure of CHB, the proposed inverter
can reach the required output voltage and the
= 2( ) ( ) (23)
maximum number of voltage levels such as 5, 8, 9,
12, 17,...with less number of dc voltage supplies and
power electronic components.

V. COMPARISON STUDY
In order to investigate the capability of the
suggested configuration, the proposed inverter is
compared with different types of multilevel inverters
such as NPC, FC, and CHB. It is evident that the
suggested three-phase N-level multilevel inverter can
considerably minimize the required number of power
components. For the same number of output voltage
levels (N ≥ 4),Table V explains the required number
of dc voltage supplies, switches, clamping diodes,
control signals, and balancing capacitors of the
Fig. 7. Circuit diagram of the proposed three-phase N-level proposed N-level inverter compared with three
multilevel inverter existing inverters NPC, FC, and CHB. As shown in
Fig. 8,it can be noticed that nearly more than two-
= 2( )
( ) (24) thirds of number of switches can be counted out as N
increases. For instance, at the same number of
voltage levels N = 17, and compared with the existing
=( − 1) = 1+ 2 = (2 ) (25) multilevel inverters which require 96 switches,
the required number of switches for the proposed
inverter is less since it requires 42 switches based on
N=1+2 (26)
the first method, 22switches based on the second
M=6(N-1) (27)
method, and 20 switches based on the third method.
On the other hand, it is well known that the voltage
Table IV illustrates some characteristics of the and current ratings of the power components have an
proposed methods.

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effect on the cost and realization of the _ = ∫0 _ () (31)

multilevel inverter. Assuming that all power
components have an equal current rating which is the Conduction power losses of IGBT and diode are
rated current of the load (IL), the voltage ratings of approximated based on their forward voltage drops
these components depend on the magnitude of dc Von IGBT ,Von diode ,and the instantaneous current i(t)
voltage supplies, voltage stress, and structure of the flowing through IGBT or diode. The total losses Pt
inverter Considering that all inverters have the same are expressed as follows:
input dc link which equals(N–1) Vdc, Table VI
illustrates the rating requirements for the proposed = + (32)
inverter comparing with the rating requirements for
the existing inverters. It is observed that the inverter Once the total semiconductors losses Pt in the
employs switching devices with high voltage rating.
introduced inverter are defined, the relative inverter
That results in high cost per-switch. Since the
topology is introduced with reduced number of efficiency is determined based on the following
switches, gate driver circuit, diodes and no clamping expression:
capacitors are involved, the semiconductor devices
expenses are considerably recovered. %= × 100 (33)

VI. POWER CONVERSION EFFICIENCY AND TOTAL

Table VII provides the possible current directions
HARMONICDISTORTION (THD%)
In order to determine the efficiency of the with corresponding conducting devices in phase a.
proposed inverter, it is necessary to determine the
value of conduction and switching power losses MATLAB/ Simulink model of the proposed inverter
generated by the semiconductor components. shown in Fig. 1 has been developed to study the
Basically, the main losses in semiconductor conduction and switching power losses. The
components such as IGBTs and diodes are proposed inverter is designed to deliver output
categorized into two groups: conduction loss (Pcon) power of Pout = 1.9 kW. Three-phase series resistive–
and switching loss (Psw) as follows: inductive (23 Ω–3 mH/Phase) in star connection is
= ∫ ( ) + ∫ ( ) ( ) (28)
used as load. The multilevel dc link is determined as
_
Vdc= 75 V, 2Vdc = 150 V, and Vfix= 4Vdc = 300 V and
the proposed staircase modulation technique at Ma =
_ = ∫ ( ) (29) 1 is implemented to generate the appropriate
switching gate signals. Three different types of
Where Eon(t) is a turn-on loss and Eoff (t) is a turn-off semiconductor components are selected to build the
loss. Switching losses Eon(t) and Eoff (t) are prototype of the proposed inverter power circuit as
experienced during the ON and OFF states, following: IGBT (HGTG20N60B3D)600 V/40 A for
respectively. While Err(t) is the reverse recovery loss the two-level bridge and CHB switches, IGBT
of the diode, the majority of switching loss, which (IRG4BC40W) 600 V/20 A for bidirectional
is experienced when the diode is turned OFF (OFF switches, and Diode (RHRP1540) 400 V/15 A for
state) embedded diodes in

_ = ∫0 _ () (30)

TABLE V
COMPARISON OF THE PROPOSED N-LEVEL INVERTER WITH THE EXISTING INVERTERS

Converter type NPC FC CHB Proposed

1st method 2nd method 3rd method

Switches 6(N-1) 6(N-1) 6(N-1) 2(N-1)+10 √8 − 15 + 11 2 ( − 1) + 12

Gate drivers 6(N-1) 6(N-1) 6(N-1) 2(N-1)+7 √8 − 15 + 8 2 ( − 1) + 9

Diodes 6(N-1) 6(N-1) 6(N-1) 2(N-1)+10 √8 − 15 + 11 2 ( − 1) + 12

Clamping diodes 6(N-2) 0 0 0 0 0

DC supplies N-1 N-1 3(N-1)/2 N-1 1+[(√8 − 15 − 1)/2] 1+ ( − 1)

Clamping capacitors 0 3(N-2) 0 0 0 0

Control signals 6(N-1) 6(N-1) 6(N-1) 2(N-1)+7 √8 − 15 + 8 2 ( − 1) + 9

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Therefore, the conduction and switching power losses

for the inverter switches and diodes can be estimated
by substituting (34)–(40) into (28)–(33). The
efficiency of the proposed inverter is estimated while
the input voltage is raised in small steps. Fig. 9(a)
depicts the estimated value of efficiency over a wide
range of the output power. It is clear that the
inverter’s efficiency varies directly proportional to
the output power and reaches its maximum value of
96.53% at 1.9 kW. It is a result of more power being
effectively transferred with respect to the power
losses. Furthermore, the power losses distribution
among the inverter’s legs and the CHB cells are
shown in Fig. 9(b). The power losses distribution is
Fig. 8. Comparison of required number of switches among existing
inverters and the proposed topology
obtained during the operation of the proposed
inverter to deliver Pout = 1.287 kW at voltage step
bidirectional switches and freewheeling diodes. The Vdc= 62.5 V, 2Vdc = 125 V, and Vfix= 4Vdc = 250 V.
data sheets of the utilized semiconductor components The power losses generated by legs a,b, and c are
are easily accessed to acquire their characteristics almost equal and slightly higher than those generated
curves. To simplify the losses calculation, a curve- by CHB cells. According to Fig. 9(b), 53.3% of the
fitting tool of MATLAB is used to approximate
total value of power loss is experienced in the
these curves by exponential equations [35]. The
mathematical models obtained for HGTG20N60B3D conventional two-level bridge since 3 × 9.92 W
600 V/40 A are given by in term of conduction power losses is generated by
Q1–Q6. It is definitely due to fact that the conduction
. ( )
_ = 1.418 (34) power loss is directly proportional to the switch
conduction time and the value of conducting current
. ( ) . ( )
_ = (201.6 − 291.6 )× 10 (35) (for instance, Q1 and Q2 conduct the load
. ( ) current in 18 modes). Negligible conduction power
_ = (323.9 ) × 10 (36)
losses are generated by the free whiling diodes (D1–
While the mathematical models obtained for D6). Further measurements show that 9.68 + 2.2 W is
IRG4BC40W600 V/20 A are given by the estimated value of the conduction power losses
generated by CHB’s switches and diodes. It is almost
. ( )
_ = 1.555 (37) 21.3% of total power loss. The higher conduction
power loss is experienced in T3 followed by T1, T4,
. ( )
_ = (0.3405 ) × 10−3 (38) and T2. The three bidirectional switches contribute to
19.6% of the total power loss as 3 × 3.66 W is the
And finally, the mathematical models obtained for estimated value of conduction power loss generated
RHRP1540 400 V/15 A are given by by S1–S6 and Da1–Dc2. Finally, it can be observed
= 1.325 . ( )
− 0.8571 . ( )
(39)
that a negligible switching loss is generated since the
_
fundamental frequency is implemented. Furthermore
. ( )
_ = (15.7 − 2.74 . ( )
- and in order to access the performance of the
. ( ) . ( )
3.162 −8 )× 10 (40) proposed inverter comparing with other type of the

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TABLE VI
PROPOSED AND THE EXISTING T OPOLOGIES R ATING REQUIREMENTS PER LEVEL N

Proposed Main Bidirectional Cascaded half bridge switches T11 to Converter type NPC FC CHB
inverter bridge Switches S1 to Tn2
Q1~Q6 S6 1st method 2nd 3rd method Switches voltage
D1a-D2c D1 to D6 method rating Vdc Vdc Vdc
Component Clamping Diode
voltage rating (N-1)Vdc (N-2)Vdc Vdc nVdc 2( )
Vdc voltage rating Vdc 0 0
Clamping capacitor
voltage rating 0 Vdc 0
Active Active component
component IL IL IL IL IL current IL IL IL
current

TABLE VII
CONDUCTING DEVICES OF THE PROPOSED INVERTER PHASE a

Current Conducting Vag Conducting Vag

Devices Phase a. Fig.1(a) Devices Phase a. Fig.1(a)

Ia>0 Q1 +4Vdc Q1 +4Vdc

T1, T3, S2, Da2 +3Vdc T1, T3, S2, Da2 +3Vdc
Dz2, T3, S2, Da2 +2Vdc Dz2, T3, S2, Da2 +2Vdc
T1, Dz4, S2, Da2 +Vdc T1, Dz4, S2, Da2 +Vdc
D2, Da2 0 D2 0
Ia<0 D1, Da1 +4Vdc D1 +4Vdc
Dz1, Dz3, S1, Da1 +3Vdc Dz1, Dz3, S1, Da1 +3Vdc
T2, Dz3, S1, Da1 +2Vdc T2, Dz3, S1, Da1 +2Vdc
Dz1, T4, S1, Da1 +Vdc Dz1, T4, S1, Da1 +Vdc
Q2 0 Q2 0

multilevel inverter, a nine-level NPC multilevel under different modulation indices (Ma = 0.9, 1, and
inverter built by IRG4BC40W 600 V/20 A and 1.15). THD% of the output voltage can be calculated
conditions to the proposed inverter. The estimated by
value of efficiency and power losses distribution of
the NPC multilevel inverter are shown in Fig. 9(c) ∑∞
and (d). Comparison of the proposed inverter’ THD%= × 100% (41)
efficiency with the nine-level NPC multilevel
inverter’s efficiency shows that the proposed inverter Where V1 and Vk are the fundamental component and
has a higher efficiency since the maximum harmonic order, respectively. NPC, FC, and CHB
estimated efficiency of the NPC multilevel inverter multilevel inverters have been tested under the same
is 93.85%. The lower Pt generated by the proposed operating conditions. The goal of his test is to
inverter comparing with Pt generated by the nine- compare the proposed inverter with the existing
level NPC multilevel inverter is a result of the low inverters in term of THD%. Fig. 10 depicts THD% of
conduction power losses and reduced number of the line to line voltage for all inverters within specific
power components. A lower voltage stress range of modulation indices [0.9–1.15]. It can be seen
leads to a lower switching power loss. However, the that the THD% of all inverter is slightly different.
more the switching devices, the higher the The measured values of THD% for the proposed
conduction power losses. At the same operating point inverter are within a range of 8.4–13.25%. As a
Pout ≈ 1.287 kW and compared with the estimated result, the proposed inverter essentially adds the
value of Pt proposed = 3 × 14.4 + 12.78 ≈ 55.9 W attractive aspects of the traditional two-level inverter
generated by the proposed inverter, the estimated such as less power components, simple working
value of Pt generated by the NPC multilevel inverter principle, and minimum conduction power loss to the
is two times higher. It is nearly Pt NPC = 3 × 37.5 ≈ main advantages of the multilevel inverter such as
112.5 W. low THD% and high output voltage quality
Moreover, the proposed inverter has been tested

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 INTERNATIONAL JOURNAL
OF PROFESSIONAL ENGINEERING STUDIES Volume V /Issue 3 /AUG 2015

VII. CONCLUSION [9] K. Ilveset al., “A new modulation method for the
A new topology of the three-phase nine- modular multilevel converter allowing fundamental
level multilevel inverter was introduced. The switching frequency,” IEEE Trans. PowerElectron.,
suggested configuration was obtained from reduced vol. 27, no. 8, pp. 3482–3494, Aug. 2012.
number of power electronic components. Therefore,
[10] W. Yong and W. Fei, “Novel three-phase three-
the proposed topology results in reduction of
installation area and cost. The fundamental frequency level-stacked neutral point clamped grid-tied solar
staircase modulation technique was comfortably inverter with a split phase controller,” IEEE
employed and showed high flexibility and simplicity Trans.Power Electron., vol. 28, no. 6, pp. 2856–
in control. Moreover, the proposed configuration was 2866, Jun. 2013.
extended to N-level with different methods.
Furthermore, the method employed to determine the
magnitudes of the dc voltage supplies was well
executed. In order to verify the performance of the
proposed multilevel inverter, the proposed A.Dileshwar Rao .Completed
configuration was simulated and its prototype was
B.Tech in Electrical & Electronics Engineering in
manufactured. The obtained simulation and hardware
results met the desired output. Hence, subsequent 2013 from ST. MARTIN’S ENGINEERING
work in the future may include an extension to COLLEGE qutubullapur Affiliated to JNTUH,
higher level with other suggested methods. For Hyderabad and M.Tech in Power Electronics joined
purpose of minimizing THD%, a selective harmonic 2013 from Gokaraju Rangaraju Institute of
elimination pulse width modulation technique can be Engineeringand Technology Affiliated to JNTUH.
also implemented. Working on my project at Gokaraju
REFERENCES
RangarajuInstitute of Engineeringand Technology,
[1] J. Rodriguez et al., “Multilevel inverters: A
Hyderabad, Telangana, India.His current research
survey of topologies, controls, and applications,”
interests include simulation of Multilevel inverter.
IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–
Email id: adileshwarrao@gmail.com
738, Aug. 2002.
[2] L. G. Franqueloet al., “The age of multilevel
converters arrives,” IEEEInd. Electron. Mag., vol. 2,
no. 2, pp. 28–39, Jun. 2008.
[3] I. Colaket al., “Review of multilevel voltage P.PRAVEEN KUMAR.Completed
source inverter topologies and control schemes,” B.Tech in Electrical & Electronics Engineering in
Energy Convers. Manage.,vol. 52, pp. 1114– 2006 from VNR Vignanajyothi Institute of
1128,2011. engineering and Technology,Hyderabad and M.Tech
[4] J. Rodriguez et al., “Multilevel converters: An in Power Electronics in 2008 from Gokaraju
enabling technology for high-power applications,” Rangaraju Institute of Engineering and Technology,
Hyderabad, Telangana, Affiliated to JNTUH,
Proc. IEEE, vol. 97, no. 11, pp. 1786–1817, Nov.
Hyderabad. Working as Assistant Professor at
2009. Gokaraju Rangaraju Institute of Engineeringand
[5] J. Rodriguez et al., “A survey on neutral-point- Technology, Hyderabad, Telangana, India. Area of
clamped inverters,” IEEETrans. Ind. Electron., vol. interest includessimulation of Multilevel inverter, Ac
57, no. 7, pp. 2219–2230, Jul. 2010. drives, and DC-DC converters.
[6] S. Gui-Jia, “Multilevel DC-link inverter,” IEEE Email id: praveenpandugu@gmail.com
Trans. Ind. Appl., vol. 41, no. 3, pp. 848–854,
May/Jun. 2005.
[7] P. Fang Zheng, “A generalized multilevel inverter
topology with self voltage balancing,” IEEE Trans.
Ind. Appl., vol. 37, no. 2, pp. 611–618, Mar./Apr.
2001.
[8] J. A. Ferreira, “The multilevel modular DC
converter,” IEEE Trans. PowerElectron., vol. 28, no.
10, pp. 4460–4465, Oct. 2013.

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