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Expt 5 Encoder Decoder

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Kathirvelu Dhandapani
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275 views

Expt 5 Encoder Decoder

Uploaded by

Kathirvelu Dhandapani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment 5: DESIGN OF ENCODER AND DECODER

AIM:
To design and implement encoder and decoder using logic gates.

APPARATUS REQUIRED:

S.No. Component Specification Qty.


1. 3 I/P NAND Gate IC 7410 2
2. OR Gate IC 7432 3
3. NOT Gate IC 7404 1
4. IC Trainer Kit - 1
5. Patch Cords - As required

THEORY:

Decoder:
A binary code of n bits is capable of representing up to 2n distinct elements of coded
information. A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n unique output lines. Their purpose is to generate the 2n (or fewer)
minterms of n input variables. Each combination of inputs will assert a unique output. The
name decoder is also used in conjunction with other code converters.
Some decoders are constructed with NAND gates. Since a NAND gate produces the AND
operation with an inverted output, it becomes more economical to generate the decoder
minterms in their complemented form. Furthermore, decoders include one or more enable
inputs to control the circuit operation. A two-to-four-line decoder with an enable input
constructed with NAND gates is implemented in this experiment. The circuit operates with
complemented outputs and a complement enable input. The decoder is enabled when E is equal
to 0 (i.e., active-low enable).

Encoder:
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has
2n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the
binary code corresponding to the input value. In encoder it is assumed that only one input has
a value of one at any given time otherwise the circuit is meaningless. It has an ambiguity that
when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0
= 1. When more than one input is 1 then its an error causing all outputs to go high.
LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:

INPUT OUTPUT
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

PROCEDURE:

1. Connections are given as per circuit diagram.


2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

RESULT:
Thus, the encoder and decoder were designed and implemented using logic gates.

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