Programmable Logic Devices

Dr Alister Hamilton

3-1
 Introduction
 Use of programmable logic devices allows the
implementation of complex logic functions on
a single IC chip.
 Programmable logic devices discussed:
 Read-only memories (ROMs)
 Programmable logic arrays (PLAs)
 Programmable array logic (PAL)
 Complex programmable logic devices (CPLDs)
 Field-programmable gate arrays (FPGAs)

3-2
 Brief Overview of Programmable
Logic Devices
 Programmable logic falls into two different
types:
 1. Devices that can be programmed only once.
 Factory programmable
 2. Devices that can be reprogrammed multiple
times.
 Field programmable

3-3
Brief Overview of Programmable
Logic Devices (continued)

3-4
 Brief Overview of Programmable
Logic Devices (continued)
 Simple programmable logic devices:
 Programmable Logic Arrays (PLAs):
 There is a programmable AND array and a
programmable OR array, allowing users to implement
combinational functions in two levels of gates.
 Programmable Array Logic (PAL):
 A special case of a PLA, in that the OR array is fixed
and only the AND array is programmable.
 Many also contain flip-flops.

 PLAs and PALs were popular in the 1970s and

1980s due to ease of design.

3-5
 Brief Overview of Programmable
Logic Devices (continued)
 Simple programmable logic devices:
 Programmable Logic Devices (PLDs)/Generic
Array Logic (GAL):
 Flash erasable/reprogrammable PALs.
 Contain macroblocks with arrays of gates, multiplexers,
flip-flops, or other standard building blocks. Several of
these macroblocks appear in a PLD.
 Lattice Semiconductor created a line of these: GALs

3-6
 Brief Overview of Programmable
Logic Devices (continued)
 Complex Programmable Logic Devices
(CPLDs):
 Have more integration capability than SPLDs.
 Come in sizes ranging from 500 to 16,000
gates.
 Multiple PLDs placed into the same chip.

3-7
 Brief Overview of Programmable
Logic Devices (continued)
 Field-Programmable Gate Arrays (FPGAs)
 During the late 1980s, Xilinx started using
static RAM storage elements to hold
configuration information.
 Larger and more complex blocks containing
static RAMs and multiplexers.
 With improved technology over the past 15
years, FPGAs can now contain more than 5
million gates.

3-8
 Brief Overview of Programmable
Logic Devices (continued)
 Comparison of devices:

3-9
 Simple Programmable Logic
Devices (SPLDs): Introduction
 Simple Programmable Logic Devices (SPLDs):
 Read-only memories (ROMs)
 Programmable Logic Arrays (PLAs)
 Programmable Array Logic (PAL)
 Programmable Logic Devices (PLDs)/Generic Array
Logic (GAL)

3-10
 Array-Based Programmable Logic

I5 I4 I3 I2 I1 I0 Programmable
OR array I3 I2 I1 I0 Programmable
OR array I5 I4 I3 I2 I1 I0 Fixed OR array

Programmable AND array Fixed AND array Programmable AND array

O3 O 2 O1 O0 O3 O2 O1 O0 O 3 O 2O 1 O 0

PLA PROM PAL

Indicates programmable connection
Indicates fixed connection
 SPLDs: Read-Only Memories
(ROMs)
 Array of semiconductor devices that are
interconnected to store an array of binary
data.
 Once data is stored in the ROM, it can be read
out but it cannot be changed.
 Outputs can be looked up: truth table.
 Basic types: mask-programmable ROMs, user-
programmable ROMs (PROMs), erasable
programmable ROMs (EPROMs), electrically
erasable and programmable ROMs
(EEPROMs), and flash memories.

3-12
 SPLDs: ROMs (continued)
 Types:
 Mask-programmable ROMs: data array is
permanently stored at the time of manufacture.
 PROMs: one-time programmable.
 EPROMs: use a special charge-storage mechanism
to enable or disable the switching elements in the
memory array. Can be erased using ultraviolet light.
 EEPROMs: similar to EPROM except that erasure is
done using electrical pulses. Can be erased and
reprogrammed only a limited number of times.
 Flash memories: similar to EEPROMs, except that
they use a different charge-storage mechanism.
Usually have built-in programming and erasure
capability.

3-13
 SPLDs: ROMs (continued)
 A ROM that has n input lines and m output
lines contains an array of 2n words, and each
word is m bits long.
 A 2n x m ROM can realise m functions of n
variables since it can store a truth table with
2n rows and m columns.
 Typical sizes for commercially available ROMs:
32 words x 4 bits to 512K words x 8 bits, or
larger.

3-14
 SPLDs: ROMs (continued)
 ROM with n inputs and m outputs:

3-15
 SPLDs: ROMs (continued)
 Example:
 Compute the size of the ROM required to
implement an 8-to-3 priority encoder.

3-16
 SPLDs: ROMs (continued)
 Answer:
 The 8-to-3 priority encoder has 8 inputs and 4
outputs. Hence, it needs a 28 x 4 bit ROM.

Note: output d indicates a valid output

3-17
SPLDs: Programmable Logic Arrays
(PLAs)
 Performs the same basic function as a ROM.
 A PLA with n inputs and m outputs can realise
m functions of n variables.
 The internal organisation of the PLA is
different from that of the ROM: the decoder is
replaced with an AND array that realises
selected product terms of the input variables.
The OR array OR’s together the product terms
needed to form the output functions.

3-18
 SPLDs: PLAs (continued)
 Example of PLA that realises these functions:
F0   m(0,1, 4, 6)  A ' B ' AC '
F1   m(2,3, 4, 6, 7)  B  AC '
F2   m(0,1, 2, 6)  A ' B ' BC '
F3   m(2,3,5, 6, 7)  AC  B

3-19
 SPLDs: PLAs (continued)
 From the preceding example, realise the
functions using a PLA:
F1   m(2,3,5, 7,8,9,10,11,13,15)
F2   m(2,3,5, 6, 7,10,11,14,15)
F3   m(6, 7,8,9,13,14,15)
 Minimise each function:
F1  bd  b ' c  ab '
F2  c  a ' bd
F3  bc  ab ' c ' abd

3-20
 SPLDs: PLAs (continued)
 Equations from preceding plotted on Karnaugh
maps:

3-21
 SPLDs: PLAs (continued)
 Instead of minimising each function separately, we
want to minimise the total number of rows in the PLA
table.
 Reduced PLA table and equations:

F1  a ' bd  abd  ab ' c ' b ' c

F2  a ' bd  b ' c  bc
F3  abd  ab ' c ' bc

 Note: a PLA table is different from a truth table for a

ROM, as each row represents a product term.

3-22
SPLDs: Programmable Array Logic
(PAL)
 The AND array is programmable and the OR array is
fixed.
 Less expensive than the PLA because only the AND
array is programmable; for this reason, designers use
PALs to replace individual logic gates when several
logic functions must be realised.
 When designing with PALs, simplify logic equations.
 AND terms cannot be shared among two or more OR gates.
 The number of AND terms that feed each output OR gate is
fixed and limited.
 If the number of AND terms in a simplified function is too large,
we may be forced to choose a PAL with more gate inputs and
fewer outputs.

3-23
 SPLDs: PAL (continued)
 Example:
 I1I’2+I’1I2
 X’s in (b) indicate
connections.

3-24
 SPLDs: Programmable Logic Devices
(PLDs)/Generic Array Logic (GAL)
 Flash erasable/reprogrammable.
 In addition to the AND-OR arrays that PALs
have, most PLDs have some type of a
macroblock that contains some multiplexers
and some additional programmability. These
PLDs are named with reference to their input
and output capability.
 All typically have tristate buffers at the
outputs and some of them have a dedicated
output enable.

3-25
 SPLDs: PLDs/GAL (continued)
 PLD 22CEV10 output macrocell:

3-26
 Complex Programmable Logic
Devices (CPLDs)
 Programmable ICs equivalent to several PLDs
(that are interconnected using crossbar-like
switch) in the same chip.
 When storage elements such as flip-flops are
also included on the same IC, a small digital
system can be implemented with a single
CPLD.
 Essentially, a CPLD is an IC that consists of a
number of PAL-like logic blocks together with
a programmable interconnect matrix.

3-27
 CPLDs (continued)
 N x M crossbar switch: each of the N input
lines can be connected to any of the M output
lines simultaneously.
 It is expensive to build the switches, but using
them results in predictable timing.
 Many CPLDs are electronically erasable and
reprogrammable: EPLDs (erasable PLDs).
 A CPLD contains macrocells grouped into
function blocks.
 Some are based on PALs and some on PLAs.

3-28
 CPLDs (continued)
 Example: Xilinx CoolRunner. Has 4 function
blocks and each block has 16 macrocells.

3-29
 Field-Programmable Gate Arrays
(FPGAs): Introduction
 ICs that contain an array of identical logic blocks
with programmable interconnections.
 Three major programmable elements in FPGAs:
the logic block, the interconnect (routing), and
the input/output block.
 Programmable logic blocks are created by using
multiplexers, look-up tables, and AND-OR or
NAND-NAND arrays.
 Have revolutionised the way prototyping and
designing is done in the world due to the
flexibility offered as it is reprogrammable.
 Vendors: Xilinx, Altera, Lattice Semiconductor,
and Microsemi.

3-30
 FPGAs: Introduction (continued)
 Advantages:
 Reduction in manufacturing time as one adopts
FPGAs instead of MPGAs.
 Easier design iterations.
 Less costly to correct design mistakes or
specification changes.
 Reduced prototyping costs.
 At low volumes, FPGAs are cheaper than
MPGAs.

3-31
 FPGAs: Introduction (continued)
 Disadvantages:
 Are less dense than traditional gate arrays (MPGAs).
 A lot of resources are needed to achieve
programmability.
 MPGAs have better performance than FPGAs.
 Interconnection delays are unpredictable in FPGAs.
 PLDs such as PALs and GALs are simple and
inexpensive.
 CPLDs are faster, cheaper, and more predictable in
timing than FPGAs.

3-32
 FPGAs: Organisation
 Matrix-based (symmetrical array):
 Manufacturer: Most Xilinx FPGAs.
 Large granularity: capable of implementing 4-
variable functions or more.
 Typically contain 8 x 8 arrays in the smaller
chips and 100 x 100 or larger arrays in the
bigger chips.
 Routing: two-dimensional channeled (horizontal
and vertical).

3-33
 FPGAs: Organisation (continued)
 Matrix-based (symmetrical array):

3-34
 FPGAs: Organisation (continued)
 Row-based:
 Inspired by traditional gate arrays.
 Traditional mask-programmable gate arrays use very
similar architectures.
 Routing: one-dimensional channeled routing, as the
routing resources are located as a channel in
between rows of logic resources.
 Manufacturer: some Microsemi FPGAs employ this
architecture.

3-35
 FPGAs: Organisation (continued)
 Row-based:

3-36
 FPGAs: Organisation (continued)
 Hierarchical:
 Blocks of logic cells are grouped together by a
local interconnect, and several such groups are
interconnected by another level of interconnect.
 Manufacturer: Altera APEX20 and APEX II.

3-37
 FPGAs: Organisation (continued)
 Hierarchical:

3-38
 FPGAs: Organisation (continued)
 Sea-of-gates:
 Consists of a large number of gates with an
interconnect superimposed on the sea of gates.
 Manufacturers: Plessey – mid-1990’s (sea-of-
gates), Microsemi Fusion (sea of tiles).

3-39
 FPGAs (continued)
 Sea-of-gates:

3-40
FPGAs: Programming Technologies
 FPGAs consist of a large number of logic
blocks interspersed with a programmable
interconnect.
 Programmable:
 The logic block: the same building block can be
“programmed” or “configured” to create any
desired circuitry.
 Interconnections between the logic blocks.

3-41
FPGAs: Programming Technologies
(continued)
 StaticRAM (SRAM):
 Involves creating reconfigurability by bits
stored in SRAM cells.
 Logic blocks, I/O blocks, and interconnects can
be made programmable by using configuration
bits stored in SRAM.
 Reconfigurable logic blocks can easily be
implemented as look-up tables (LUTs).
 Bits that are stored in the SRAM for deciding
the LUT functionality or interconnection are
called configuration bits.

3-42
FPGAs: Programming Technologies
(continued)
 SRAM:
 A cell usually takes six transistors.
 Write Operation: when the Word Line is set to
high, the values on the Bit Line will be latched
into the cell.
 Read operation: done by precharging the Bit
Line and Bit Line to a logic 1 and then setting
Word Line to high. The contents stored in the
cell will then appear on the Bit Line.

3-43
FPGAs: Programming Technologies
(continued)
 Typical 6-transistor SRAM cell:

3-44
FPGAs: Programming Technologies
(continued)
 SRAM Advantages:
 Volatile: new contents can be written again and
again.
 Fabrication steps are the same for making
SRAM cells and for making logic.
 SRAM Disadvantages:
 Cost: five or six transistors are used for every
SRAM cell.
 Volatile: another device (such as an EPROM) is
needed to store the configuration bits.

3-45
FPGAs: Programming Technologies
 EPROM/EEPROM:
 Used to control programmable connections.
 Compared with SRAMs:
 Are slower than SRAMs; SRAMS can be programmed
faster.
 EPROMs also require more processing steps than
SRAM.
 EEPROM is similar to EPROM, but removal of
the gate charge can be done electrically.

3-46
FPGAs: Programming Technologies
(continued)
 EPROM/EEPROM:
 Flash memory:
 A form of EEPROM.
 Allows multiple locations/segments to be erased in one
operation by pulling electrons off.
 Stores information in floating gate transistors as in
EPROM.
 Cell is read by placing a specific voltage on the control
gate.

3-47
FPGAs: Programming Technologies
(continued)
 Antifuse:
 Programming: changes from high resistance (open)
to low resistance (closed) when a high voltage is
applied to it.
 Normally OFF.
 One-time programmable.
 Antifuse Advantages:
 Area consumed is small.
 Connections are faster than SRAM and EEPROM.
 Antifuse Disadvantages:
 Not reprogrammable.

3-48
FPGAs: Programming Technologies
(continued)
 Comparison of technologies:

3-49
FPGAs: Programmable Logic Block
Architectures
 Look-Up-Table–Based Programmable Logic
Blocks:
 Many LUT–based FPGAs use a 4-variable look-
up table (LUT4) plus a flip-flop as the basic
element and then combine them in different
ways.
 Very common for Xilinx and Altera.

3-50
FPGAs: Programmable Logic Block
Architectures (continued)
 Look-Up-Table–Based Programmable Logic
Blocks:

3-51
FPGAs: Programmable Logic Block
Architectures (continued)
 Logic Blocks Based on Multiplexers and Gates:
 Any combinational function can be
implemented using multiplexers alone.
 Microsemi is a manufacturer of multiplexer-
based FPGAs.

3-52
FPGAs: Programmable Logic Block
Architectures (continued)
 Logic Blocks Based on Multiplexers and Gates:

3-53
 FPGAs: Programmable
Interconnects
 There are different types of interconnection
resources in all commercial FPGAs. Every
vendor has its own specific names for the
different types of interconnects in their FPGA.
 Main types:
 Interconnects in Symmetric Array
 Row-based

3-54
 FPGAs: Programmable
Interconnects (continued)
 Interconnects in Symmetric Array FPGAs:
 General-purpose
 Direct interconnects
 Global lines

3-55
 FPGAs: Programmable
Interconnects (continued)
 General-purpose:
 Use switch matrices that provide interconnections
between routing wires connected to the switch
matrix.

3-56
 FPGAs: Programmable
Interconnects (continued)
 Direct interconnects:
 Special connections between adjacent logic
blocks. Interconnects are fast because they do
not go through the routing matrix.
 Direct interconnections are to the four nearest
neighbours or, in some cases, to eight
neighbouring blocks.

3-57
 FPGAs: Programmable
Interconnects (continued)
 Direct interconnects:
 Nearest 4 and 8 neighbouring blocks

3-58
 FPGAs: Programmable
Interconnects (continued)
 Global lines:
 Routing lines span the entire width/height of
device.
 A limited number (two or four) of such global
lines are provided by many FPGAs in horizontal
and vertical directions.

3-59
 FPGAs: Programmable
Interconnects (continued)
 Global lines:

3-60
 FPGAs: Programmable
Interconnects (continued)
 Row-Based:
 Has rows of logic blocks and channels of
switches to enable connections between the
logic blocks.
 Routing resources in these are similar to
routing in traditional gate arrays.
 Interconnects are either nonsegmented or
segmented.
 Nonsegmented has a high area overhead compared to
segmented.

3-61
 FPGAs: Programmable
Interconnects (continued)
 Row-Based:
 Non-segmented vs. segmented

3-62
 FPGAs: Programmable I/O Blocks
 I/O blocks on modern FPGAs allow use of the
pin as input and/or output, in direct
(combinational) or latched forms, in tristate
true or inverted forms, and with a variety of
I/O standards.

3-63
 FPGAs: Programmable I/O Blocks
(continued)
 Programmable I/O block (based on Xilinx):

3-64
 FPGAs: Programmable I/O Blocks
(continued)
 I/O Standards:
 LVTTL: low-voltage transistor-transistor logic; 3.3-V
standard that can tolerate 5-V signals.
 PCI: peripheral component interconnect; has 5-V and 3.3-V
versions.
 LVCMOS: low-voltage complementary metal-oxide
semiconductor; LVCMOS2, a 2.5-V standard that can
tolerate 5-V signals.
 LVPECL: low-voltage positive emitter-coupled logic
 SSTL: stub-series terminated logic
 AGP: advanced graphics port
 CTT: center tap terminated
 GTL: gunning transceiver logic
 HSTL: high-speed transceiver logic

3-65
 FPGAs: Dedicated Specialised
Components
 Dedicated Memory:
 A key feature of modern FPGAs is the
embedding of dedicated memory blocks (RAM)
onto the chip.
 Modern FPGAs include 16K to 10M bits of
memory. The width of the embedded RAM often
can be adjusted.

3-66
 FPGAs: Dedicated Specialised
Components (continued)
 Dedicated Arithmetic Units:
 Used to implement arithmetic logic.
 Implementation generally takes more area and
power and is slower than custom
implementations. It is therefore of benefit to
provide dedicated fast-carry logic to create fast
adders.
 Many FPGAs also contain dedicated multipliers
that are more efficient than those implemented
using the programmable logic in the FPGA.

3-67
 FPGAs: Dedicated Specialised
Components (continued)
 Digital Signal Processing (DSP) Blocks:
 Dedicated multipliers help DSP applications.
 Example: Xilinx Virtex 5
 Carry chains to facilitate addition.
 Example: Altera Stratix IV

 Also provided: DSP building blocks such as

hardware for fast Fourier transforms (FFTs),
finite impulse response (FIR) filters, infinite
impulse response (IIR) filters, encryption/
decryption, compression/decompression, and
security functions.

3-68
 FPGAs: Dedicated Specialised
Components (continued)
 Embedded Processors:
 Many modern FPGAs contain an entire
processor core which is useful when designers
use hybrid solutions.
 Some also include: the core of a small MIPS
processor (i.e., MIPS R 4000), an embedded
version of the IBM PowerPC processor, or
custom processors (i.e., MicroBlaze from
Xilinx).

3-69
 FPGAs: Dedicated Specialised
Components (continued)
 Content Addressable Memories (CAM):
 Memory blocks can be used as content
addressable memories (CAMs).
 A CAM is a special kind of memory in which the
content, not the address, is used to search the
memory.
 CAMs contain more logic than RAMs.

3-70
 FPGAs: Applications
 Rapid prototyping:
 FPGAs can contain 5 million or more gates, so many
large real-world systems can be prototyped using a
single FPGA.
 Multiple FPGAs can be interconnected to realise large
systems.
 Accomplished by using boards with multiple FPGAs
and plugging multiple boards into a backplane
(motherboard).

3-71
 FPGAs: Applications (continued)
 As Final Product in Medium-Speed Systems:
 When 150-200 MHz is sufficient, FPGAs can be
used as the final product.
 Enhancements to the system can be done as
software updates rather than as hardware
changes.

3-72
 FPGAs: Applications (continued)
 Reconfigurable Circuits and Systems:
 Can build dynamically reconfigurable circuits
and systems.
 SRAM-based FPGAs make it possible to
implement “soft” hardware.
 Used to design circuits and systems that need
multiple functionalities at various times.
 Example: reprogrammable Tomahawk missile.

3-73
 FPGAs: Applications (continued)
 Glue Logic:
 New interface logic can be implemented on the
same FPGA as in a software update.
 Hardware Accelerators/Coprocessors:
 An FPGA can be used to implement the key
kernel, as different kernels can dynamically be
programmed into the FPGA.
 Examples: computer architecture simulator
acceleration, emulation boards, and hardware
test/verification.

3-74
 FPGAs: Design Flow
 Automatic synthesis tools are available that
will take a Verilog description of the system as
an input and generate an interconnection of
gates and flip-flops to realise the system.
 Behavioral models can be translated into
design implementations reasonably efficiently.

3-75
 FPGAs: Design Flow (continued)
 Design steps for a digital system:
 1. Create a behavioral, RTL, or structural model of
the design in a hardware description language such
as Verilog or VHDL.
 2. Simulate and debug the design.
 3. Synthesize the design targeting the desired
device.
 4. Run a mapping/partitioning program.
 5. Run an automatic place and route program.
 6. Run a program that will generate the bit pattern
necessary to program the FPGA.
 7. Download the bit pattern into the internal
configuration cells in the FPGA, and test the
operation of the FPGA.

3-76
 Programmable SoCs (PSOC)
 A system on a chip (SoC) is an IC that
integrates all parts of a system into one chip.
 Intellectual property (IP) cores can be bought
and electronically integrated.
 A PSOC is a field-programmable SoC chip.

3-77
 PSOC (continued)
 Overview of a programmable SoC:

3-78
 Summary
 Technology underlying early programmable
logic devices, such as ROMs, PALs, and PLAs
was presented.
 Simple PLDs and GALs were presented.
 CPLDs and FPGAs were presented.
 FPGA topics discussed include an overview of
the general technology, general organisation
of FPGAs, general structure of logic blocks,
and typical programming techniques.
 PSOC designs were presented.

3-79