16-Bit Single-Chip Microcontroller With C166SV2 Core: Never Stop Thinking

Data Sheet, V1.
0, June 2005
XC164-32F
16-Bit Single-Chip Microcontroller
with C166SV2 Core
Microcontrollers
N e v e r s t o p t h i n k i n g .
Edition 2005-06
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
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Data Sheet, V1.0, June 2005
XC164-32F
16-Bit Single-Chip Microcontroller
with C166SV2 Core
Microcontrollers
N e v e r s t o p t h i n k i n g .
XC164
Revision History: 2005-06 V1.0

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Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15

XC164-32
Derivatives
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Capture/Compare Units (CAPCOM1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7 The Capture/Compare Unit CAPCOM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.8 General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.10 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 40
3.12 High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 41
3.13 TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.14 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.15 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.16 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.17 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.18 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4.1 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4.2 On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.3 External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.4.4 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.4.5 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.2 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Data Sheet 3 V1.0, 2005-06

16-Bit Single-Chip Microcontroller with C166SV2 Core XC164
XC166 Family
1 Summary of Features
• High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with 75 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or
via Prescaler (factors 1:1 … 60:1)
• On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 4 Kbytes On-Chip Data SRAM (DSRAM)
– 6 Kbytes On-Chip Program/Data SRAM (PSRAM)
– 256 Kbytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
– 14-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and
Conversion Time (down to 2.55 µs or 2.15 µs)
– Two 16-Channel General Purpose Capture/Compare Units (12 Input/Output Pins)
– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)
(3/6 Capture/Compare Channels and 1 Compare Channel)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects
(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
– On-Chip Real Time Clock
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
Data Sheet 4 V1.0, 2005-06

XC164-32
Derivatives
Summary of Features
• Up to 12 Mbytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-bit or 8-bit Data Bus Width
– Four Programmable Chip-Select Signals
• Up to 79 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
• Supported by a Large Range of Development Tools like C-Compilers, Macro-
Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators,
Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Support via JTAG Interface
• 100-Pin TQFP Package, 0.5 mm (19.7 mil) pitch
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the XC164 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
This document describes several derivatives of the XC164 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term XC164 throughout this document.
Data Sheet 5 V1.0, 2005-06

XC164-32
Derivatives
Summary of Features
Table 1 XC164 Derivative Synopsis

Derivative1) Temp. Program On-Chip RAM Interfaces
Range Memory
Standard Devices2)
SAK-XC164CS-32F40F -40 °C to 256 Kbytes 2 Kbytes DPRAM, ASC0, ASC1,
SAK-XC164CS-32F20F 125 °C Flash 4 Kbytes DSRAM, SSC0, SSC1,
SAF-XC164CS-32F40F -40 °C to 6 Kbytes PSRAM CAN0, CAN1,
SAF-XC164CS-32F20F 85 °C CC6
SAK-XC164CL-32F40F -40 °C to 256 Kbytes 2 Kbytes DPRAM, ASC0, ASC1,
SAK-XC164CL-32F20F 125 °C Flash 4 Kbytes DSRAM, SSC0, SSC1,
SAF-XC164CL-32F40F -40 °C to 6 Kbytes PSRAM CAN0
SAF-XC164CL-32F20F 85 °C
SAK-XC164CR-32F40F -40 °C to 256 Kbytes 2 Kbytes DPRAM, ASC0, ASC1,
SAK-XC164CR-32F20F 125 °C Flash 4 Kbytes DSRAM, SSC0, SSC1,
SAF-XC164CR-32F40F -40 °C to 6 Kbytes PSRAM CAN0,
SAF-XC164CR-32F20F 85 °C CC6
SAK-XC164CB-32F40F -40 °C to 256 Kbytes 2 Kbytes DPRAM, ASC0, ASC1,
SAK-XC164CB-32F20F 125 °C Flash 4 Kbytes DSRAM, SSC0, SSC1,
SAF-XC164CB-32F40F -40 °C to 6 Kbytes PSRAM CAN0, CAN1
SAF-XC164CB-32F20F 85 °C
Grade A Devices2)
SAK-XC164CS-32F40F -40 °C to 256 Kbytes 2 Kbytes DPRAM, ASC0, ASC1,
SAK-XC164CS-32F20F 125 °C Flash 4 Kbytes DSRAM, SSC0, SSC1,
SAF-XC164CS-32F40F -40 °C to 6 Kbytes PSRAM CAN0, CAN1,
SAF-XC164CS-32F20F 85 °C CC6
1) This Data Sheet is valid for devices starting with and including design step BA.
2) The Flash speed grading indicates the access time to the on-chip Flash module. According to this access time
Flash waitstates must be selected (bitfield WSFLASH in register IMBCTRL) according to the intended
operating frequency. For more details, please refer to Section 4.4.2.
Grade A devices are identified by “Grade A” in the fourth line of the chip marking.
Data Sheet 6 V1.0, 2005-06

XC164-32
Derivatives
General Device Information
2 General Device Information
2.1 Introduction
The XC164 derivatives are high-performance members of the Infineon XC166 Family of
full featured single-chip CMOS microcontrollers. These devices extend the functionality
and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and
speed. They combine high CPU performance (up to 40 million instructions per second)
with high peripheral functionality and enhanced IO-capabilities. They also provide clock
generation via PLL and various on-chip memory modules such as program Flash,
program RAM, and data RAM.
VAREF VDDI/P
VAGND VSSI/P
PORT0
16 bit
XTAL1
XTAL2 PORT1
16 bit
NMI
RSTIN Port 3
14 bit
RSTOUT XC164
EA Port 4
8 bit
Port 20
5 bit ALE
RD
WR/WRL
Port 5
14 bit Port 9
6 bit
TRST JTAG Debug

via Port 3
MCA05554_XC164
Figure 1 Logic Symbol
Data Sheet 7 V1.0, 2005-06

XC164-32
Derivatives
2.2 Pin Configuration and Definition

The pins of the XC164 are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E*) and C*) mark pins to be used as alternate external
interrupt inputs, C*) marks pins that can have CAN interface lines assigned to them.
P1H.3/A11/T7IN/SCLK1/EX3IN/E*)
P1H.2/A10/C6P2/MTSR1/EX2IN
P1H.0/A8/C6P0/CC23IO/EX0IN
P1H.1/A9/C6P1/MRST1/EX1IN
P1H.7/A15/CC27IO/EX7IN
P1L.7/A7/CTRAP/CC22IO
P1L.6/A6/COUT63
P1L.5/A5/COUT62
P1L.3/A3/COUT61
P1L.1/A1/COUT60
P1L.4/A4/CC62
P1L.2/A2/CC61
P1L.0/A0/CC60
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
XTAL1
XTAL2
VDDP
VSSP
VDDI
VSSI
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RSTIN 1 75 P0H.4/AD12
P20.12/RSTOUT 2 74 P0L.7/AD7
NMI 3 73 P0L.6/AD6
P0H.0/AD8 4 72 P0L.5/AD5
P0H.1/AD9 5 71 P0L.4/AD4
P0H.2/AD10 6 70 P0L.3/AD3
P0H.3/AD11 7 69 P0L.2/AD2
VSSP 8 68 P0L.1/AD1
VDDP 9 67 P0L.0/AD0
P9.0/CC16IO/C*) 10 66 P20.5/EA
P9.1/CC17IO/C*) 11 65 P20.4/ALE
P9.2/CC18IO/C*) 12 64 P20.1/WR/WRL
P9.3/CC19IO/C*) 13 XC164 63 P20.0/RD
P9.4/CC20IO 14 62 VSSP
P9.5/CC21IO 15 61 VDDP
VSSP 16 60 P4.7/A23/C*)
VDDP 17 59 P4.6/A22/C*)
P5.0/AN0 18 58 P4.5/A21/C*)
P5.1/AN1 19 57 P4.4/A20/C*)
P5.2/AN2 20 56 P4.3/A19/CS0
P5.3/AN3 21 55 P4.2/A18/CS1
P5.4/AN4 22 54 P4.1/A17/CS2
P5.5/AN5 23 53 P4.0/A16/CS3
P5.10/AN10/T6EUD 24 52 P3.15/CLKOUT/FOUT
P5.11/AN11/T5EUD 25 51 P3.13/SCLK0/E*)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P3.1/T6OUT/RxD1/TCK/E*)
P5.6/AN6
P5.7/AN7
P3.3/T3OUT/TDO
P3.8/MRST0
P3.9/MTSR0
P3.10/TxD0/E*)
P3.11/RxD0/E*)
P3.12/BHE/WRH/E*)
VSSI
VDDI
TRST
P3.5/T4IN/TxD1/BRKOUT
VAREF
P3.4/T3EUD/TMS
VSSP
VDDP
P3.2/CAPIN/TDI
VAGND
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4EUD
P5.15/AN15/T2EUD
P3.6/T3IN
P3.7/T2IN/BRKIN
MCP06457
Figure 2 Pin Configuration (top view)
Data Sheet 8 V1.0, 2005-06

XC164-32
Derivatives
Table 2 Pin Definitions and Functions

Sym- Pin Input Function
bol Num. Outp.
RSTIN 1 I Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the XC164.
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the
hardware configuration signals settle.
External circuitry must guarantee low level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.
P20.12 2 IO For details, please refer to the description of P20.
NMI 3 I Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164 into power down
mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
P0H.0 - 4 … 7 IO For details, please refer to the description of PORT0.
P0H.3
Data Sheet 9 V1.0, 2005-06

XC164-32
Derivatives
Table 2 Pin Definitions and Functions (cont’d)

bol Num. Outp.
P9 IO Port 9 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 9 is selectable (standard
or special).
The following Port 9 pins also serve for alternate functions:1)
P9.0 10 I/O CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.,
I CAN2_RxD CAN Node 2 Receive Data Input,
I EX7IN Fast External Interrupt 7 Input (alternate pin B)
O CAN2_TxD CAN Node 2 Transmit Data Output,
I EX7IN Fast External Interrupt 7 Input (alternate pin A)
P9.4 14 I/O CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp.
P9.5 15 I/O CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp.
P5 I Port 5 is a 14-bit input-only port.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
P5.0 18 I AN0
P5.1 19 I AN1
P5.2 20 I AN2
P5.3 21 I AN3
P5.4 22 I AN4
P5.5 23 I AN5
P5.10 24 I AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
P5.6 26 I AN6
P5.7 27 I AN7
P5.12 30 I AN12, T6IN GPT2 Timer T6 Count/Gate Input
P5.13 31 I AN13, T5IN GPT2 Timer T5 Count/Gate Input
Data Sheet 10 V1.0, 2005-06

XC164-32
Derivatives

bol Num. Outp.
TRST 36 I Test-System Reset Input. A high level at this pin activates
the XC164’s debug system. For normal system operation,
pin TRST should be held low.
or special).
The following Port 3 pins also serve for alternate functions:
P3.1 39 O T6OUT GPT2 Timer T6 Toggle Latch Output,
I/O RxD1 ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
I EX1IN Fast External Interrupt 1 Input (alternate pin A),
I TCK Debug System: JTAG Clock Input
P3.2 40 I CAPIN GPT2 Register CAPREL Capture Input,
I TDI Debug System: JTAG Data In
P3.3 41 O T3OUT GPT1 Timer T3 Toggle Latch Output,
O TDO Debug System: JTAG Data Out
P3.4 42 I T3EUD GPT1 Timer T3 External Up/Down Control Input,
I TMS Debug System: JTAG Test Mode Selection
P3.5 43 I T4IN GPT1 Timer T4 Count/Gate/Reload/Capture In.,
O TxD1 ASC0 Clock/Data Output (Async./Sync.),
O BRKOUT Debug System: Break Out
P3.6 44 I T3IN GPT1 Timer T3 Count/Gate Input
P3.7 45 I T2IN GPT1 Timer T2 Count/Gate/Reload/Capture In.,
I BRKIN Debug System: Break In
P3.8 46 I/O MRST0 SSC0 Master-Receive/Slave-Transmit In/Out.
P3.9 47 I/O MTSR0 SSC0 Master-Transmit/Slave-Receive Out/In.
P3.10 48 O TxD0 ASC0 Clock/Data Output (Async./Sync.),
P3.11 49 I/O RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
P3.12 50 O BHE External Memory High Byte Enable Signal,
O WRH External Memory High Byte Write Strobe,
P3.13 51 I/O SCLK0 SSC0 Master Clock Output / Slave Clock Input,
P3.15 52 O CLKOUT System Clock Output (= CPU Clock),
O FOUT Programmable Frequency Output
Data Sheet 11 V1.0, 2005-06

XC164-32
Derivatives

bol Num. Outp.
P4 IO Port 4 is an 8-bit bidirectional I/O port. Each pin can be
or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:1)
P4.0 53 O A16 Least Significant Segment Address Line,
O CS3 Chip Select 3 Output
P4.1 54 O A17 Segment Address Line,
P4.7 60 O A23 Most Significant Segment Address Line,
Data Sheet 12 V1.0, 2005-06

XC164-32
Derivatives

bol Num. Outp.
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
P20.0 63 O RD External Memory Read Strobe, activated for
every external instruction or data read access.
P20.1 64 O WR/WRL External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.
P20.4 65 O ALE Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.
P20.5 66 I EA External Access Enable pin.
A low level at this pin during and after Reset
forces the XC164 to latch the configuration from
PORT0 and pin RD, and to begin instruction
execution out of external memory.
A high level forces the XC164 to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. “ROMless” versions must
have this pin tied to ‘0’.
P20.12 2 O RSTOUT Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.
Note: Port 20 pins may input configuration values (see EA).
Data Sheet 13 V1.0, 2005-06

XC164-32
Derivatives

bol Num. Outp.
PORT0 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. Each pin can be programmed for input (output
P0L.0 - 67 - 74 driver in high-impedance state) or output.
P0L.7 In case of an external bus configuration, PORT0 serves as
P0H.0 - 4 - 7 the address (A) and address/data (AD) bus in multiplexed
P0H.3 bus modes and as the data (D) bus in demultiplexed bus
P0H.4 - 75 - 78 modes.
P0H.7 Demultiplexed bus modes:
8-bit data bus: P0H = I/O, P0L = D7 - D0
16-bit data bus: P0H = D15 - D8, P0L = D7 - D0
Multiplexed bus modes:
8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0
16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0
Note: At the end of an external reset (EA = 0) PORT0 also
may input configuration values
PORT1 IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes (also after switching from a
demultiplexed to a multiplexed bus mode).
The following PORT1 pins also serve for alt. functions:
P1L.0 79 I/O CC60 CAPCOM6: Input / Output of Channel 0
P1L.1 80 O COUT60 CAPCOM6: Output of Channel 0
P1L.6 85 O COUT63 Output of 10-bit Compare Channel
P1L.7 86 I CTRAP CAPCOM6: Trap Input
CTRAP is an input pin with an internal pull-up resistor. A low
level on this pin switches the CAPCOM6 compare outputs to
the logic level defined by software (if enabled).
I/O CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp.
P1H … …continued…
Data Sheet 14 V1.0, 2005-06

XC164-32
Derivatives

bol Num. Outp.
PORT1 IO …continued…
(cont’d)
P1H.0 89 I CC6POS0 CAPCOM6: Position 0 Input,
I EX0IN Fast External Interrupt 0 Input (default pin),
I/O CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.
I/O MRST1 SSC1 Master-Receive/Slave-Transmit In/Out.
I/O MTSR1 SSC1 Master-Transmit/Slave-Receive Out/Inp.
P1H.3 92 I T7IN CAPCOM2: Timer T7 Count Input,
I/O SCLK1 SSC1 Master Clock Output / Slave Clock Input,
P1H.4 93 I/O CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp.,
I EX4IN Fast External Interrupt 4 Input (default pin)
XTAL2 99 O XTAL2: Output of the oscillator amplifier circuit
XTAL1 100 I XTAL1: Input to the oscillator amplifier and input to the
internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC.
Characteristics must be observed.
VAREF 28 – Reference voltage for the A/D converter.
VAGND 29 – Reference ground for the A/D converter.
VDDI 35, 97 – Digital Core Supply Voltage (On-Chip Modules):
+2.5 V during normal operation and idle mode.
Please refer to the Operating Condition Parameters.
Data Sheet 15 V1.0, 2005-06

XC164-32
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bol Num. Outp.
VDDP 9, 17, – Digital Pad Supply Voltage (Pin Output Drivers):
38, 61, +5 V during normal operation and idle mode.
87 Please refer to the Operating Condition Parameters.
VSSI 34, 98 – Digital Ground
VSSP 8, 16, – Connect decoupling capacitors to adjacent VDD/VSS pin pairs
37, 62, as close as possible to the pins.
88 All VSS pins must be connected to the ground-line or ground-
plane.
1) The CAN interface lines are assigned to ports P4 and P9 under software control.
Data Sheet 16 V1.0, 2005-06

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Functional Description
3 Functional Description
The architecture of the XC164 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164.
PSRAM DPRAM DSRAM
ProgMem EBC
Flash CPU LXBus Control
256 Kbytes External Bus
PMU
DMU
C166SV2 - Core Control

OCDS
Debug Support
LXBus
XTAL
Osc / PLL
RTC WDT Interrupt & PEC
Clock Generator
Interrupt Bus
ADC GPT ASC0 ASC1 SSC0 SSC1 CC1 CC2 CC6 Twin
Peripheral Data Bus
8-Bit/ USART USARTSPI SPI CAN

T2
10-Bit T0 T7 T12
14 Ch T3
T1 T8 T13
T4
T5 A B
T6 BRGen BRGen BRGen BRGen
P 20 P 9 Port 5 Port 4 Port 3 PORT1 PORT0
5 6 14 8 14 16 16
MCB04323_X432
Figure 3 Block Diagram
Data Sheet 17 V1.0, 2005-06

XC164-32
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3.1 Memory Subsystem and Organization

The memory space of the XC164 is configured in a Von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed bytewise or wordwise. Portions of the
on-chip DPRAM and the register spaces (E/SFR) have additionally been made directly
bitaddressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, code is fetched from external memory, or data is read from or written to
external resources, including peripherals on the LXBus (such as TwinCAN). The system
bus allows concurrent two-way communication for maximum transfer performance.
256 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash
memory is organized as four 8-Kbyte sectors, one 32-Kbyte sector, and three 64-Kbyte
sectors. Each sector can be separately write protected1), erased and programmed (in
blocks of 128 bytes). The complete Flash area can be read-protected. A password
sequence temporarily unlocks protected areas. The Flash module combines very fast
64-bit one-cycle read accesses with protected and efficient writing algorithms for
programming and erasing. Thus, program execution out of the internal Flash results in
maximum performance. Dynamic error correction provides extremely high read data
security for all read accesses.
For timing characteristics, please refer to Section 4.4.2.
6 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.
4 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data. The DSRAM is accessed via the DMU and is therefore optimized for data
accesses.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, and general purpose register banks. A register
bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7,
1) Each two 8-Kbyte sectors are combined for write-protection purposes.
Data Sheet 18 V1.0, 2005-06

XC164-32
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RH7) so-called General Purpose Registers (GPRs).

The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3 XC164 Memory Map1)

Address Area Start Loc. End Loc. Area Size2) Notes
3)
Flash register space FF’F000H FF’FFFFH 4 Kbytes
Reserved (Acc. trap) FE’0000H FF’EFFFH 60 Kbytes –
Reserved for EPSRAM F8’1800H FD’FFFFH 378 Kbytes –
Emul. Program F8’0000H F8’17FFH 6 Kbytes 2nd way to PSRAM
SRAM4)
Reserved for PSRAM E0’1800H F7’FFFFH < 1.5 Mbytes Minus PSRAM
Program SRAM E0’0000H E0’17FFH 6 Kbytes Maximum
Reserved for program C4’0000H DF’FFFFH < 2 Mbytes Minus Flash
memory
Program Flash C0’0000H C3’FFFFH 256 Kbytes –
Reserved BF’0000H BF’FFFFH 64 Kbytes –
External memory area 40’0000H BE’FFFFH < 8 Mbytes Minus reserved
segment
External IO area5) 20’0800H 3F’FFFFH < 2 Mbytes Minus TwinCAN
TwinCAN registers 20’0000H 20’07FFH 2 Kbytes –
External memory area 01’0000H 1F’FFFFH < 2 Mbytes Minus segment 0
Data RAMs and SFRs 00’8000H 00’FFFFH 32 Kbytes Partly used
External memory area 00’0000H 00’7FFFH 32 Kbytes –
1) Accesses to the shaded areas generate external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) Not defined register locations return a trap code.
4) The Emulation PSRAM (EPSRAM) realizes a 2nd access path to the PSRAM with a different timing.
Data Sheet 19 V1.0, 2005-06

XC164-32
Derivatives
5) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
3.2 External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes1), which
are as follows:
• 16 … 24-bit Addresses, 16-bit Data, Demultiplexed
• 16 … 24-bit Addresses, 16-bit Data, Multiplexed
• 16 … 24-bit Addresses, 8-bit Data, Multiplexed
• 16 … 24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output. The high order address (segment) lines
use Port 4. The number of active segment address lines is selectable, restricting the
external address space to 8 Mbytes … 64 Kbytes. This is required when interface lines
are assigned to Port 4.
Up to 4 external CS signals (3 windows plus default) can be generated in order to save
external glue logic. External modules can directly be connected to the common
address/data bus and their individual select lines.
Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control the access to different resources with different bus
characteristics. These address windows are arranged hierarchically where window 4
overrides window 3, and window 2 overrides window 1. All accesses to locations not
covered by these 4 address windows are controlled by TCONCS0/FCONCS0. The
currently active window can generate a chip select signal.
Note: The chip select signal of address window 4 is not available on a pin.
The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.
The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
The TwinCAN module is connected and accessed via the LXBus.
1) Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet 20 V1.0, 2005-06

XC164-32
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3.3 Central Processing Unit (CPU)

The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
PM U PSRAM
Flash/RO M
CPU
P refetch CSP IP VECSEG 2-S tage

U nit P refetch
CPUCON1 TF R P ipeline
B ranch CPUCON2
5-S tage
U nit Injection/ P ipeline DPRAM
Exception
R etu rn Handler
FIFO
S tack IFU IPIP
ID X 0 QR0 DPP0 SPSEG CP

ID X 1 QR1 DPP1 SP
QX0 DPP2 STKO V RR1515
R 15
QX1 DPP3 STKUN RR1414
R 15 R 14
R 14
+ /- + /- GPRs GPRs
GPRs
ADU GPRs
RR1 1 R1
M u ltip ly MRW D ivisio n U n it B it-M a sk-G e n .
R0
U nit RR0 0R 1
M u ltip ly U n it B a rre l-S h ifte r
R0
MCW MDC
RF
+ /- MSW PSW + /-
MDH MDL
MAH MAL B uffer DSRAM
ZE R O S ONES EBC
M AC ALU WB Peripherals
DM U
m ca04917_x.vsd
Figure 4 CPU Block Diagram

Based on these hardware provisions, most of the XC164’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
Data Sheet 21 V1.0, 2005-06

XC164-32
Derivatives
and rotate instructions are always processed during one machine cycle independent of
the number of bits to be shifted. Also multiplication and most MAC instructions execute
in one single cycle. All multiple-cycle instructions have been optimized so that they can
be executed very fast as well: for example, a division algorithm is performed in 18 to 21
CPU cycles, depending on the data and division type. Four cycles are always visible, the
rest runs in the background. Another pipeline optimization, the branch target prediction,
allows eliminating the execution time of branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 wordwide
GPRs each at its disposal. The global register bank is physically allocated within the on-
chip DPRAM area. A Context Pointer (CP) register determines the base address of the
active global register bank to be accessed by the CPU at any time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter
passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided as a storage for temporary data. The
system stack can be allocated to any location within the address space (preferably in the
on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient XC164 instruction set which includes
the following instruction classes:
• Standard Arithmetic Instructions
• DSP-Oriented Arithmetic Instructions
• Logical Instructions
• Boolean Bit Manipulation Instructions
• Compare and Loop Control Instructions
• Shift and Rotate Instructions
• Prioritize Instruction
• Data Movement Instructions
• System Stack Instructions
• Jump and Call Instructions
• Return Instructions
• System Control Instructions
• Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet 22 V1.0, 2005-06

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3.4 Interrupt System

With an interrupt response time of typically 8 CPU clocks (in case of internal program
execution), the XC164 is capable of reacting very fast to the occurrence of non-
deterministic events.
The architecture of the XC164 supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source, or the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The XC164 has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt nodes. Via its
related register, each node can be programmed to one of sixteen interrupt priority levels.
Once having been accepted by the CPU, an interrupt service can only be interrupted by
a higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt nodes has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge, or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 4 shows all of the possible XC164 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may
be used to generate software controlled interrupt requests by setting the
respective interrupt request bit (xIR).
Data Sheet 23 V1.0, 2005-06

XC164-32
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Table 4 XC164 Interrupt Nodes

Source of Interrupt or PEC Control Vector Trap
Service Request Register Location1) Number
CAPCOM Register 0 CC1_CC0IC xx’0040H 10H / 16D
CAPCOM Register 3 CC1_CC3IC xx’004CH 13H / 19D
CAPCOM Register 7 CC1_CC7IC xx’005CH 17H / 23D
CAPCOM Register 10 CC1_CC10IC xx’0068H 1AH / 26D
CAPCOM Register 11 CC1_CC11IC xx’006CH 1BH / 27D
CAPCOM Register 12 CC1_CC12IC xx’0070H 1CH / 28D
CAPCOM Register 13 CC1_CC13IC xx’0074H 1DH / 29D
CAPCOM Register 14 CC1_CC14IC xx’0078H 1EH / 30D
CAPCOM Register 15 CC1_CC15IC xx’007CH 1FH / 31D
CAPCOM Register 16 CC2_CC16IC xx’00C0H 30H / 48D
CAPCOM Register 19 CC2_CC19IC xx’00CCH 33H / 51D
CAPCOM Register 20 CC2_CC20IC xx’00D0H 34H / 52D
CAPCOM Register 23 CC2_CC23IC xx’00DCH 37H / 55D
CAPCOM Register 24 CC2_CC24IC xx’00E0H 38H / 56D
CAPCOM Register 25 CC2_CC25IC xx’00E4H 39H / 57D
CAPCOM Register 26 CC2_CC26IC xx’00E8H 3AH / 58D
CAPCOM Register 27 CC2_CC27IC xx’00ECH 3BH / 59D
CAPCOM Register 28 CC2_CC28IC xx’00F0H 3CH / 60D
Data Sheet 24 V1.0, 2005-06

XC164-32
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Table 4 XC164 Interrupt Nodes (cont’d)

CAPCOM Timer 0 CC1_T0IC xx’0080H 20H / 32D
CAPCOM Timer 1 CC1_T1IC xx’0084H 21H / 33D
CAPCOM Timer 7 CC2_T7IC xx’00F4H 3DH / 61D
CAPCOM Timer 8 CC2_T8IC xx’00F8H 3EH / 62D
GPT1 Timer 2 GPT12E_T2IC xx’0088H 22H / 34D
GPT1 Timer 3 GPT12E_T3IC xx’008CH 23H / 35D
GPT2 CAPREL Register GPT12E_CRIC xx’009CH 27H / 39D
A/D Conversion Complete ADC_CIC xx’00A0H 28H / 40D
A/D Overrun Error ADC_EIC xx’00A4H 29H / 41D
ASC0 Transmit ASC0_TIC xx’00A8H 2AH / 42D
ASC0 Transmit Buffer ASC0_TBIC xx’011CH 47H / 71D
ASC0 Receive ASC0_RIC xx’00ACH 2BH / 43D
ASC0 Error ASC0_EIC xx’00B0H 2CH / 44D
ASC0 Autobaud ASC0_ABIC xx’017CH 5FH / 95D
SSC0 Transmit SSC0_TIC xx’00B4H 2DH / 45D
SSC0 Receive SSC0_RIC xx’00B8H 2EH / 46D
SSC0 Error SSC0_EIC xx’00BCH 2FH / 47D
PLL/OWD PLLIC xx’010CH 43H / 67D
ASC1 Transmit ASC1_TIC xx’0120H 48H / 72D
ASC1 Transmit Buffer ASC1_TBIC xx’0178H 5EH / 94D
ASC1 Receive ASC1_RIC xx’0124H 49H / 73D
ASC1 Error ASC1_EIC xx’0128H 4AH / 74D
ASC1 Autobaud ASC1_ABIC xx’0108H 42H / 66D
End of PEC Subchannel EOPIC xx’0130H 4CH / 76D
Data Sheet 25 V1.0, 2005-06

XC164-32
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Table 4 XC164 Interrupt Nodes (cont’d)

CAPCOM6 Timer T12 CCU6_T12IC xx’0134H 4DH / 77D
CAPCOM6 Timer T13 CCU6_T13IC xx’0138H 4EH / 78D
CAPCOM6 Emergency CCU6_EIC xx’013CH 4FH / 79D
CAPCOM6 CCU6_IC xx’0140H 50H / 80D
SSC1 Transmit SSC1_TIC xx’0144H 52H / 82D
SSC1 Receive SSC1_RIC xx’0148H 52H / 82D
SSC1 Error SSC1_EIC xx’014CH 53H / 83D
CAN0 CAN_0IC xx’0150H 54H / 84D
CAN3 CAN_3IC xx’015CH 57H / 87D
CAN5 CAN_5IC xx’0168H 5AH / 90D
CAN6 CAN_6IC xx’016CH 5BH / 91D
CAN7 CAN_7IC xx’0170H 5CH / 92D
RTC RTC_IC xx’0174H 5DH / 93D
Unassigned node – xx’0100H 40H / 64D
Unassigned node – xx’012CH 4BH / 75D
Unassigned node – xx’00FCH 3FH / 63D
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet 26 V1.0, 2005-06

XC164-32
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The XC164 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5 Hardware Trap Summary

Exception Condition Trap Trap Vector Trap Trap
1)
Flag Vector Location Number Priority
Reset Functions: –
• Hardware Reset RESET xx’0000H 00H III
• Software Reset RESET xx’0000H 00H III
• Watchdog Timer RESET xx’0000H 00H III
Overflow
Class A Hardware Traps:
• Non-Maskable Interrupt NMI NMITRAP xx’0008H 02H II
• Stack Overflow STKOF STOTRAP xx’0010H 04H II
• Stack Underflow STKUF STUTRAP xx’0018H 06H II
• Software Break SOFTBRK SBRKTRAP xx’0020H 08H II
Class B Hardware Traps:
• Undefined Opcode UNDOPC BTRAP xx’0028H 0AH I
• PMI Access Error PACER BTRAP xx’0028H 0AH I
• Protected Instruction PRTFLT BTRAP xx’0028H 0AH I
Fault
• Illegal Word Operand ILLOPA BTRAP xx’0028H 0AH I
Access
Reserved – – [2CH - 3CH] [0BH - –
0FH]
Software Traps – – Any Any Current
• TRAP Instruction [xx’0000H - [00H - CPU
xx’01FCH] 7FH] Priority
in steps of
4H
1) Register VECSEG defines the segment where the vector table is located to.
Data Sheet 27 V1.0, 2005-06

XC164-32
Derivatives
3.5 On-Chip Debug Support (OCDS)

The On-Chip Debug Support system provides a broad range of debug and emulation
features built into the XC164. The user software running on the XC164 can thus be
debugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,
consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger
controls the OCDS via a set of dedicated registers accessible via the JTAG interface.
Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.
An injection interface allows the execution of OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported as well as the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the JTAG interface or via the external bus interface for
increased performance.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to
communicate with external circuitry. These interface signals are realized as alternate
functions on Port 3 pins.
Complete system emulation is supported by the New Emulation Technology (NET)
interface.
Data Sheet 28 V1.0, 2005-06

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3.6 Capture/Compare Units (CAPCOM1/2)

The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM units are typically used to handle high speed I/O tasks such as
pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for each capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose
capture/compare registers, each of which may be individually allocated to either
CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or
compare function.
12 registers of the CAPCOM2 module have each one port pin associated with it which
serves as an input pin for triggering the capture function, or as an output pin to indicate
the occurrence of a compare event.
Table 6 Compare Modes (CAPCOM1/2)

Compare Modes Function
Mode 0 Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1 Pin toggles on each compare match;
several compare events per timer period are possible
Mode 2 Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
only one compare event per timer period is generated
Double Register Two registers operate on one pin;
Mode pin toggles on each compare match;
several compare events per timer period are possible
Single Event Mode Generates single edges or pulses;
can be used with any compare mode
Data Sheet 29 V1.0, 2005-06

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When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
Data Sheet 30 V1.0, 2005-06

XC164-32
Derivatives
Reload Reg.
T0REL/T7REL
f CC T0/T7
T0IRQ,
T0IN/T7IN Input Timer T0/T7
T7IRQ
T6OUF Control
CCxIO CCxIRQ
CCxIO CCxIRQ
Mode Sixteen
Control 16-bit
(Capture Capture/
or Compare
Compare) Registers
CCxIO CCxIRQ
f CC T1/T8
T1IRQ,
Input Timer T1/T8
T8IRQ
T6OUF Control
Reload Reg.
T1REL/T8REL
CAPCOM1 provides channels x = 0 … 15,

CAPCOM2 provides channels x = 16 … 31.
(see signals CCxIO and CCxIRQ)
MCB05569
Figure 5 CAPCOM1/2 Unit Block Diagram
Data Sheet 31 V1.0, 2005-06

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3.7 The Capture/Compare Unit CAPCOM6

The CAPCOM6 unit supports generation and control of timing sequences on up to three
16-bit capture/compare channels plus one independent 10-bit compare channel.
In compare mode the CAPCOM6 unit provides two output signals per channel which
have inverted polarity and non-overlapping pulse transitions (deadtime control). The
compare channel can generate a single PWM output signal and is further used to
modulate the capture/compare output signals.
In capture mode the contents of compare timer T12 is stored in the capture registers
upon a signal transition at pins CCx.
Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked
by the prescaled system clock.
Mode
Period Register
Select Register Trap Register CTRAP
T12P
CC6MSEL
Offset Register CC Channel 0 CC60

T12OF CC60 COUT60
Prescaler
Control
fCPU CC Channel 1 CC61

Port
Compare CC61 Control COUT61
Timer T12 Logic
16-bit CC Channel 2 CC62
CC62 COUT62
Control Register
CTCON
Prescaler
fCPU Compare
Compare Register
Timer T13 COUT63
CMP13
10-bit
Block CC6POS0
Commutation
CC6POS1
Period Register Control
CC6MCON.H CC6POS2
T13P
MCB04109
The timer registers (T12, T13) are not directly accessible.
The period and offset registers are loading a value into the timer registers.
Figure 6 CAPCOM6 Block Diagram

For motor control applications both subunits may generate versatile multichannel PWM
signals which are basically either controlled by compare timer T12 or by a typical hall
sensor pattern at the interrupt inputs (block commutation).
Data Sheet 32 V1.0, 2005-06

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Derivatives
3.8 General Purpose Timer (GPT12E) Unit

The GPT12E unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the system clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet 33 V1.0, 2005-06

XC164-32
Derivatives
T3CON.BPS1
f GPT 2n:1 Basic Clock

Interrupt
Aux. Timer T2 Request
(T2IRQ)
U/D
T2IN T2
Mode
Reload
T2EUD Control
Capture
Interrupt
Request
(T3IRQ)
T3
T3IN Mode Core Timer T3 T3OTL T3OUT
Control
U/D Toggle
T3EUD Latch
Capture
Reload
T4IN T4
Mode Interrupt
T4EUD Control Aux. Timer T4 Request
(T4IRQ)
U/D
MCA05563
Figure 7 Block Diagram of GPT1

With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
Data Sheet 34 V1.0, 2005-06

XC164-32
Derivatives
count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM1/2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
after the capture procedure. This allows the XC164 to measure absolute time differences
or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
Data Sheet 35 V1.0, 2005-06

XC164-32
Derivatives
T6CON.BPS2
f GPT 2 n:1 Basic Clock

Interrupt
GPT2 Timer T5 Request
(T5IR)
T5
U/D
T5IN Mode
Control
Clear
Capture
CAPIN GPT2 CAPREL

CAPREL Interrupt
Mode Request
T3IN/ Control Reload (CRIR)
T3EUD
Clear Interrupt
Request
(T6IR)
Toggle
FF
GPT2 Timer T6 T6OTL T6OUT
T6
Mode
T6OUF
Control U/D
T6IN
MCA05564
Figure 8 Block Diagram of GPT2
Data Sheet 36 V1.0, 2005-06

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Derivatives
3.9 Real Time Clock

The Real Time Clock (RTC) module of the XC164 is directly clocked via a separate clock
driver with the prescaled on-chip main oscillator frequency (fRTC = fOSCm/32). It is
therefore independent from the selected clock generation mode of the XC164.
The RTC basically consists of a chain of divider blocks:
• a selectable 8:1 divider (on - off)
• the reloadable 16-bit timer T14
• the 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
fRTC
:8 MUX
RTCINT
Interrupt Sub Node
RUN CNT CNT CNT CNT

INT0 INT1 INT2 INT3
PRE
REL-Register
T14REL 10 Bits 6 Bits 6 Bits 10 Bits
fCNT T14 10 Bits 6 Bits 6 Bits 10 Bits
T14-Register CNT-Register
MCB05568
Figure 9 RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
Data Sheet 37 V1.0, 2005-06

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The RTC module can be used for different purposes:

• System clock to determine the current time and date,
optionally during idle mode, sleep mode, and power down mode
• Cyclic time based interrupt, to provide a system time tick independent of CPU
frequency and other resources, e.g. to wake up regularly from idle mode
• 48-bit timer for long term measurements (maximum timespan is > 100 years)
• Alarm interrupt for wake-up on a defined time
Data Sheet 38 V1.0, 2005-06

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Derivatives
3.10 A/D Converter

For analog signal measurement, a 10-bit A/D converter with 14 multiplexed input
channels and a sample and hold circuit has been integrated on-chip. It uses the method
of successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable (in two modes) and can thus be adjusted to the
external circuitry. The A/D converter can also operate in 8-bit conversion mode, where
the conversion time is further reduced.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.
For applications which require less analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converter of the XC164 supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels are sequentially sampled and converted. In the Auto Scan
Continuous mode, the prespecified channels are repeatedly sampled and converted. In
addition, the conversion of a specific channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is called Channel Injection Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).
The Auto-Power-Down feature of the A/D converter minimizes the power consumption
when no conversion is in progress.
Data Sheet 39 V1.0, 2005-06

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Derivatives
3.11 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)

The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial
communication with other microcontrollers, processors, terminals or external peripheral
components. They are upward compatible with the serial ports of the Infineon 8-bit
microcontroller families and support full-duplex asynchronous communication and half-
duplex synchronous communication. A dedicated baud rate generator with a fractional
divider precisely generates all standard baud rates without oscillator tuning. For
transmission, reception, error handling, and baudrate detection 5 separate interrupt
vectors are provided.
In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmitted
or received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake-up bit mode). IrDA data transmissions up to
115.2 kbit/s with fixed or programmable IrDA pulse width are supported.
In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift
clock which is generated by the ASC0/1. The LSB is always shifted first.
In both modes, transmission and reception of data is FIFO-buffered. An autobaud
detection unit allows to detect asynchronous data frames with its baudrate and mode
with automatic initialization of the baudrate generator and the mode control bits.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
Summary of Features
• Full-duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking
– Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz)
– Multiprocessor mode for automatic address/data byte detection
– Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)
– Loop-back capability
– Auto baudrate detection
• Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz)
• Buffered transmitter/receiver with FIFO support (8 entries per direction)
• Loop-back option available for testing purposes
• Interrupt generation on transmitter buffer empty condition, last bit transmitted
condition, receive buffer full condition, error condition (frame, parity, overrun error),
start and end of an autobaud detection
Data Sheet 40 V1.0, 2005-06

XC164-32
Derivatives
3.12 High Speed Synchronous Serial Channels (SSC0/SSC1)

The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half-
duplex synchronous communication. It may be configured so it interfaces with serially
linked peripheral components, full SPI functionality is supported.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling three separate interrupt
vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit error and receive error supervise the correct
handling of the data buffer. Phase error and baudrate error detect incorrect serial data.
Summary of Features
• Master or Slave mode operation
• Full-duplex or Half-duplex transfers
• Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz)
• Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB-first or MSB-first
– Programmable clock polarity: idle low or idle high
– Programmable clock/data phase: data shift with leading or trailing clock edge
• Loop back option available for testing purposes
• Interrupt generation on transmitter buffer empty condition, receive buffer full
condition, error condition (receive, phase, baudrate, transmit error)
• Three pin interface with flexible SSC pin configuration
Data Sheet 41 V1.0, 2005-06

XC164-32
Derivatives
3.13 TwinCAN Module

The integrated TwinCAN module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
Two Full-CAN nodes share the TwinCAN module’s resources to optimize the CAN bus
traffic handling and to minimize the CPU load. The module provides up to 32 message
objects, which can be assigned to one of the CAN nodes and can be combined to FIFO-
structures. Each object provides separate masks for acceptance filtering.
The flexible combination of Full-CAN functionality and FIFO architecture reduces the
efforts to fulfill the real-time requirements of complex embedded control applications.
Improved CAN bus monitoring functionality as well as the number of message objects
permit precise and comfortable CAN bus traffic handling.
Gateway functionality allows automatic data exchange between two separate CAN bus
systems, which reduces CPU load and improves the real time behavior of the entire
system.
The bit timing for both CAN nodes is derived from the master clock and is programmable
up to a data rate of 1 Mbit/s. Each CAN node uses two pins of Port 4, Port 7, or Port 9 to
interface to an external bus transceiver. The interface pins are assigned via software.
TwinCAN Module Kernel

fCAN TxDCA
Clock CAN CAN
Control Node A Node B RxDCA
Port
Address Message Control
Decoder Object
Buffer TxDCB
Interrupt RxDCB
Control TwinCAN Control
MCB05567
Figure 10 TwinCAN Module Block Diagram
Data Sheet 42 V1.0, 2005-06

XC164-32
Derivatives
Summary of Features
• CAN functionality according to CAN specification V2.0 B active
• Data transfer rate up to 1 Mbit/s
• Flexible and powerful message transfer control and error handling capabilities
• Full-CAN functionality and Basic CAN functionality for each message object
• 32 flexible message objects
– Assignment to one of the two CAN nodes
– Configuration as transmit object or receive object
– Concatenation to a 2-, 4-, 8-, 16-, or 32-message buffer with FIFO algorithm
– Handling of frames with 11-bit or 29-bit identifiers
– Individual programmable acceptance mask register for filtering for each object
– Monitoring via a frame counter
– Configuration for Remote Monitoring Mode
• Up to eight individually programmable interrupt nodes can be used
• CAN Analyzer Mode for bus monitoring is implemented
Note: When a CAN node has the interface lines assigned to Port 4, the segment address
output on Port 4 must be limited. CS lines can be used to increase the total amount
of addressable external memory.
Data Sheet 43 V1.0, 2005-06

XC164-32
Derivatives
3.14 Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
until the EINIT instruction has been executed (compatible mode), or it can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT (enhanced
mode). Thus, the chip’s start-up procedure is always monitored. The software has to be
designed to restart the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by
2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between
13 µs and 419 ms can be monitored (@ 40 MHz).
The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).
Data Sheet 44 V1.0, 2005-06

XC164-32
Derivatives
3.15 Clock Generation

The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC164 with high flexibility. The master clock fMC is
the reference clock signal, and is used for TwinCAN and is output to the external system.
The CPU clock fCPU and the system clock fSYS are derived from the master clock either
directly (1:1) or via a 2:1 prescaler (fSYS = fCPU = fMC / 2). See also Section 4.4.1.
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
Note: At the end of an external reset (EA = ‘0’) the oscillator watchdog may be disabled
via hardware by (externally) pulling the RD line low upon a reset, similar to the
standard reset configuration.
3.16 Parallel Ports

The XC164 provides up to 79 I/O lines which are organized into six input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of some I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs (except for pin RSTOUT).
The edge characteristics (shape) and driver characteristics (output current) of the port
drivers can be selected via registers POCONx.
The input threshold of some ports is selectable (TTL or CMOS like), where the special
CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The
input threshold may be selected individually for each byte of the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
Data Sheet 45 V1.0, 2005-06

XC164-32
Derivatives
Table 7 Summary of the XC164’s Parallel Ports

Port Control Alternate Functions
PORT0 Pad drivers Address/Data lines or data lines1)
PORT1 Pad drivers Address lines2)
Capture inputs or compare outputs,
Serial interface lines
Port 3 Pad drivers, Timer control signals, serial interface lines,
Open drain, Optional bus control signal BHE/WRH,
Input threshold System clock output CLKOUT (or FOUT)
Port 4 Pad drivers, Segment address lines3), CS signal lines
Open drain, CAN interface lines4)
Input threshold
Port 5 – Analog input channels to the A/D converter,
Timer control signals
Port 9 Pad drivers, Capture inputs or compare outputs
Open drain, CAN interface lines4)
Input threshold
Port 20 Pad drivers, Bus control signals RD, WR/WRL, ALE,
Open drain External access enable pin EA,
Reset indication output RSTOUT
1) For multiplexed bus cycles.
2) For demultiplexed bus cycles.
3) For more than 64 Kbytes of external resources.
4) Can be assigned by software.
Data Sheet 46 V1.0, 2005-06

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3.17 Power Management

The XC164 provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):
• Power Saving Modes switch the XC164 into a special operating mode (control via
instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.
• Clock Generation Management controls the distribution and the frequency of
internal and external clock signals. While the clock signals for currently inactive parts
of logic are disabled automatically, the user can reduce the XC164’s CPU clock
frequency which drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output FOUT.
• Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3). Each peripheral can separately be disabled/enabled.
The on-chip RTC supports intermittent operation of the XC164 by generating cyclic
wake-up signals. This offers full performance to quickly react on action requests while
the intermittent sleep phases greatly reduce the average power consumption of the
system.
Data Sheet 47 V1.0, 2005-06

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3.18 Instruction Set Summary

Table 8 lists the instructions of the XC164 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 8 Instruction Set Summary

Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2/4
ADDC(B) Add word (byte) operands with Carry 2/4
SUB(B) Subtract word (byte) operands 2/4
SUBC(B) Subtract word (byte) operands with Carry 2/4
MUL(U) (Un)Signed multiply direct GPR by direct GPR 2
(16- × 16-bit)
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2/4
(X)OR(B) Bitwise (exclusive) OR, (word/byte operands) 2/4
BCLR/BSET Clear/Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/BFLDL Bitwise modify masked high/low byte of bit-addressable 4
direct word memory with immediate data
CMP(B) Compare word (byte) operands 2/4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4
PRIOR Determine number of shift cycles to normalize direct 2
word GPR and store result in direct word GPR
SHL/SHR Shift left/right direct word GPR 2
ROL/ROR Rotate left/right direct word GPR 2
Data Sheet 48 V1.0, 2005-06

XC164-32
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Table 8 Instruction Set Summary (cont’d)

ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2/4
MOVBS/Z Move byte operand to word op. with sign/zero extension 2/4
JMPA/I/R Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
JB(C) Jump relative if direct bit is set (and clear bit) 4
JNB(S) Jump relative if direct bit is not set (and set bit) 4
CALLA/I/R Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call 4
absolute subroutine
TRAP Call interrupt service routine via immediate trap number 2
PUSH/POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update 4
register with word operand
RET(P) Return from intra-segment subroutine 2
(and pop direct word register from system stack)
RETS Return from inter-segment subroutine 2
RETI Return from interrupt service subroutine 2
SBRK Software Break 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT/ENWDT Disable/Enable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2/4
EXTS(R) Begin EXTended Segment (and Register) sequence 2/4
NOP Null operation 2
Data Sheet 49 V1.0, 2005-06

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Table 8 Instruction Set Summary (cont’d)

CoMUL/CoMAC Multiply (and accumulate) 4
CoADD/CoSUB Add/Subtract 4
Co(A)SHR/CoSHL (Arithmetic) Shift right/Shift left 4
CoLOAD/STORE Load accumulator/Store MAC register 4
CoCMP/MAX/MIN Compare (maximum/minimum) 4
CoABS/CoRND Absolute value/Round accumulator 4
CoMOV/NEG/NOP Data move/Negate accumulator/Null operation 4
Data Sheet 50 V1.0, 2005-06

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Derivatives
Electrical Parameters
4 Electrical Parameters
4.1 General Parameters
Table 9 Absolute Maximum Ratings

Parameter Symbol Limit Values Unit Notes
Min. Max.
Storage temperature TST -65 150 °C –
Junction temperature TJ -40 150 °C under bias
Voltage on VDDI pins with VDDI -0.5 3.25 V –
respect to ground (VSS)
Voltage on VDDP pins with VDDP -0.5 6.2 V –
respect to ground (VSS)
Voltage on any pin with VIN -0.5 VDDP + V –
respect to ground (VSS) 0.5
Input current on any pin – -10 10 mA –
during overload condition
Absolute sum of all input – – |100| mA –
currents during overload
condition
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet 51 V1.0, 2005-06

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Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XC164. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Table 10 Operating Condition Parameters

Min. Max.
Digital supply voltage for VDDI 2.35 2.7 V Active mode,
the core fCPU = fCPUmax1)2)
Digital supply voltage for VDDP 4.4 5.5 V Active mode2)3)
IO pads
Supply Voltage Difference ∆VDD -0.5 – V VDDP - VDDI4)
Digital ground voltage VSS 0 V Reference voltage
Overload current IOV -5 5 mA Per IO pin5)6)
-2 5 mA Per analog input
pin5)6)
Overload current coupling KOVA – 1.0 × 10-4 – IOV > 0
factor for analog inputs7) – 1.5 × 10-3 – IOV < 0
Overload current coupling KOVD – 5.0 × 10-3 – IOV > 0
factor for digital I/O pins7) – 1.0 × 10-2 – IOV < 0
6)
Absolute sum of overload Σ|IOV| – 50 mA
currents
External Load CL – 50 pF Pin drivers in
Capacitance default mode8)
Ambient temperature TA 0 70 °C SAB-XC164…
-40 85 °C SAF-XC164…
-40 125 °C SAK-XC164…
1) fCPUmax = 40 MHz for devices marked … 40F, fCPUmax = 20 MHz for devices marked … 20F.
2) External circuitry must guarantee low-level at the RSTIN pin at least until both power supply voltages have
reached the operating range.
3) The specified voltage range is allowed for operation. The range limits may be reached under extreme
operating conditions. However, specified parameters, such as leakage currents, refer to the standard
operating voltage range of VDDP = 4.75 V to 5.25 V.
4) This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down,
and power-save modes.
Data Sheet 52 V1.0, 2005-06

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5) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VDDP + 0.5 V (IOV > 0) or VOV < VSS - 0.5 V (IOV < 0). The absolute sum of
input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the
specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
6) Not subject to production test - verified by design/characterization.
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.
The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the input
voltage on analog inputs.
8) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the XC164
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the XC164 will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
XC164.
Data Sheet 53 V1.0, 2005-06

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4.2 DC Parameters
Table 11 DC Characteristics (Operating Conditions apply)1)

Parameter Symbol Limit Values Unit Test Condition
Min. Max.
Input low voltage TTL VIL SR -0.5 0.2 × VDDP V –
(all except XTAL1) - 0.1
Input low voltage VILC SR -0.5 0.3 × VDDI V –
XTAL1
2)
Input low voltage VILS SR -0.5 0.45 × V
(Special Threshold) VDDP
Input high voltage TTL VIH SR 0.2 × VDDP VDDP + 0.5 V –
(all except XTAL1) + 0.9
Input high voltage VIHC SR 0.7 × VDDI VDDI + 0.5 V –
XTAL1
2)
Input high voltage VIHS SR 0.8 × VDDP VDDP + 0.5 V
(Special Threshold) - 0.2
Input Hysteresis HYS 0.04 × – V VDDP in [V],
(Special Threshold) VDDP Series resis-
tance = 0 Ω2)
Output low voltage VOL CC – 1.0 V IOL ≤ IOLmax3)
– 0.45 V IOL ≤ IOLnom3)4)
5)
Output high voltage VOH CC VDDP - 1.0 – V IOH ≥ IOHmax3)
VDDP - – V IOH ≥ IOHnom3)4)
0.45
Input leakage current IOZ1 CC – ±300 nA 0 V < VIN < VDDP,
(Port 5)6) TA ≤ 125 °C
±200 nA 0 V < VIN < VDDP,
TA ≤ 85 °C12)
Input leakage current IOZ2 CC – ±500 nA 0.45 V < VIN <
(all other)6) VDDP
Configuration pull-up ICPUH8) – -10 µA VIN = VIHmin
current7) ICPUL9) -100 – µA VIN = VILmax
Configuration pull- ICPDL8) – 10 µA VIN = VILmax
down current10) ICPDH9) 120 – µA VIN = VIHmin
Data Sheet 54 V1.0, 2005-06

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Table 11 DC Characteristics (Operating Conditions apply)1) (cont’d)

Parameter Symbol Limit Values Unit Test Condition
Min. Max.
Level inactive hold ILHI8) – -10 µA VOUT = 0.5 ×
current11) VDDP
Level active hold ILHA9) -100 – µA VOUT = 0.45 V
current11)
XTAL1 input current IIL CC – ±20 µA 0 V < VIN < VDDI
Pin capacitance12) CIO CC – 10 pF –
(digital inputs/outputs)
1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV.
2) This parameter is tested for P3, P4, P9.
3) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Table 12, Current Limits for Port Output Drivers. The limit for pin groups must be respected.
4) As a rule, with decreasing output current the output levels approach the respective supply level (VOL → VSS,
VOH → VDDP). However, only the levels for nominal output currents are guaranteed.
5) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
6) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV.
7) This specification is valid during Reset for configuration on RD, WR, EA, PORT0
8) The maximum current may be drawn while the respective signal line remains inactive.
9) The minimum current must be drawn to drive the respective signal line active.
10) This specification is valid during Reset for configuration on ALE.
11) This specification is valid during Reset for pins P4.3-0, which can act as CS outputs, and for P3.12.
Data Sheet 55 V1.0, 2005-06

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Table 12 Current Limits for Port Output Drivers

Port Output Driver Maximum Output Current Nominal Output Current
Mode (IOLmax, -IOHmax)1) (IOLnom, -IOHnom)
Strong driver 10 mA 2.5 mA
Medium driver 4.0 mA 1.0 mA
Weak driver 0.5 mA 0.1 mA
1) An output current above |IOXnom| may be drawn from up to three pins at the same time.
For any group of 16 neighboring port output pins the total output current in each direction (ΣIOL and Σ-IOH) must
remain below 50 mA.
Table 13 Power Consumption XC164 (Operating Conditions apply)

Parameter Sym- Limit Values Unit Test Condition
bol Min. Max.
Power supply current (active) IDDI – 10 + mA fCPU in [MHz]1)2)
with all peripherals active 3.0 × fCPU
3)
Pad supply current IDDP – 5 mA
Idle mode supply current IIDX – 10 + mA fCPU in [MHz]2)
with all peripherals active 1.3 × fCPU
Sleep and Power down mode IPDL5) – 128,000 mA VDDI = VDDImax6)
supply current caused by × e-α TJ in [°C]
leakage4) α=
4670 / (273 + TJ)
Sleep and Power down mode IPDM7) – 0.6 + mA VDDI = VDDImax
supply current caused by 0.02 × fOSC fOSC in [MHz]
leakage and the RTC running, + IPDL
clocked by the main oscillator4)
1) During Flash programming or erase operations the supply current is increased by max. 5 mA.
2) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 11.
These parameters are tested at VDDImax and maximum CPU clock frequency with all outputs disconnected and
all inputs at VIL or VIH.
3) The pad supply voltage pins (VDDP) mainly provides the current consumed by the pin output drivers. A small
amount of current is consumed even though no outputs are driven, because the drivers’ input stages are
switched and also the Flash module draws some power from the VDDP supply.
4) The total supply current in Sleep and Power down mode is the sum of the temperature dependent leakage
current and the frequency dependent current for RTC and main oscillator (if active).
5) This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the
junction temperature (see Figure 13). The junction temperature TJ is the same as the ambient temperature TA
if no current flows through the port output drivers. Otherwise, the resulting temperature difference must be
taken into account.
Data Sheet 56 V1.0, 2005-06

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6) All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP, all outputs (including
pins configured as outputs) disconnected. This parameter is tested at 25 °C and is valid for TJ ≥ 25 °C.
7) This parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (see
Figure 12). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The
given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.
Data Sheet 57 V1.0, 2005-06

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I [mA]
IDDImax
140
IDDItyp
120
100
80
IIDXmax
60 IIDXtyp
40
20
10 20 30 40 fCPU [MHz]
Figure 11 Supply/Idle Current as a Function of Operating Frequency
Data Sheet 58 V1.0, 2005-06

XC164-32
Derivatives
I [mA]
3.0
2.0
1.0 IPDMmax
IPDMtyp
0.1
4 8 12 16 fOSC [MHz]
Figure 12 Sleep and Power Down Supply Current due to RTC and Oscillator
Running, as a Function of Oscillator Frequency
IPDO
[mA]
1.5
1.0
0.5
-50 0 50 100 150 TJ [°C]
Figure 13 Sleep and Power Down Leakage Supply Current as a Function of

Temperature
Data Sheet 59 V1.0, 2005-06

XC164-32
Derivatives
4.3 Analog/Digital Converter Parameters
Table 14 A/D Converter Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test
Min. Max. Condition
1)
Analog reference supply VAREF SR 4.5 VDDP V
+ 0.1
Analog reference ground VAGND SR VSS - 0.1 VSS + 0.1 V –
2)
Analog input voltage range VAIN SR VAGND VAREF V
3)
Basic clock frequency fBC 0.5 20 MHz
Conversion time for 10-bit tC10P CC 52 × tBC + tS + 6 × tSYS – Post-calibr. on
result4) tC10 CC 40 × tBC + tS + 6 × tSYS – Post-calibr. off
Conversion time for 8-bit tC8P CC 44 × tBC + tS + 6 × tSYS – Post-calibr. on
result4) tC8 CC 32 × tBC + tS + 6 × tSYS – Post-calibr. off
5)
Calibration time after reset tCAL CC 484 11,696 tBC
1)
Total unadjusted error TUE CC – ±2 LSB
6)
Total capacitance CAINT CC – 15 pF
of an analog input
6)
Switched capacitance CAINS CC – 10 pF
of an analog input
6)
Resistance of RAIN CC – 2 kΩ
the analog input path
6)
Total capacitance CAREFT CC – 20 pF
of the reference input
6)
Switched capacitance CAREFS CC – 15 pF
of the reference input
6)
Resistance of RAREF CC – 1 kΩ
the reference input path
1) TUE is tested at VAREF = VDDP + 0.1 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage range.
If the analog reference supply voltage drops below 4.5 V (i.e. VAREF ≥ 4.0 V) or exceeds the power supply
voltage by up to 0.2 V (i.e. VAREF = VDDP + 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not
subject to production test.
The specified TUE is guaranteed only, if the absolute sum of input overload currents on Port 5 pins (see IOV
specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the respective period of
time. During the reset calibration sequence the maximum TUE may be ±4 LSB.
2) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
Data Sheet 60 V1.0, 2005-06

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3) The limit values for fBC must not be exceeded when selecting the peripheral frequency and the ADCTC setting.
4) This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result (tSYS = 1/fSYS).
Values for the basic clock tBC depend on programming and can be taken from Table 15.
When the post-calibration is switched off, the conversion time is reduced by 12 x tBC.
5) The actual duration of the reset calibration depends on the noise on the reference signal. Conversions
executed during the reset calibration increase the calibration time. The TUE for those conversions may be
increased.
The given parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) reduced values can be used for calculations. At room temperature and nominal
supply voltage the following typical values can be used:
CAINTtyp = 12 pF, CAINStyp = 7 pF, RAINtyp = 1.5 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 13 pF, RAREFtyp = 0.7 kΩ.
A/D Converter
RSource R AIN, On
V AIN C Ext C AINT - C AINS CAINS
MCS05570
Figure 14 Equivalent Circuitry for Analog Inputs
Data Sheet 61 V1.0, 2005-06

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Sample time and conversion time of the XC164’s A/D Converter are programmable. In
compatibility mode, the above timing can be calculated using Table 15.
The limit values for fBC must not be exceeded when selecting ADCTC.
Table 15 A/D Converter Computation Table1)

ADCON.15|14 A/D Converter ADCON.13|12 Sample Time
(ADCTC) Basic Clock fBC (ADSTC) tS
00 fSYS / 4 00 tBC × 8
01 fSYS / 2 01 tBC × 16
10 fSYS / 16 10 tBC × 32
11 fSYS / 8 11 tBC × 64
1) These selections are available in compatibility mode. An improved mechanism to control the ADC input clock
can be selected.
Converter Timing Example:
Assumptions: fSYS = 40 MHz (i.e. tSYS = 25 ns), ADCTC = ‘01’, ADSTC = ‘00’
Basic clock fBC = fSYS / 2 = 20 MHz, i.e. tBC = 50 ns
Sample time tS = tBC × 8 = 400 ns
Conversion 10-bit:
With post-calibr. tC10P = 52 × tBC + tS + 6 × tSYS = (2600 + 400 + 150) ns = 3.15 µs
Post-calibr. off tC10 = 40 × tBC + tS + 6 × tSYS = (2000 + 400 + 150) ns = 2.55 µs
Conversion 8-bit:
With post-calibr. tC8P = 44 × tBC + tS + 6 × tSYS = (2200 + 400 + 150) ns = 2.75 µs
Post-calibr. off tC8 = 32 × tBC + tS + 6 × tSYS = (1600 + 400 + 150) ns = 2.15 µs
Data Sheet 62 V1.0, 2005-06

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4.4 AC Parameters
4.4.1 Definition of Internal Timing

The internal operation of the XC164 is controlled by the internal master clock fMC.
The master clock signal fMC can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate fMC.
This influence must be regarded when calculating the timings for the XC164.
Phase Locked Loop Operation (1:N)
f OSC
f MC
TCM
Direct Clock Drive (1:1)
f OSC
f MC
TCM
Prescaler Operation (N:1)
f OSC
f MC
TCM
MCT05555
Figure 15 Generation Mechanisms for the Master Clock

Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
Data Sheet 63 V1.0, 2005-06

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Derivatives
CPU and EBC are clocked with the CPU clock signal fCPU. The CPU clock can have the
same frequency as the master clock (fCPU = fMC) or can be the master clock divided by
two: fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal fSYS which has the same
frequency as the CPU clock signal fCPU.
Bypass Operation
When bypass operation is configured (PLLCTRL = 0xB) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
fMC = fOSC / ((PLLIDIV+1) × (PLLODIV+1)).
If both divider factors are selected as ‘1’ (PLLIDIV = PLLODIV = ‘0’) the frequency of fMC
directly follows the frequency of fOSC so the high and low time of fMC is defined by the duty
cycle of the input clock fOSC.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
fMC = fOSC / ((3 + 1) × (14 + 1)) = fOSC / 60.
Phase Locked Loop (PLL)

When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor, and
the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so it
is locked to fOSC. The slight variation causes a jitter of fMC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from
fMC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and Figure 16).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
Data Sheet 64 V1.0, 2005-06

XC164-32
Derivatives
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal fMC. Therefore,
the number of VCO cycles can be represented as K × N, where N is the number of
consecutive fMC cycles (TCM).
For a period of N × TCM the accumulated PLL jitter is defined by the deviation DN:
DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods the K × N = 95 value can be
used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)).
Acc. jitter DN K = 12 K=8

ns K = 15 K = 10 K=6 K=5
±8
±7
±6
±5 10 MHz
20 MHz
±4
±3
±2
40 MHz
±1
0
0 1 5 10 15 20 25 N
MCD05566
Figure 16 Approximated Accumulated PLL Jitter

Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
Data Sheet 65 V1.0, 2005-06

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Table 16 VCO Bands for PLL Operation1)

PLLCON.PLLVB VCO Frequency Range Base Frequency Range
00 100 … 150 MHz 20 … 80 MHz
01 150 … 200 MHz 40 … 130 MHz
10 200 … 250 MHz 60 … 180 MHz
11 Reserved
Data Sheet 66 V1.0, 2005-06

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4.4.2 On-chip Flash Operation

The XC164’s Flash module delivers data within a fixed access time (see Table 17).
Accesses to the Flash module are controlled by the PMI and take 1 + WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time tACC of the Flash array. Therefore, the required Flash waitstates depend on the
available speed grade as well as on the actual system frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
Table 17 Flash Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit
Min. Typ. Max.
Flash module access time (Standard) tACC CC – – 701) ns
Flash module access time (Grade A) tACC CC – – 501) ns
2)
Programming time per 128-byte block tPR CC – 2 5 ms
2)
Erase time per sector tER CC – 200 500 ms
1) The actual access time is also influenced by the system frequency, so the frequency ranges are not fully linear.
See Table 18.
2) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), Standard devices
must be operated with 2 waitstates: ((2 + 1) × 25 ns) ≥ 70 ns.
Grade A devices can be operated with 1 waitstate: ((1 + 1) × 25 ns) ≥ 50 ns.
Table 18 indicates the interrelation of waitstates, system frequency, and speed grade.
Table 18 Flash Access Waitstates

Required Waitstates Frequency Range for Frequency Range for
Standard Flash Speed Flash Speed Grade A
0 WS (WSFLASH = 00B) fCPU ≤ 16 MHz fCPU ≤ 20 MHz
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative, i.e. 40 MHz (or 20 MHz for xxx-32F20F devices).
Data Sheet 67 V1.0, 2005-06

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4.4.3 External Clock Drive XTAL1
Table 19 External Clock Drive Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit
Min. Max.
Oscillator period tOSC SR 25 2501) ns
High time2) t1 SR 6 – ns
Low time2) t2 SR 6 – ns
Rise time2) t3 SR – 8 ns
Fall time2) t4 SR – 8 ns
1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.
2) The clock input signal must reach the defined levels VILC and VIHC.
t1 t3 t4
0.5 V DDI V IHC

V ILC
t2
t OSC
MCT05572
Figure 17 External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the
oscillator frequency is limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimum
parameters for the oscillator operation. Please refer to the limits specified by the
crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not subject to production test).
Data Sheet 68 V1.0, 2005-06

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4.4.4 Testing Waveforms
Output delay Output delay
Hold time Hold time
2.0 V
Input Signal
(driven by tester)
Output Signal
(measured)
0.8 V
0.45 V
Output timings refer to the rising edge of CLKOUT.

Input timings are calculated from the time, when the input signal reaches
VIH or VIL, respectively.
MCD05556
Figure 18 Input Output Waveforms
VLoad + 0.1 V V OH - 0.1 V

Timing
Reference
Points
V Load - 0.1 V V OL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV

change from load voltage occurs, but begins to float when a 100 mV
change from the loaded V OH /V OL level occurs (IOH / IOL = 20 mA).
MCA05565
Figure 19 Float Waveforms
Data Sheet 69 V1.0, 2005-06

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4.4.5 External Bus Timing
Table 20 CLKOUT Reference Signal

Parameter Symbol Limits Unit
Min. Max.
CLKOUT cycle time tc5 CC 40/30/251) ns
CLKOUT high time tc6 CC 8 – ns
CLKOUT low time tc7 CC 6 – ns
CLKOUT rise time tc8 CC – 4 ns
CLKOUT fall time tc9 CC – 4 ns
1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 25/33/40 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
t C9
t C5 tC6 t C7 tC8
CLKOUT
MCT05571
Figure 20 CLKOUT Signal Timing
Data Sheet 70 V1.0, 2005-06

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Variable Memory Cycles

External bus cycles of the XC164 are executed in five subsequent cycle phases (AB, C,
D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
This table provides a summary of the phases and the respective choices for their
duration.
Table 21 Programmable Bus Cycle Phases (see timing diagrams)

Bus Cycle Phase Parameter Valid Values Unit
Address setup phase, the standard duration of this tpAB 1 … 2 (5) TCP
phase (1 … 2 TCP) can be extended by 0 … 3 TCP
if the address window is changed
Command delay phase tpC 0…3 TCP
Write Data setup/MUX Tristate phase tpD 0…1 TCP
Access phase tpE 1 … 32 TCP
Address/Write Data hold phase tpF 0…3 TCP
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Data Sheet 71 V1.0, 2005-06

XC164-32
Derivatives
Table 22 External Bus Cycle Timing (Operating Conditions apply)

Parameter Symbol Limits Unit
Min. Max.
Output valid delay for: tc10 CC 1 15 ns
RD, WR(L/H)
Output valid delay for: tc11 CC -1 8 ns
BHE, ALE
A23 … A16, A15 … A0 (on PORT1)
A15 … A0 (on PORT0)
CS
D15 … D0 (write data, MUX-mode)
D15 … D0 (write data, DEMUX-mode)
Output hold time for: tc20 CC -3 4 ns
RD, WR(L/H)
Output hold time for: tc21 CC 0 11 ns
BHE, ALE
A23 … A16, A15 … A0 (on PORT0)
Output hold time for: tc24 CC -2 4 ns
CS
D15 … D0 (write data)
Input setup time for: tc30 SR 29 – ns
D15 … D0 (read data)
Input hold time tc31 SR -5 – ns
D15 … D0 (read data)1)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
Note: The shaded parameters have been verified by characterization.

They are not subject to production test.
Data Sheet 72 V1.0, 2005-06

XC164-32
Derivatives
tp AB tpC tp D tp E tp F
CLKOUT
tc 21
tc 11
ALE
tc 11/tc 14
A23-A16,
High Address
BHE, CSx
tc 20
tc 10
RD
WR(L/H)
tc 31
tc 13 tc 23 tc 30
AD15-AD0
Low Address Data In
(read)
tc 13 tc 15 tc 25
AD15-AD0
Low Address Data Out
(write)
MCT05557
Figure 21 Multiplexed Bus Cycle
Data Sheet 73 V1.0, 2005-06

XC164-32
Derivatives
tp AB tp C tp D tp E tp F
CLKOUT
tc 21
tc 11
ALE
tc 11 /tc 14
A23-A0,
Address
BHE, CSx
tc 20
tc 10
RD
WR(L/H)
tc 31
tc 30
D15-D0
Data In
(read)
tc 16 tc 25
D15-D0
Data Out
(write)
MCT05558
Figure 22 Demultiplexed Bus Cycle
Data Sheet 74 V1.0, 2005-06

XC164-32
Derivatives
Package and Reliability
5 Package and Reliability
5.1 Packaging
Table 23 Package Parameters (P-TQFP-100-16)

Min. Max.
Power dissipation PDISS – 0.8 W –
Thermal resistance RTHA – 29 K/W Chip-Ambient
Package Outlines
1.6 MAX.
0.1 ±0.05
1.4 ±0.05
0.15 +0.05
-0.06
7˚ MAX.
H
0.5 0.6 ±0.15

12
C
1)
0.08
0.22 ±0.05
0.08 M A-B D C 100x
16
14 1) 0.2 A-B D 100x
D 0.2 A-B D H 4x
A B
14 1)
16
100
1
Index Marking
1)
Does not include plastic or metal protrusion of 0.25 max. per side
2)
Does not include dambar protrusion of 0.08 max. per side at max. material condition
GPP09189
Figure 23 P-TQFP-100-16 (Plastic Thin Quad Flat Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm
Data Sheet 75 V1.0, 2005-06

XC164-32
Derivatives
5.2 Flash Memory Parameters

The data retention time of the XC164’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Table 24 Flash Parameters (XC164, 256 Kbytes)

Min. Max.
Data retention time tRET 15 – years Max. 103
erase/program
cycles
Flash Erase Endurance NER 20 × 103 – – Max. data
retention time
5 years
Data Sheet 76 V1.0, 2005-06

XC164-32
Derivatives
5.3 Quality Declarations
Table 25 Quality Parameters

Min. Max.
ESD susceptibility VHBM – 2000 V Conforming to
according to Human EIA/JESD22-
Body Model (HBM) A114-B
ESD susceptibility VSDM – 500 V Conforming to
according to Socketed ESDA Std DS5.3-
Device Model (SDM) 1993
Moisture Sensitivity – – 3 – Conforming to
Level (MSL) Jedec J-STD-
020C for 240 °C
Note: Information about soldering can be found on the “package” information page
under: http://www.infineon.com/products.
Data Sheet 77 V1.0, 2005-06

w w w . i n f i n e o n . c o m
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Data Sheet, V1.

Revision History: 2005-06 V1.0

We Listen to Your Comments

Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15

Data Sheet 3 V1.0, 2005-06

Data Sheet 4 V1.0, 2005-06

• Up to 12 Mbytes External Address Space for Code and Data

Data Sheet 5 V1.0, 2005-06

Table 1 XC164 Derivative Synopsis

Data Sheet 6 V1.0, 2005-06

2 General Device Information

TRST JTAG Debug

Figure 1 Logic Symbol

Data Sheet 7 V1.0, 2005-06

2.2 Pin Configuration and Definition

Figure 2 Pin Configuration (top view)

Data Sheet 8 V1.0, 2005-06

Table 2 Pin Definitions and Functions

Data Sheet 9 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 10 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 11 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 12 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 13 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 14 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 15 V1.0, 2005-06

Table 2 Pin Definitions and Functions (cont’d)

Data Sheet 16 V1.0, 2005-06

PSRAM DPRAM DSRAM

C166SV2 - Core Control

8-Bit/ USART USARTSPI SPI CAN

P 20 P 9 Port 5 Port 4 Port 3 PORT1 PORT0

Figure 3 Block Diagram

Data Sheet 17 V1.0, 2005-06

3.1 Memory Subsystem and Organization

1) Each two 8-Kbyte sectors are combined for write-protection purposes.

Data Sheet 18 V1.0, 2005-06

RH7) so-called General Purpose Registers (GPRs).

Table 3 XC164 Memory Map1)

Data Sheet 19 V1.0, 2005-06

3.2 External Bus Controller

Data Sheet 20 V1.0, 2005-06

3.3 Central Processing Unit (CPU)

P refetch CSP IP VECSEG 2-S tage

ID X 0 QR0 DPP0 SPSEG CP

Figure 4 CPU Block Diagram

Data Sheet 21 V1.0, 2005-06

Data Sheet 22 V1.0, 2005-06

3.4 Interrupt System

Data Sheet 23 V1.0, 2005-06

Table 4 XC164 Interrupt Nodes

Data Sheet 24 V1.0, 2005-06

Table 4 XC164 Interrupt Nodes (cont’d)

Data Sheet 25 V1.0, 2005-06