DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DIGITAL VLSI DESIGN

Experiential Learning Report

Submitted by,

Narendra Babu B V USN: 1RV21EC108

Pranav Kumar USN: 1RV21EC123
Rohan K Loni USN: 1RV21EC136
Naram Vimlaesh USN: 1RV21EC107

Under the guidance of

Dr. Shilpa D R
Assistant Professor,
Dept. of ECE
RV College of Engineering

In partial fulfillment of the requirements for the degree of

BACHELOR OF ENGINEERING
in
ELECTRONICS AND COMMUNICATION ENGINEERING
2023-2024
 CONTENTS

1. Problem Statement
2. Introduction
3. Design Process
4. Component Used
5. Implementation
6. Conclusion
 Page | 2

1.Problem Statement
 Problem Statement
Design a digital bank token number display system that generates sequential token
numbers for a bank, starting from 00 and incrementing up to 16. The system should display
the current token number on a seven-segment display in Binary Coded Decimal (BCD)
format. The design should incorporate the following components:
1) 3 Input Or Gate
2) 1 D Positive edge flipflop(Register Counter)
3) 3 D Negative edge flipflop(Register Counter)
4) 1 Full Adder
5) 3 Enable Pins
6) Nand Gates
7) Invertor
The system should consist of two cascaded 4-bit up counters, each capable of counting
from 0 to 16. The final output of the counter should be decoded using a 7-segment decoder
to display the token number on the seven-segment display.
2. Introduction
 2. Introduction
A bank token system is a queuing mechanism used in banks and other service-oriented
establishments to manage customer flow efficiently. It typically involves issuing tokens to
customers upon arrival, which contain information such as their place in line or the service
they require. These tokens are then called in order, guiding customers to respective service
counters or tellers. By allocating numbered tokens on a fair and equitable basis, typically
adhering to the first-come-first-serve principle, token issue systems revolutionize the waiting
paradigm by affording individuals the luxury of waiting in comfort until their designated
number is summoned, obviating the need for protracted periods of standing in serpentine
queues. Key components of a bank token system may include:
1. Token Issuing System: This system generates unique tokens for each customer,
often utilizing a ticket dispenser or electronic interface.
2. Token Display: Displays or screens placed throughout the bank or service area
show the current token number being served, keeping customers informed of their
position in the queue.
3. Service Counters: Designated counters or stations where bank employees or
service personnel attend to customers based on their token numbers.
4. Token Management Software: Backend software manages the token queue, tracks
token numbers, and allocates resources to handle customer requests efficiently.
5. Customer Interface: Interfaces such as kiosks or mobile apps allow customers to
input their needs or preferences, aiding in directing them to the appropriate service
counter.
The bank token system enhances customer experience by reducing wait times, improving
staff efficiency, and ensuring fair and organized service delivery. It optimizes resource
allocation within the bank, leading to smoother operations and increased customer
satisfaction.

In this project, we aim to design a digital bank token number display using digital circuits.
The display will count from 00 to 16 using a cascaded 4-bit up counter. The design includes
various logic gates, flipflops (D),Adders and a 7-segment decoder to display the count on a
common cathode 7-segment display.
3. Design Process
 3. Design Process
 D Flip-Flop Design:
We begin by constructing a D flip-flop utilizing NAND gates, configuring it to operate on
negative edge triggering. This D flip-flop will serve as the fundamental memory element in
our counter design, effectively storing and manipulating binary information.

 4-Bit Up Counter Design:

Next, we embark on the creation of a 4-bit up counter, utilizing a series of cascaded JK flip-
flops. With each clock pulse, the counter increments by one, systematically progressing
through its binary count. When the count reaches its maximum value of 9 (represented as
1001 in binary), it cyclically resets to 0 (0000), thus perpetuating the counting cycle
seamlessly.

 Full Addder Circuit:

In the bank token counter system designed in Cadence, adders play a pivotal role in
facilitating efficient counting operations. When the enable pin is activated, the adder
incrementally accumulates the count, ensuring accurate tracking of tokens processed. This
essential component efficiently combines multiple input signals, enabling seamless addition
of binary digits and yielding a comprehensive tally of tokens served. By integrating adders
within the system, Cadence ensures robust functionality, allowing the bank to effectively
manage customer flow and optimize service delivery.

 7-Segment Decoder:
To translate the binary-coded decimal (BCD) output of our mod 100 counter into a format
suitable for display, we integrate a 7-segment decoder into our design. This decoder
functions as the intermediary between the digital counter output and the visual
representation on the 7-segment display, converting the BCD input into signals capable of
driving the individual segments of the display. Through this seamless integration, we ensure
that the numerical information stored within our counter is conveyed accurately and
comprehensibly to the end user, facilitating intuitive interpretation and interaction with the
displayed data.
4. Component Used
 4. Component Used
 NAND Gates:
NAND gates are digital logic gates that perform the operation of the logical NAND function.
They have two or more inputs and one output.
The output is high (1) only when all inputs are low (0).
In this project, NAND gates are primarily used for constructing the D flip-flop and other logic
functions required for counting and control.
 OR Gates:
OR gates are digital logic gates that perform the operation of the logical OR function.
They have two or more inputs and one output.
The output is low (0) only when all inputs are low (0).
OR gates might be used in various parts of the project for logical operations.
 D Flip-Flop:
A D flip-flop is a sequential logic circuit with one input D and clock input (CLK), and two
outputs (Q and Q').
It can store one bit of data and is commonly used in counters, shift registers, and memory
storage applications.
D flip-flops can be constructed using various logic gates, such as NAND gates in this project.
4-Bit Up Counter:
A 4-bit up counter is a digital circuit that counts in binary from 0000 to 1111 (0 to 15 in
decimal) and then resets.
It consists of four flip-flops, each representing one bit of the count.
The counter increments by one on each clock cycle.
In this project, four D flip-flops are connected in cascade to form the 4-bit up counter.

 7-Segment Display Decoder:

A 7-segment display decoder is a digital circuit that converts binary-coded decimal (BCD)
input into signals that can drive a 7-segment display to represent decimal numbers (0-9).
It typically has four input lines (BCD inputs) and seven output lines (segments of the
display). Each output corresponds to one segment of the 7-segment display. The decoder
is essential for converting the binary count into a readable display format.
 Adder Circuit:
An adder is a fundamental digital circuit that performs addition of binary numbers. It takes
two binary inputs (usually termed A and B) and produces a sum output. Additionally, it may
produce a carry output for use in cascading multiple adders to handle multi-bit numbers.
5. Implementation
 5. Implementation
Positive D Flipflop Construction:
To construct a D flip-flop using NAND gates, we first need to understand the functionality of
a D flip-flop. A D flip-flop is a type of sequential logic circuit with two input D, one clock input
(CLK), and two outputs (Q and Q'). It has two possible input combinations: D=0 output
Q=0,Q’=1; and D=1,Q=1,Q’=0;
Here's how we can implement a D flip-flop using NAND gates:

Fig: D ff schematics using Nand

Fig: D FlipFlop output

 Negative Edge D Flipflop Construction:
To construct a D flip-flop using NAND gates, we first need to understand the functionality of
a D flip-flop. A D flip-flop is a type of sequential logic circuit with two input D, one clock input
(CLK), and two outputs (Q and Q'). It has two possible input combinations: D=0 output
Q=0,Q’=1; and D=1,Q=1,Q’=0; but here all functionality happens at falling edge of clock.
Here's how we can implement a Neg Edge D flip-flop using NAND gates:

Fig: Negative Edge D ff schematics using Nand

Fig: Negative D FlipFlop output

 Adder Construction:
An adder is a fundamental digital circuit that performs addition of binary numbers. It takes
two binary inputs (usually termed A and B) and produces a sum output. Additionally, it may
produce a carry output for use in cascading multiple adders to handle multi-bit numbers.

How it Works:

1. Binary Addition Principle: Binary addition follows the same principles as decimal
addition. Each bit position in the result depends on the sum of the corresponding bits
in the input numbers, as well as any carry from the previous lower significant bit.

2. Basic Components:

• Half Adder: Adds two single binary digits (bits) and produces a sum and a
carry-out.

• Full Adder: An extension of the half adder that also considers an incoming
carry, producing both a sum and a carry-out.

3. Cascading: To add multi-bit numbers, you cascade multiple full adders. The carry-
out from one full adder serves as the carry-in to the next, allowing addition of
numbers of arbitrary length.

Fig: Circuit of Adder using Transistors

 Fig: outputs of Adder using Transistors

NOR GATE Construction:

A NOR gate is a fundamental logic gate with two or more inputs and one output. Its output is
true only when all of its inputs are false. NOR gates are widely used in digital circuits and can
be constructed using transistors. Here's how you can construct a NOR gate using transistors:

Construction Details:
• Transistors (Q1 and Q2):
• Q1 and Q2 are N-channel MOSFETs (NMOS).
• Q3 and Q4 are (pmos)
• Connect both pmos in parallel source short them and connect to vdd and
drain shot them and connect to Vout
• The gate terminal of Q1 is connected to input A.
• The gate terminal of Q2 is connected to input B.
• Connect both nmos in series Drain Of Q1 to Vout and Source of Q1 to Drain
of Drain of Q2 and Source of Q1 to gnd.
• Then Take Vout and Shorted Drain of Q1,Q2,Q3.
• Operation:
• When either input A or B is high (logic 1), the corresponding transistor (Q1 or
Q2) conducts, pulling the output node (Vout) to ground (logic 0).
• Only when both inputs A and B are low (logic 0), both transistors are off,
allowing Vout to be pulled up to Vdd through the pull-up resistor, resulting in a
logic 1 output.
 Fig: outputs of NOR using Transistors
NAND GATE Construction:
A NAND gate is a fundamental logic gate with two or more inputs and one output. Its output
is true only when all of its inputs are false or anyone input is false. NAND gates are widely
used in digital circuits and can be constructed using transistors. Here's how you can construct
a NOR gate using transistors:

Construction Details:
• Transistors (Q1 and Q2,Q3 and Q4):
• Q1 and Q2 are N-channel MOSFETs (NMOS).
• Q3 and Q4 are (pmos)
• Connect both nmos in parallel source short them and connect to vdd and
drain shot them and connect to Vout
• The gate terminal of Q1 is connected to input A.
• The gate terminal of Q2 is connected to input B.
• Connect both pmos in series Source Of Q3 to Vout and Source of Q4 to
Drain of Q3 and Drain of Q4 to gnd.
• Then Take Vout and Shorted Drain of Q1,Q2 and Source of Q3.
• Operation:
• When either input A or B is high (logic 1), the corresponding transistor (Q1 or
Q2) conducts, pulling the output node (Vout) to ground (logic 0).
 • Only when both inputs A and B are low (logic 0), both transistors are off,
allowing Vout to be pulled up to Vdd through the pull-up resistor, resulting in a
logic 1 output.

Fig: outputs of NAND using Transistors

Bank Token Counter Construction (Integration of Each part of circuit):

The design involves three separate counters, each displaying its present count value when
enabled. Enabling any one of the three counters triggers an increment of 1 in each of the
counters. This incremented value is stored in positive edge-triggered D flip-flops.
Simultaneously, this value is sent to negative edge-triggered flip-flops for storage (registers)
and display on a 7-segment display.

The flip-flops are arranged as 4-bit registers labelled as b0, b1, b2, and b3. Upon
encountering another enable, the process repeats. When the sum reaches 2, the value is
updated and stored in the positive edge-triggered D flip-flop. Similarly, this updated value is
stored in the negative edge-triggered flip-flops and displayed on the 7-segment display. This
process continues for subsequent increments.
 Fig: schematic of Bank Token Counter

Fig: Outputs of Bank Token Counter

Here whenever the enable e1 is on the outputs b0,b1,b2,b3 display 0001 and similarly next
When another enable is encountered the outputs b4,b5,b6,b7 display 0010 and similary
When another enable is encountered the outputs b8,b9,b10,b11 displays 0011 and so on.
Then again the process continues then 4 to 16 is being displayed in in 4 bit and displayed on
7 Segment Display.
Fig: Outputs of Bank Token Counter Cont..
6. Conclusions
 6. Conclusions
The undertaken project presented formidable challenges, requiring a comprehensive
approach to address. Our development of the "BANK TOKEN ISSUE SYSTEM" represents
more than a mere replication of existing market models; it embodies a pioneering research
endeavor poised to redefine industry standards. In light of the escalating demands of
industrialization, the imperative for sophisticated interfacing systems has become
increasingly apparent. The repercussions of inadequate time management and data
oversight within industrial settings have been starkly evident.

The primary objective of this project is to facilitate seamless data management across
diverse units within large-scale enterprises, particularly within multifaceted industrial plants.
The automation of token issuance stands as a critical feature, particularly within the evolving
landscape of banking services in India. The automatic allocation of tokens to customers is
indispensable, serving as a cornerstone function in enhancing operational efficiency and
customer satisfaction within banking institutions.

Furthermore, the versatility of token display systems extends beyond the banking sector,
finding utility in various public-facing domains such as airports, governmental offices,
healthcare facilities, and hospitality establishments. By leveraging these systems,
organizations can optimize customer flow, eliminating the need for prolonged queuing and
enhancing overall service delivery.

In essence, our project not only addresses immediate operational needs but also anticipates
and aligns with the evolving demands of modern industries. By championing innovation and
efficiency, we endeavor to set new benchmarks for excellence in data management and
customer service across diverse sectors.