UNIT 1: DIGITAL LOGICAL CIRCUITS

What is Digital Computer? OR Explain the block diagram of digital computers.

 Digital computer is a digital system that performs various computational tasks.

 The word “DIGITAL” implies that the information in the computer is represented by
digits.
 Digital computers use the binary number system, which has two digits, 0 and 1.
 A binary digit is called a bit.
 Information is represented in digital computers in the groups of bit.
 By using various coding techniques, groups of bits can be made to represent not only
binary numbers but also other symbols, letters of alphabets and decimal digit.
 Bits are grouped together as bytes and words to form some type of representation
within the computer.
 A sequence of instructions for the computer is known as program.

Block diagram of a digital computer

Random Access Memory

Central Processing Unit

Input Output
Devices Input-Output Processor Devices

 The hardware of the computer is usually divided into three major parts.
 The Central processing Unit (CPU) contains an arithmetic and logic unit for
manipulating data, a number of registers for storing data and control circuits for
fetching and executing instructions.
 The memory of a computer contains storage for instructions and data, it is called a
Random Access Memory (RAM) because the CPU can access any location in memory
at random and retrieve the binary information within a fixed interval of time.
 The input and output processor contains electronic circuit for communication and
controlling the transfer of information between the computer and the outside world.
 The input and output device connected to the computer include keyboards, printers,
terminals, magnetic disk drives and other communication devices.
What is Gates? Explain the Logic Gates in brief.

 Binary information is represented in digital computers using electrical signals.

 These signals can be represented by voltage to specify one of two possible states.
 The two states represent a binary variable that can be equal to 1 or 0.
 The manipulation of binary information in a computer is done using logic circuits called
gates.
  Gates are blocks of hardware that produce signals of binary 1 or 0 when input logic
requirements are satisfied.
 There are various types of logic gates are commonly used in digital computer.
 Each gate has a different graphic symbols and operation.
 The input-output relationship of binary variables for each gate can be represented in
tabular form by Truth-Table.
 There are three types of gates:
o Basic / Fundamental Gates (AND, OR, NOT)
o Universal Gates (NAND, NOR)
o Exclusive Gates (EX-OR, EX-NOR)

LOGICAL GATES

Basic / Fundamental Gates Universal Gates Exclusive Gates

(AND, OR, NOT) (NAND, NOR) (EX-OR, EX-NOR)

Basic Gates
AND Gate:
 In this type of gate output is high only when all its inputs are high.
 If any single input is law then the output will remain low.
 So it is said that in AND gate the output is only high when the input is also high.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPUT
A B A AND B
0 0 0
0 1 0
1 0 0

1 1 1

OR Gate:
 In this type of gate if any input signal is high then the output will be high.
 The output is only low only when all the inputs are low
 SYMBOL:

TRUTH-TABLE:

INPUT OUTPUT
A B A OR B
0 0 0
0 1 1
1 0 1

1 1 1

NOT Gate:
 This type of gate is also known as “Inverter”.
 It is a gate that contains only one input and only one output.
 The output is always opposite than the input signals.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPUT
A NOT A
(A’)
0 1
1 0

Universal Gates

NAND and NOR gates are known as universal gates because we can construct any gate using
NAND & NOR gate.
NOR Gate:
 The NOR gate is the complement of the OR gate.
 As shown in the truth table that the output of NOR gate is exactly opposite than the
output of OR gate.
 This means that the output will be high when all the input is low.

SYMBOL:
 TRUTH-TABLE:

INPUT OUTPUT
A B A NOR B
0 0 1
0 1 0
1 0 0

1 1 0

NAND Gate:
 The NAND gate is an AND gate followed by NOT gate.
 As shown in the truth table that the output of NAND gate is exactly opposite than the
output of AND gate.
 This means that the output will be high when all the input is high.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPUT
A B A NAND B
0 0 1
0 1 1
1 0 1

1 1 0

Exclusive Gates
EX-OR Gate:
 This gate is produces high output whenever the two inputs are at opposite level.
 The EX-OR gate is the gate that produces high output for Odd number of high inputs.

SYMBOL:
 TRUTH-TABLE:

INPUT OUTPUT
A B A EX-OR B
0 0 0
0 1 1
1 0 1

1 1 0

EX-NOR Gate:
 This gate is produces high output whenever the two inputs are at same level.
 The EX-OR gate is the gate that produces high output for Even number of high inputs.
 The truth table shows that output of this gate is exactly opposite of EX-OR gate.

SYMBOL:

TRUTH-TABLE:

INPUT OUTPUT
A B A EX-NOR B
0 0 1
0 1 0
1 0 0

1 1 1

Write a note on Boolean Algebra

 In 1854 George Boole introduced a systemic treatment of logic and developed for this
purpose an algebric system called Boolean Algebra.
 Boolean Algebra is an algebra that deals with binary variables and logic operations.
 The variables are designated by letters such as A,B, X ,Y etc.
 The three basic operations are AND, OR and complement.
 A Boolean function can be expressed with binary variable, the logic operation
symbols, parentheses ( rounded bracket) and equal to (=) sign.
 The result of a Boolean function is either 0 or 1.
  A Boolean function can be represented by either:

a. Truth tables
b. Logic diagrams
c. Algebraic expression

 For example: F=x+y’z

o F=1 only if x is 1 or if both y’ and z=1.
o If y’(complement of y)=1 means that y=0 so we can say that F=1 only when
x=1,y=0,z=1.
o So we can say that function F equal to 1 for those combination where x=1 or
yz=01
 A Boolean function can be transformed form algebraic expression into a logic diagram
composed of AND,OR and NOT gates.
 Truth table and logic diagram For above example :

x Y z F
0 0 0 0
0 0 1 1
0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

Boolean Operations

There are three basic logical operations:

 AND: This operation is represented by a dot or by the absence of an operator. For

example, x.y = z or xy = z is read “x AND y is equal to z.” The logical operation AND is
interpreted to mean that z=1 if and only if x=1 and y=1; otherwise z=0.
 OR: This operation is represented by a plus sign. For example, x+y = z is read “x OR y is
equal to z”, meaning that z=1 if x=1 or if y=1 or if both x=1 and y=1. If both x=0 and y=0,
then z=0.
 NOT: This operation is represented by a prime (sometimes by a bar). For example, x’ =
z (or x = z) is read “x not is equal to z”, meaning that z is complement of x. In other
words, if x=1, then z=0, but if
 x=0, then z=1.

Basic Identities of Boolean Algebra

Postulates and theorems of Boolean Algebra

Write a note on K- Maps.

 The Karnaugh map is also referred as Veitch Diagrams, KV maps or K-maps.

 K-map is a method to minimizes the Boolean function.
 K-map provides a simple and straight forward method to minimizing Boolean
expression.
 With the help of K-map we can simplified Boolean expression up to 4 and 6 variables.
 K-map diagram represents squares and each square represents 1 minterm.
 In K-map values of the variables are written in binary form & the logic function can be
expressed in one of the following form
o SUM OF PRODUCTS (SOP)
o PRODUCT OF SUM (POS)
 A K-map for n variables is made up of 2n squares and each squares designed a product
term of Boolean expression.
 For product terms which are present in expression, 1s are written in correspondence
squares and 0 will be written in blank square.
 For example: K-map for 2 variables:

 F =xy’ + x’y
  RULES FOR K- MAP:
 Each cell with 1 must be included in at list 1 group.
 Try to form the largest possible groups.
 Try to end up with as few groups as possible.
 Groups may be in sizes that are powered of 2.
 Groups may be square or rectangular only.
 Groups may be horizontal or vertical but not diagonal.
 Groups may wrap around the table.
 Groups may overleap.
 The larger a group is, the more redundant inputs there are:
o Group of 1 has no redundant input.
o Group of 2 known as pair has 1 redundant input.
o Group of 4 known as quad has 2 redundant input.
o Group of 8 known as octet has 3 redundant input.

Sum-of-Products Simplification
 A Boolean function represented by a truth table is plotted into the map by inserting 1's
into those squares where the function is 1.
 Boolean functions can then be simplified by identifying adjacent squares in the
Karnaugh map that contain a 1.
 A square is considered adjacent to another square if it is next to, above, or below it. In
addition, squares at the extreme ends of the same horizontal row are also considered
 adjacent. The same applies to the top and bottom squares of a column. The objective
to identify adjacent squares containing 1's and group them together.
 Groups must contain a number of squares that is an integral power of 2.
 Groups of combined adjacent squares may share one or more squares with one or
more groups.
 Each group of squares represents an algebraic term, and the OR of those terms gives
the simplified algebraic expression for the function.
 To find the most simplified algebraic expression, the goal of map simplification is to
identify the least number of groups with the largest number of members.

We will simplify the Boolean function.

F (A,B,C) = (3,4,6,7)

Map for F(A,B,C) = Σ(3,4,6,7)

 The three variable maps for this function is shown in the figure 2.4
 There are four squares marked with 1’s, one for each minterm that produces 1 for the
function. These squares belong to minterm 3,4,6,7 and are recognized from the figure
b.
 Two adjacent squares are combined in the third column. This column belongs to both
B and C produces the term BC.
 The remaining two squares with 1’s in the two corner of the second row are adjacent
and belong to row columns of C’, so they produce the term AC’.
 The simplified expression for the function is the or of the two terms:
F = BC + AC’

The second example simplifies the following Boolean function:

F(A,B,C) = (0,2,4,5,6)
 The five minterms are marked with 1’s in the corresponding squares of the three
variable maps.
 The four squares in the first and the fourth columns are adjacent and represent the
term C’.
 The remaining square marked with a 1 belongs to minterm 5 and can be combined
with the square of minterm 4 to produce the term AB’.

The simplified function is

F = C’+AB’
Map for F(A,B,C) = Σ(0,2,4,5,6)
 Figure 2.6 Map for F(A,B,C,D) = Σ(0,1,2,6,8,9,10)

 The area in the map covered by this four variable consists of the squares marked with
1’s in fig 1.10. The function contains 1’s in the four corners that when taken as groups
give the term B’D’. This is possible because these four squares are adjacent when the
map is considered with the top and bottom or left and right edges touching.
 The two 1’s on the bottom row are combined with the two 1’s on the left of the
bottom row to give the term B’C’.
 The remaining 1 in the square of minterm 6 is combined with the minterm 2 to give the
term A’CD’.

The simplified function is:

F = B’D’ + B’C’ + A’CD’

Product-of-Sums Simplification
 Another method for simplifying Boolean expressions can be to represent the function
as a product of sums.
 This approach is similar to the Sum-of-Products simplification, but identifying adjacent
squares containing 0’s instead of 1’s forms the groups of adjacent squares.
 Then, instead of representing the function as a sum of products, the function is
represented as a product of sums.

Examples
F(A,B,C,D) = (0,1,2,5,8,9,10)

The 1’s marked in the map of figure 2.7 represents the minterms that produces a 1 for
the function.
The squares marked with 0’s represent the minterm not included in F and therefore
denote the complement of F.
Combining the squares with 1’s gives the simplified function in sum-of-products form:
F = B’D +B’C’+A’C’D

If the squares marked with 0’s are combined as shown in the diagram, we obtain the
simplified complement function:
 F’=(A’+B’)(C’D’)(B’+D)

Figure 2.7 Map for F(A,B,C,D) = Σ (0,1,2,5,8,9,10)

The logic diagram of the two simplified expression are shown in fig 2.8

Logic Diagram with AND and OR gates

 The sum of product expression us implemented in fig 2.8(a) with a group of of AND
gates, one for each AND term.
 The output of the AND gates are connected to the inputs of a single OR gate. The
same function is implemented in fig 2.8(b) in product of sum form with a group of OR
gates, one for each OR term, the outputs of the OR gates are connected to the inputs
of a single And gate.
 In each case it is assumed that the input variable are directly available in their
complement, so inverter are not included.

Write a note on Combinational Circuits

 A combinational circuit is the circuit where more than 1 circuit is designed into single
component.
 It has N no of inputs and M no of outputs.
 It is basically used to design digital applications and it transforms the data into the
digital manner.
 A combinational circuit is a connected arrangement of logic gates with a set of inputs
and outputs.
  At any given time, the binary values of the outputs are a function of the binary values
of the inputs.
 The design of a combinational circuit starts from a verbal outline of the problem and
ends in a logic circuit diagram. The procedure involves the following steps:

1. The problem is stated.

2. The input and output variables are assigned letter symbols.
3. The truth table that defines the relationship between inputs and outputs is
derived.
4. The simplified Boolean functions for each output are obtained.
5. The logic diagram is drawn.

Arithmatic circuits:
 It is made of different arithmetic operators. There will be addition, substraction,
division, modules and any other arithmetic operations.

Half-Adder

 Half-Adder is a part of combinational circuit.

 It is basically designed for arithmetic addition.
 It is most basic digital arithmetic circuit.
 Performs the addition of two binary digits.
 The input variables of a half-adder are called the augend and the addend.
 The output variables of a half-adder are called the sum and the carry.

Full-Adder

 A full-adder performs the addition of three binary digits.

 Two half-adders can be combined to for a full-adder..
 Although a full adder has three inputs, it still only has two outputs since the largest
number is 1+1+1 = 3, and 3 can be represented by two bits.
WHAT IS THE DIFFERENCE BETWEEN HALF ADDER AND FULL ADDER?

Half adder Full adder

The most basic digital arithmetic circuit. A full-adder performs the addition of three
binary digits.
Performs the addition of two binary digits. It is used for multi bit additions.
Output is sum of two signals. Output is sum of three signals.
There are two input and two output There are three input and two output
terminal. terminal.
From full adder half adder cant not be built Two full adder makes one full adder
On EX-OR gate and one AND gate are used. Two EX-OR, two AND and one OR gate is
used.
WHAT IS THE DIFFERENCE BETWEEN COMBINATIONAL CIRCUIT AND
SEQUENCIAL CIRCUIT?

COMBINATIONAL CIRCUIT SEQUENTIAL CIRCUIT

It is a digital logic circuit whose output It is a digital logic circuit whose output
depends on the present inputs. depends on the present inputs as well as
previous inputs.

It can describe by the output values. It can describe by the output values as well
as state values.

It contains no memory element. It contains at least one memory element.

It is easy to design and understand. It is difficult to design and understand.

It is faster in speed. It is slower in speed.

It is expensive in cost. It is less expensive in cost.

Examples of combinational circuit are half Examples of sequential circuit are flip-flops
adder and full adder. like RS, Clocked RS, D and JK.

A combinational circuit is a connected However, if a circuit uses both gates and

arrangement of logic gates with a set of flip-flops, it is called a sequential circuit.
inputs and outputs.

At any given time, the binary values of the Hence, a sequential circuit is an
outputs are a function of the binary values interconnection of flip-flops and gates.
of the inputs.

The design of a combinational circuit starts If we think of a sequential circuit as some

from a verbal outline of the problem and black box that, when provided with some
ends in a logic circuit diagram. external input, produces some external
output

What is Flip-flops

 A Flip-flop is a binary cell capable of storing one bit of information.

 It has two outputs, one for the normal value and one for the complement value of the
bit stored in it.
 Flip-flops are storage elements utilized in synchronous sequential circuits.
 Synchronous sequential circuits employ signals that effect storage elements only at
discrete instances of time.
 A timing device called a clock pulse generator that produces a periodic train of clock
pulses achieves synchronization.
  Values maintained in the storage elements can only change when the clock pulses.
 Hence, a flip-flop maintains a binary state until directed by a clock pulse to switch
states.
 The difference in the types of flip flops is in the number of inputs and the manner in
which the inputs affect the binary state.
 Flip-flops can be described by a characteristic table which permutates all possible
inputs (just like a truth table).
 The characteristic table of a flip-flop describes all possible outputs (called the next
state) at time Q(t+1) over all possible inputs and the present state at time Q(t).
 The most common types of flip flops are:
 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop

SR Flip-Flop
Figure SR Flip-Flop

Inputs:
 S (for set)
 R (for reset)
 C (for clock)

Outputs:
 Q
 Q'

The operation of the SR flip-flop is as follow.

 If there is no signal at the clock input C, the output of the circuit cannot change
irrespective of the values at inputs S and R.
 Only when the clock signals changes from 0 to 1 can the output be affected according
to the values in inputs S and R
 If S =1 and R = 0 when C changes when C changes from 0 to 1 output Q is set to 1. If S =
0 and R =1 when C changes from 0 to 1.
 If both S and R are 0 during the clock transition, output does not change.
 When both S and R are equal to 1, the output is unpredictable and may go to either 0
or 1, depending on internal timing that occur within the circuit.
D Flip-Flop
D Flip-flop

Inputs:
 D (for data)
 C (for clock)

Outputs:
 Q
 Q'
The operation of the D flip-flop is as follow.

 The D Flip-Flop can be converted from SR Flip-Flop by inserting an inverter between S

and R and assigning the symbol D to the single input.
 The D input is sampled during the occurrence of a clock transition from 0 to 1.
 If D=1, the output of the flip-flop goes to the 1 state, but if D=0, the output of the flip-
flop goes to the 0 state.
 The next state Q(t+1) is determined from the D input. The relationship can be
expressed by a characteristic equation:
Q(t+1) = D
 D Flip-Flop has the advantage of having only one input (excluding ), but the
disadvantage that its characteristic table does not have a “no change” condition
Q(t+1) = Q(t).

JK Flip-Flop

Jk Flip-Flop

Inputs:
 J
 K
 C (for clock)
 Outputs:
 Q
 Q'

The operation of the JK flip-flop is as follow.

 A JK Flip-Flop is a refinement of the SR flip-flop in that the indeterminate condition of

the SR type is defined in the JK type.
 Inputs J and K behave like inputs S and R to set and clear the flip-flop, respectively.
 When inputs J and K are both equal to 1, a clock transition switches the outputs of the
flip-flop to their complement state.
 Instead of the indeterminate condition of the SR flip-flop, the JK flip-flop has a
complement condition Q(t+1) = Q’(t) when both J and K are equal to 1.

T Flip-Flop
T Flip-Flop

Inputs:
 T (for toggle)
 C (for clock)

Outputs:
 Q
 Q'

The operation of the T flip-flop is as follow.

 Most flip-flops are edge-triggered flip-flops, which means that the transition occurs at
a specific level of the clock pulse.
 A positive-edge transition occurs on the rising edge of the clock signal.
 A negative-edge transition occurs on the falling edge of the clock signal.
 Another type of flip-flop is called a master-slave flip-flop that is basically two flip-flops
in series.
 Flip-flops can also include special input terminals for setting or clearing the flip-flop
asynchronously. These inputs are usually called preset and clear and are useful for
initialing the flip-flops before clocked operations are initiated.
Flip-Flop Excitation Tables

 During the design of sequential circuits, the required transition from present state to
next state is known.
 What the designer needs to know is what input conditions must exist to implement
the required transition.
 This requires the use of flip-flop excitation tables.

Excitation Tables

SR Flip-Flop Excitation Table

Q(t+1) S R
Q(t)
0 0 0 X
0 1 1 0

1 0 0 1

1 1 X 0

JK Flip-Flop Excitation Table

Q(t) Q(t+1) J K

0 0 0 X
0 1 1 X

1 0 X 1

1 1 X 0
 T Flip-Flop Excitation Table

Q(t) Q(t+1) T

0 0 0

0 1 1

1 0 1

1 1 0

Sequential Circuits

 When a circuit contains just gates, it is called a combinational circuit. However, if a

circuit uses both gates and flip-flops, it is called a sequential circuit. Hence, a sequential
circuit is an interconnection of flip-flops and gates.
 If we think of a sequential circuit as some black box that, when provided with some
external input, produces some external output, a typical sequential circuit would
function as follows:
 The external inputs constitute some of the inputs to the combinational circuit. The
internal outputs of the combinational circuit are the internal inputs to the flip-flops.
 The internal outputs of the flip-flops constitute the remaining inputs to the
combinational circuit. The external outputs are some combination of the outputs from
the combinational circuit and flip-flops. The behavior of a sequential circuit is
determined from the inputs, the outputs, and the state of the flip-flops. Both the
outputs and the next state are determined by the inputs and the present state.
 A state diagram can represent the information in a state table graphically, where
states are represented by circles (vertices) and transitions on specific input is
represented by the labels on the directed lines (edges) connecting the circles.

Design Procedure

 Formulate behavior of circuit using a state diagram.

 Determine # of flip-flops needed (equal to # bits in circles).
 Determine # inputs (specified on edges of diagram).
 Create state table, assigning letters to flip-flips, input, and output variables.*
 For each row, list the next state as specified by the state diagram.
 Select flip-flop type to be used in circuit.
 Extend state table into an excitation table by including columns for each input of each
flip-flop.
 Using excitation table and present state-to-next state transitions, formulate input
conditions for flip-flops.
 Construct truth table for combinational circuit using present-state and input columns
of excitation table (for inputs) and flip-flop inputs (for outputs).
 Use map simplification of truth table to obtain flip-flop input equations.**
 Determine external outputs of sequential circuit (flip-flop outputs and potentially
combinational circuit outputs).
 Draw logic diagram as follows:
  Draw flip-flops and label all their inputs and outputs.
 Draw combinational circuit from the Boolean expressions given by the flip-
flop input equations.
 Connect outputs of flip-flops to inputs in the combinational circuit.
 Connect outputs of combinational circuit to flip-flop inputs.

For m flip-flops and n inputs, the state table will consist of m columns for the present
state, n columns for the inputs, and m columns for the next state. The number of rows
in the table will be up to 2m+n, one row for each binary combination of present state
and inputs.

** Each flip-flop input equation specifies a logic diagram whose output must be
connected to one of the flip-flop inputs.

NAND and NOR Implementation

A sum-of-products expression can be implemented with NAND and NOR gates as

shown in the figure 2.9

Figure 2.9 Logic Diagram with NAND and NOR gates

Don't Care Conditions

 In k-map each cell represents a minterm or maxterm and the 0’s and 1’s in k map
represents the minterm that make the function equal to either 0 or 1.

 But in some occasion, it doesn't matter whether a function produces a 0 or 1 for a

given minterm.
 When this condition occurs, an X is used in the map to represent the don't care
condition.
 The minterm that may produce either 0 or 1 for function are said to be Don’t Care and
marked as x in map.
 This don’t care condition are used to further simplify the Boolean expression.
 Don’t care condition is the condition where any single square or map will appear as x n
it is not necessary to write into Boolean expression.
 Example
F(w,x,y,z)= ∑(0,1 ) + d(4,5,14)

 So the ans is W’Y’