MG 21 Sup

1
Colour television
Chassis
MG2.1 E
Training Manual
Contents
Contents Introduction Mechanical Instructions Blockdiagram Service modes / Compair Control and Teletext Power Supply Tuner and IF Sound MG2.1E HIP, I/O select, Video processing Featurebox (integrated on SSP) TOPIC HOP PTP and Scavem Line deflection Frame output stage Audio amplifiers Protection structure
Published by CO9870 Television Service Department Printed in The Netherlands Copyright reserved 1998 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips Subject to modification 5 4822 727 21619
1 2 3 5 9 10 14 30 33 35 38 40 43 51 56 65 66 73
Copyright reserved 1998 Philips Consumer Electronics B.V. Eindhoven, The Netherlands. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips Published by CO9870 Television Service DepartmentPrinted in The Netherlands Subject to modification 5 4822 727 21619
Chapter 1 Introduction
European eco 100 Hz
MG2.1 E
Introduction
Chapter 1 Introduction
The MG project includes all developments of high-end for Europe, Asia and America (Global = all over the world one chassis). With this concept a large range of TV-sets are possible: 50Hz, 100Hz, PAL+, SVGA, etc.... MG consist of two basic concepts: low- and high-end architecture. A big difference with previous chassis is the high integration of function into IC's. Specs dependent of the region: Europe Source select for 2 till 4 scarts Mostly 100 Hz and 16:9 No PIP but dual screen for the top-range Philips CRT Easylink (P50) and nexTView (EPG) with or without flashram Tuner and IF suitable for all European standards A lot of possibilities for picture and sound
LOW architecture: FBX is flat (integrated) on SSP Not real AUTO TV, however many picture improvements are automatic Source selection with 2 Scarts No comb filter, no TOPIC, sometimes scavem No Dolby, audio amplifier 2 X 15 W NextView from the received channel FL8 styling
European Medium (digital scan) AUTO TV, via a lightsensor to the TOPIC, the PICNIC and PROZONIC settings are controlled Source select with 3 Scarts Combfilter, TOPIC and Scavem Dual screen TXT in 16/9 sets Virtual Dolby audio amplifier 4 X 15 W Full Nextview FL7 styling
AP (Asia + Latin America) Cinch source select Mostly 1Fh (60 Hz) sets Mostly 4:3 applications Siemens PIP, dual screen optional Various Asian and Latam standards, country dependent
European TOP 100 Hz All features of medium-range and extra features added: HIGH architecture, separate FBX (module) Most sets 4 Scarts Pal plus in 16/9-sets Full Dolby or cordless dolby-surround (optional MCS) 4 X 15W + 2 X 8 W amplifiers (= multi channel sound) FL7 or FL9 styling
USA TOP sets Cinch Source select Digital Dolby: Multi Channel Sound (MCS) This is a digital sound systeem (MPEG or AC3) with max 6 channels audio 2Fh, 1Fv (60 Hz) Decoder for MPEG video Dual screen
AP 1 Fh (50 Hz or 60 Hz) Always 1 Fh mostly 60 Hz, for some regions 50 Hz LOW architecture for LSP AUTO TV , TOPIC with lightsensor AP source select with cinch-plugs Comb filter, Scavem PIP present Virtual Dolby FL7 styling
General note: The MG project includes also panels for Projection- or Flat-TV Type number description; First two digits for tube size: Lettercombination PT = 4 : 3 PW = 16 : 9 First digit 6 = 50 Hz or 60 Hz 7 = ECO 100 Hz AABB; 8 = DIG SCAN 9 = Natural motion/progressive Scan Second digit, (the higher the number- the higher the specs) Third digit: 0 = no dolby; 1 = dolby and Fourth digit 4 = Program 98; 5 = Program 99; 8 = AP With the MG-chassis various sets are possible:
EUROPEAN 50 Hz PICNIC for AARA in 16/9 Low architecture Auto TV with TOPIC Source Select 3 scarts. Combfilter, Scavem Dual Screen TXT Dolby Nextview of the received channel FL8 styling
Second European TOP 100 Hz Dual Screen Cordless Dolby-surround with MCS (multi channel sound)
MG2.1 E
Chapter 2 Mechanical instructions
Removing the rear cover

2. Remove I/O-backplate by releasing snap at left side. Pull to left and backwards. The I/O-bracket hinges at the right side. It can be removed now. 3. Pull backwards (about 8 cm) the bracket with the SSP and the LSP. These brackets are not fixed to each other, but can be repositioned backwards, as if they were one bracket. 4. Hook the brackets in the first row of fixation-holes of the bottom tray; see figure 4.3. In other words re-position the fixation from (1) TO (2)
Side I/O assembly
A A A
SSP - bracket LSP - topbracket
LSP - bracket
or
A or
A'
A or A or
CL 86532042_001.AI 160798
1. Remove the fixation screws (A) of the rear cover, notice also the side-I/O-screw; see figure 4.1 (A') screw only valid for 3-scart configuration. 2. Remove the rear cover.
1 Bottom tray 2
Service positions
There are two predefined service positions 1. Service position for the top side (component-side) 2. Service position for the bottom side (only valid for LSP) (copper-side)
CL 86532042_002.AI 240798
Service position bottom side (only for LSP)
Service position top side
CL 86532042_005.ai 090698
CL 86532042_003.ai 090698
1. Remove 1 screw in case of 2-scart I/O-backplate and 2 screws in case of a 3-scart I/O-backplate. (See figure 4.2)

Removing the SSP from SSP-bracket
MG2.1 E
1. Release the three fixation clamps on the right hand side of the bracket 2. Press the board upwards and remove the board from the bracket
Removing the LSP from LSP-bracket

2 1
1. Release the two fixation clamps on the right hand side of the bracket 2. Press the board upwards and remove the board from the bracket
CL 86532042_004.AI 240798
Removing the top control board
1. Referring to previous Service position one must remove the SSP and LSP from bottom tray by pulling back these two panels. 2. Disconnect the SSP from the LSP bracket 3. The two panels must be shifted some 25 cm to the right. When doing this the side-assembly can be taken out of the hinge (see figure 4.4), and placed on the bottom tray. 4. Either the LSP-topbracket must be removed first, or the cabling from SSP to LSP (0310 and O311) must be re-routed outside the LSP-topbracket to get room to position these panels 5. Turn the LSP 90 degrees anti clock wise and place the LSP in the hole of the bottom tray. If needed a screw can reinforce the stability of this position. (see figure 4.5) (See (2). 6. The left front hook of the SSP panel can be fixed in a fixation-hole, that was used in previous service-position for the right front hook of the SSP. See described movement-action (1). (there is no right fixation hole)
Top control board
CL 86532042_006.ai 160798
1. See figure 4.6. Pull 2 clamps to the outer side 2. Top control board can be pushed down now, while it hinges still in the front 3. Now the board can be pulled backwards 4. (If by accident the hinge in front is damaged or one of the clamps is broken, the top control board can also be fixed by 2 screws)
Service position bottom side SSP Removing the side I/O board
1. In fact there is no service position for the bottom of the SSP. Almost all components are present on the component-side. All test points are located on the component-side. 2. If ICs must be replaced take the complete panel out. If still a service-position is needed take SSP out of bracket and rotate it so that one (sitting behind the set) sees the copperside of the SSP, with Tuner pointed to the upper-side. 1. The complete Side I/O-assembly can be lifted out of the hinges and placed on the bottom tray of the set. (see fig 4.3) 2. The pcb can easily be removed out of the bracket by releasing the fixation clamps
Removing the mains switch/LED board

1. Release the two fixation clamps 2. Pull the board backwards
Removing the LSP-top bracket

1. (See figure 4.3). Remove the two fixation screws of the LSP-topbracket (one on the left hand side, one on the right hand side) 2. Disconnect wirings from cable-clamps of LSP-topbracket 3. In case the line transformer is changed by a bigger type a part of the LSP-topbracket can be removed by breaking it
Mounting the rear cover

Before mounting the rear cover, check whether the mains cord is mounted correctly in the guiding brackets
MG2.1 E
Chapter 3 Blockdiagram
Fig. 3.1
CL 86532047_001.eps 140798
Chassis name
The 'MG' chassis is the successor of the MD1, MD2, GFL-chassis. The MG architecture is global and can be produced all over the world. Explanation chassis name MGX.YZ Xdepends on specification Ydepends on introduction-timing Zregion e.g. E(urope); A(sia Pacific); U(SA) This manual deals with the MG2.1E. A small signal panel (SSP) is used and a large signal panel (LSP). On the LSP there are only a few SMD's, but the SSP is further integrated. There are no modules anymore; the FBX (feature-box) is integrated on the chassis. Due to the fact that all features are flat on one board, repair down to component level is an absolute must. For this reason there is a lot of diagnostic support built-in in the chassis: customer service mode (CSM) as used in the MD2.2-chassis. It decreases the number of nuisance calls.
service default mode (SDM). Predefined state of the set. service alignment mode (SAM) to do all kind of alignments, select test patterns, display error codes,.... full support of the dealer service tool (DST).
New tools and service features

A lot of additional service "features" are built in the MG2.1E. These "features" can be addressed with a new tool called ComPair (Computer Aided Repair). This is an interface that can receive the error codes and can send RC5 and RC6-codes. To this interface belongs also software and a CD-ROM with the service manual, circuit descriptions and fault finding trees. In this way searching for components on the PCB and schematics is history. Explanation Small Signal (fig 3.1). The tuner type UV1316 is a PLL tuner and delivers the IF-signal to the HIP (High-end Input Processor (TDA9320H)). The HIP has the following functions: IF-part video source select and record select colour decoder (PAL/SECAM/NTSC) synchronisation
Three scart connectors can be used. Scart 1 and 2 are full scart and scart 3 is only cvbs. Scart 2 is meant for VCR, thus on this scartpin 10 is used for Easylink and there is possibility for y/c
MG2.1 E
in/out. The cvbs-out on pin 19 can be used for WYSIWYR (= what you see is what you record). A digital combfilter can be used to have Y/C separation. The HIP delivers the signal to the PICNIC (SAA4978). The PICNIC takes care of: ADC (9 bits) (was FRONTIC) DAC (was ECOBENDIC) 100 Hz (was ECOBENDIC) Panorama mode (super zoom) (was PANIC) Noise reduction (was LIMERIC) Dynamic contrast (was SMARTIC)
tion, sound controls, source select. The sound for the subwoofer is derived from L and R. To the MSP3410 a new IC can be added: called SEDSP (Sound Effects Digital Sound Processing IC (SAA7712H)). This IC takes care of Dolby prologic decoding and some other features like virtual DOLBY, incredible surround, DBE, equaliser, ... I2C bus. In MG2.1E three different I2C busses are used: 1. Slow I2C bus (SCL/SDA-S); speed 100 kHz used for various IC's 2. Fast I2C bus (SCL/SDA-F); speed 400 kHz. (In the OTC there is only one hardware I2C bus. The two busses are made by a very fast switch.) 3. I2C bus for NVM (SCL/SDA-NVM). This short I2C-bus is used to avoid data corruption in the Non Volatile Memory. Microprocessor = OTC2.5 (On screen display, Teletext and Control, level 2.5 Txt) with integrated teletext (SAA5800). This IC takes care of the analogue Input- and Output-processing. The OTC, ROM and RAM are supplied with 3.3V. This voltage is derived from the +5V Standby.
For digital scan the PROZONIC (SAA4990) is required, that can be connected to the PICNIC. The PROZONIC was already used in the GFL- and MD2-chassis. For natural motion the MELZONIC can be used. These two ICs are mentioned in the blockdiagram as 2fh-features. For sets with PAL+ the same concept is used as in the MD2chassis and this is also connected to the PICNIC. From the PICNIC the signal is fed to the TOPIC (The most Outstanding Picture Improvement IC) TDA9178. This IC handles various picture improvements, e.g. sharpness. This IC works together with the PICNIC to handle auto-DNR. If there is noise in the videosignal then the DNR has to be high, but the sharpness must be low. So also the other possibility if the signal is perfect then the DNR is not necessary (DNR low) and the sharpness can be higher. (First introduced sets will not have Topic-ICs and also not a light sensor.)
Personal notes
DNR noisy signal good signal high low
Sharpness low high
The customer can select AUTO TV for a very high performance. Auto TV contains algorithms for contrast-improvement, sharpness, noise reduction and better colour behaviour. Via a light sensor the influence of the ambient light can be used for optimal contrast/brightness control.After the TOPIC the YUVsignals are fed to the HOP (High-end Output Processor (TDA933X)). In the HOP is the video control part and geometry integrated. The RGB-signals from TXT/OSD are inserted via the HOP. This IC has all functions from a videoprocessor and geometry control (like the DDP in MD2).The cut-off control is a little different: via the service menu there is an indication that the VG2-setting is correct (later in the first sets). The geometry part delivers the H-drive, V-drive and also a drivesignal for rotation. Blue mute is possible for: HOP OTC PICNIC
For the MG2.1E blue mute is made via the PICNIC and perhaps in future sets from the OTC. The soundpart is built up around the MSP3410D (all versions have NICAM) for IF sound detec-
MG2.1 E
+5V Standby
1010 degaussing +t Rs +t Rp 7020
~ 220V
+5V Standby
+140 (Vbat)
7213 start 7020 7020 7808 +8V6
3517/3520 7212 +5V Standby DCDC convertor IC7520 3 MC44603 10 14 IC7556 1 M34063A 5V2
TL431 Blockdiagram supply-part
Fig. 3.2a
CL 86532047_002.eps 140798
I2C bus. In MG2.1E three different I2C busses are used: 1. Slow I2C bus (SCL/SDA-S); speed 100 kHz used for various IC's 2. Fast I2C bus (SCL/SDA-F); speed 400 kHz. (In the OTC there is only one hardware I2C bus. The two busses are made by a very fast switch.) 3. I2C bus for NVM (SCL/SDA-NVM). This short I2C-bus is used to avoid data corruption in the Non Volatile Memory. Microprocessor = OTC2.5 (On screen display, Teletext and Control, level 2.5 Txt) with integrated teletext (SAA5800). This IC takes care of the analogue Input- and Output-processing. The OTC, ROM and RAM are supplied with 3.3V. This voltage is derived from the +5V Standby.
Personal notes
MG2.1 E
+140V (Vbat)
+13
+13
+5V2 Hdefl 7421 2432/2434
HOP
Hdrive
east/west modulator
Vdrive+ Vdrive-
7600 TDA8177 +13V
-15V Vdefl Blockdiagram deflection
Fig. 3.2b
CL 86532047_003.eps 140798
Explanation Large Signal (fig 3.2a+b). In MG2.1E there is a separate Standby supply that is used to reduce the Standby power. The main power supply is completely switched off via a relay and only the Standby supply is operational in Standby. A second relay (no triac) is used for switching off the degaussing circuitry. The degaussing is not switched from Standby to on. The power supply is a Fixed Frequency Supply with an operating frequency of 40 kHz. For the control part the MC44603 is used (also known from a lot of other chassis). Secondary a DCDC-converter (MC34063A) is used for stabilisation of the 5V2 for various circuitry. The Standby-command is also fed to the FFS to ensure quick switch-off of the power supply. In fig 3.2b the blockdiagram is drawn for the line output stage. There is no seriesswitch as in MD2- and GFL-chassis, because this function is now integrated in the HOP. In case of a flash or protection the line output stage is switched off by the HOP. The complete geometrycontrol is integrated in the HOP. The Vdrive is also coming from the HOP and the amplifier is realised with TDA8177.
Personal notes
MG2.1 E
Chapter 4 Service modes / Compair
Service modes
Chapter 4 Service modes / Compair
In the MG the following service modes are available: SAM (service alignment mode) SDM (service default mode) CSM (customer service mode)
Personal notes
This looks very much alike the MD2.2. ( For details see service manual). The DST tool can still be used, but an upgrade version of this is the Compair tool. (A PC-based diagnosis system). Difference related to previous sets: With an I2C bus error, the set will not be placed in protection anymore.
Compair (tool)
Compair (Computer Aided Repair) is a new tool for repairing the new TV-Sets and the new high-end video-recorders. With the help of Compair, repairing a set will be more time effective even without much knowledge of the set. By guiding the technician with the help of self-diagnostics and documents with text and oscilloscope waveforms on the screen of the PC, repairtime will decrease as well in the SSP and in the LSP part of the set. Compair consists of an electronic interface connected to the computer, to make via infrared communications a link to the upmarket TV-sets and via a wired I2C a link to Basic TV-Sets and high-end video recorders, and a Windows based computer program. Compair is running on a 486 PC with Windows 3.1 onwards Infra-red commands, received from the Compair interface, are converted into I2C commands towards devices connected to the I2C bus. In this all registers from IC's can be read to make a good diagnose.
Step-wise start-up/Stepwise shutdown (feature of Compair)

With Compair it will also be possible to start-up the set step by step. In this way the problem is solved that without knowing what the problem is the set switches into protection. (see also chapter 17). The repairman will be guided by Compair by means of fault-finding instructions with text and oscilloscope waveforms.
10
Chapter 5: Control and teletext 5.1 Control part

+5VSTBY 7012 3059 3054 G 3V3 470E TLUV 5300 SERVICE SEND LED IR receiver 100 R MAINS-SWITCH PANEL
MG2.1 E
ON/OFF
470
90
+5V STBY
7009 3V3
3V STBY
113 111
8V6
5VSTBY
SAA 5800 OTC 2.5
7006 7007 POR 104 74 R G B FADING 100E 5V2 3V3 108 H V KEYBOARD 107 93 83 84 109 115 96 103 106 AFC tuner HIP HSEL (OPTIONAL) STATUS 3 I/O CNTR - BUS OUT I/O I/O CNTR - BUS IN I/O FRONT DETECT 16/9 DETECT 90 94 95 5 16 6Mc 3V3 3209 STBY RAM_CS RAM_DE 3206 17 18 73 I C-0 I2C-1
2
470
STANDBY
77 8V6 3V3 105 OSD/TXT 78 79 80
+ 10R
HOP IC
SELECT CL/VL RESET AUDIO SOUND EN ABLE CVBS for txt PEAKING PEAKING FILTER TUNER I2C-SLOW I2C-FAST HIP I C-3
2
FBX
VIDEO SEL
AUDIO SELECT
RAM_DE CASHN CASL RaSN WE
HOP
WE
MSP 3410
TOPIC
ROM CE ROM CS 23 11 ROM 16Mbit (2Mbyte)
40 43 42 41 12 14 FLASH RAM EPG
41 71 73 69 70
RAM TXT CONTROL
NVM 32 Kbit
AO
A19
AO
A17
AO
A8
Fig. 5.1
CL 86532047_004.eps 051098
MG2.1 E

TXT
11
Remote Control
In MG2.1E a new remote control is introduced which uses RC6, because new commands are used like cursor control in 8 directions. There are two mode buttons on the side of the remote control: One for VCR and the other for DVD/SAT (digital source).
OTC
The SAA5800 (IC7003) is called the OTC (OSD, TXT and CONTROL). In this IC the microprocessor and the TXT-decoder are integrated. The SAA5800 is also called the OTC2.5 because also TXT-level 2.5 is supported. The OTC has also : RGB outputs for blending. The contrast (for blending) is software controlled. OTC 2.5 has various I/O ports for I2C, RC5, LED, ....
The TXT-decoder in the OTC gets two video signals: Direct to pin 5 and via the peaking filter (for Scandinavian countries) to pin 7. The input is selected via country selection in the installation menu. The RGB-outputs are available on pins 77/78/79. Fast blanking is realised via pen 80, but TS7017 and TS7018 are added to create a nice fast blanking signal that is needed in the TXT-mixed mode. These transistors are driven by an extra fast-blanking signal from pin 81. In future sets this circuitry will be deleted. In the previous chassis there was separate memory to store the TXT information. In MG the RAM (IC7001) of the microprocessor is also used for the TXT-decoder.
NexTView
NexTView allows the user to display a program guide on the TV screen which contains extensive information for each program. This information can be displayed in a number of different summaries: DAY: The daily summary shows, from the current moment, the program schedule for several stations for a short time ahead. CHANNEL: The channel summary shows the program schedule for one station. THEME: The theme summary shows, for each theme, the program schedule of the various stations. These themes consist of sport, film, culture, etc. and is determined from the station side.
The software for MG can be 2 MB (Megabyte). For sets with nexTView (also called EPG) a 512 KB flash-RAM IC7013 is used to store the Electronic Program Guide. For TXT-data 440 pages can be stored in a RAM IC7001. This is a DRAM of 4 Mbit and this IC is also used to store data of a working set. The Non Volatile Memory IC7008 is a 32 kbit version M24C32W6. All ICs in this part are supplied with 3V3. For this voltage a 3V3 stabiliser is used (IC7009). At start-up the POR is generated with TS7006/7007. During a reset all I/O pins are high. When a POR is generated the TV-set is in Standby mode. Via pins 105 and 106 the 8V6 and the 5V2 are sensed. If one of them is not present, the FFS-supply is switched off. The OTC will generate an error code to indicate what was wrong. The horizontal and vertical flyback pulses are also fed to the OTC for stable OSD and TXT. To create good stable pulses the HFB(H) and VFB(V) are inverted and fed to the OTC. The RGBoutputs (77/78/79) together with fading (pin 80) is fed to the HOP. The fading pin has in fact a double function: Make transparent menu Fast-blanking for TXT
NexTView does not have to restrict itself to information about the station which is being viewed, but also offers information about other stations. In the various summaries 3 different commands can be given for the various program overviews. These commands appear as follows: WATCH: The set immediately switches over to the station concerned. REMINDER: The start time and date and the station of the program concerned is stored in the TV reminder list. The TV will give an OSD-message with the program information, or switch on the set at the correct moment (provided the set is in Standby) and tune to the station concerned. RECORD: The timer of the video recorder with 'Easylink Plus' is programmed with the data of the program concerned. There has to be a video recorder (with Easylink Plus) connected to SCART2 otherwise the 'RECORD' function will not be highlighted. The connection is via pin 10 from SCART. This means that it has to be a full SCART or at least pin 10 has to be wired.
In MG2.1E there are three I2C-busses used: Slow I2C bus for tuner, fbx, video- and audio-selection Fast I2C bus for the HIP, HOP, MSP3410 and the TOPIC NVM- I2C bus for the Non Volatile Memory to prevent data corruption (=I2C3)
The OTC has also a connection with mains switch/led panel: Driving the "ON" and "Standby"-leds . The green led gives a quick indication that the 8V6 is present.<----- Service tip MG2.1E has an IR-send led connected to pin 90 for communication with DST or ComPair. The remote control signal comes in on pin 100. This can be RC5 or RC6 commands.
In order to be able to realise nexTView, two teletext type data flows, Datastream 1 and 2, are transmitted with various subcode pages of information. This data flow can transport limited information (max. 40 pages). Datastream 1 is quick repeating with a repetition time of approximately 20 to 30 seconds. How-
12
MG2.1 E
ever, Datastream 2 has a much longer repetition time of approximately half an hour and has a large transport capacity. Datastream 1 contains information of the station which is being viewed. Datastream 2 contains up to one week of advance information from various stations which are covered by the provider. The provider has to be selected in the installation menu.
Personal notes
Realisation of nexTView in MG2.1E

MG2.1E knows two executions of nexTView called "This Channel EPG" and "Multi Channel Composite EPG". "Multi Channel Composite EPG" makes use of both Datastream 1 and Datastream 2. Due to the size, in particular of Datastream 2 and the pass time which is coupled with that, a number of additional provisions have to be made in the set. Therefore, an extra Flash Memory is used in order to retain the information. Both the interpretation and storage of Datastream 2 require calculating capacity of the microprocessor. This all can not be performed during normal operation. Datastream 2 is then also stored at the moment that the set is in Standby. For this the set will go into Semi-standby (also see Power Supply chapter). The Semi-standby mode can be recognised by both the Standby and the "On"-LED illuminating. In the Semi-standby mode the entire small signal is switched on and it will be tuned to the nexTView provider which has been assigned during installation. The microprocessor can now use its full calculating capacity in order to load the Flash Memory. After the Datastream 2 has been completely stored the set will switch to Standby. This takes place after approximately half an hour. After this the set will check every 12 hours whether the information in Datastream 2 has changed. To do this the set again switches to Semistandby and the Flash Memory is erased and re-loaded when the information in Dataflow 2 has changed. Every morning at 5:40 the nexTView information will also be re-loaded because then information for the previous day can be deleted from the Flash Memory. "This Channel EPG" makes use of Datastream 1only. This data is loaded in the RAM as soon as the set is switched on. Only data of the current and next day is loaded and this is only data of the station watched. No Flash Memory is used. As soon as the set is put in standby after watching, the set will go to semi-standby for updating the so called CNI numbers. For this the set tunes to all pre-installed presets and tries to detect the CNI number of the broadcaster. A CNI number is an unique identification number assigned to a broadcaster and is available in TXT package 8/30. This CNI number will be stored in the EAROM as part of the preset information. As more then one broadcasters can be available on a certain preset more then one CNI number can be registered under one preset. These CNI numbers are used to identify the right broadcatser when EPG features like Watch, Record and Remind are used. If no nexTView provider is available the set will show a nexTView alike screen including a TXT page as soon as the nexTView feature is activated. This TXT page can be set to the TXT program guide if available. Some of the nexTView features as record can still be used in this case.
MG2.1 E

SAA5800 pin description
13
pin nr.
1 2 3 4 5 6 7 8 9 10 11
pin name
IREF_DEC IREF REF+ CVBS0_R CVBS0 CVBS1_R CVBS1 STN/BLACK VDDA VSSA TEST0
Description
Iref decouple Current reference input ADC voltage reference decoupling Reference for video signal 0 Composite video signal 0
I/O Level
I I I I I analogue analogue analogue analogue analogue analogue analogue analogue 3V3 gnd gnd
pin nr.
61 62 63 64 65 66 67 68 69 70 71
pin name
A7 A8 A17 A19 A18 A20 A21 A22 RASn WEn CASHn
Description
Address bit Address bit Address bit Address bit Address bit Address bit Address bit Address bit DRAM Row address strobe Write enable DRAM Column address strobe high byte DRAM Column address strobe low byte External rom access Reset Digital power 2 Digital ground 2 Red Green Blue Blending Data indicator Frame indicator Horizontal display sync Vertical display sync SCL Slow I2C bus SDA Slow I2C bus SCL Fast I2C bus SDA Fast I2C bus Reserved for switching SCAVEM IR Led for Service SDA EAROM SCL EAROM Status SCART 4 Reset audio Sound mute Switch to service default mode Easy link out Fixed Beam Current Switch Off (FBCSO) IR receiver Digital power 3 Digital ground 3
I/O Level
O O O O O O O O O O O digital digital digital digital digital digital digital digital active low active low active low
I Reference for video signal 1 Composite video signal 1 I ADC current reference decoupling Analogue power Analogue ground Ground I I I I
12
TEST1
Ground
gnd
72
CASLn
active low
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
TEST2 TEST3 TEST4 OSCOUT OSCIN OSCGND VDDN1 VDD1 VSSD1 D11 D4 D3 D12 D10 D5 D2 D13 D9 D6 D1 D14 D8 D7 D0 D15 VDDP1 VSSP1 ROM_OEn RAM_OEn RAM_CSn ROM_CSn
Ground Ground Ground 6 MHz Oscillator out 6 MHz Oscillator in Oscillator local ground reference Digital power (connect to VDDD1) Digital power 1 Digital ground 1 Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Periphery power 1 Periphery ground 1 ROM output enable RAM output enable SRAM chip select (FLASH RAM) ROM chip select
I I I O I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O O O O
gnd gnd gnd analogue analogue gnd 3V3 3V3 gnd digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital 3V3 gnd active low active low active low active low
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
EAn RESET VDDD2 VSSD2 R G B FADING DATA/VIDEOn FRAME HSYNC VSYNC P0.0|SCL0 P0.1|SDA0 P0.2|SCL1 P0.3|SDA1 P0.4|RXD P0.5|TXD P0.6|COR P0.7 P1.0|T0 P1.1|T1 P1.2|T2 P1.3|INT0 P1.4|INT1 P1.5|INT2 P1.6|INT3 P1.6|RC5 VDDD3 VSSD3 P2.0|PWM0
I I I I O O O
active low active low 3V3 gnd analogue analogue analogue
O analogue O high active O high active I active low I active low I/0 digital I/O digital I/O digital I/O digital O active low O I/O O I O O I I I I I I digital digital digital active low active low active low active low digital active low active low 3v3 gnd active high
Front detect: Signal I present on front connector Standby PROTECTION +8V6 PROTECTION +5V2 KEYBOARD Status SCART 3 Periphery power 3 Periphery ground 3 Stand-by LED Beam Current protection (BC-PROT) DC protection (DC-PROT) Service mode input Easy link out O I I I I I I O I I I O
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
A16 A0 A15 A1 A14 VDDP2 VSSP2 A2 A13 A3 A12 A4 A11 A5 A10 A6 A9
Address bit Address bit Address bit Address bit Address bit Periphery power 2 Periphery ground 2 Address bit Address bit Address bit Address bit Address bit Address bit Address bit Address bit Address bit Address bit
O O O O O I I O O O O O O O O O O
digital digital digital digital digital 3v3 gnd digital digital digital digital digital digital digital digital digital digital
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
P2.1|PWM1 P2.2|ADC1 P2.3|PROTECTION +5V2 P2.4|KEYBOARD P2.5|AGC P2.6|STATUS3 P2.7 VDDP3 VSSP3 P3.0|LED0 P3.1|LED1 P3.2 P3.3 P3.4 P3.5 P3.6|SERVICE MODE P3.7|P50_OUT
active high active high active high analogue active low 3V3 gnd low: LED on active high active high low active digital
14
Chapter 6: POWER SUPPLY GENERAL
MG2.1 E
Chapter 6: POWER SUPPLY GENERAL
TO DEGAUSSING CIRCUITRY UMAIN 1501 1052 3002 2511 6514 2512 2504 2505
5003
2503
3506
V 1053 3005 3006 220V TO 5V STBY SUPPLY +5V STBY 2100 6006 1002 6008 2008 2006 3007 +5STBY +5STBY
3003 7000 2007
7001 3008 STBY 2009 3009
Fig. 6.1
CL 86532047_005.eps 140798
The power supply has a number of main functions. These functions are dealt with in succession: Mains filter Standby power supply Degaussing picture tube Main supply
Personal notes
MG2.1 E
Chapter 6: POWER SUPPLY MAINS FILTER
15
(fig. 6.1)
MAINS FILTER
The mains filter has 2 functions. It prevents high-frequency signals to be transferred into the mains and it protects the set from lightning damage. C2503 prevents the high-frequency signals, generated by the set, to be conveyed into the mains by shortcircuiting them. In the case of a lightning surge between the 2 phases (differential mode) the energy is immediately bled through this VDR (R3506) to the other phase. In the case of a lightning surge on both phases of the mains in relation to the aerial earth, the mains filter acts as a high resistance (Uemk=L*dI/dT) as a result of which the voltage across the coil increases. If the voltage would increase too much, flash-over across the coil would be the result. In order to prevent this from happening a spark gap (1501) is fitted across the mains filter. When ignited, the discharge current will be discharged via this spark gap. In order to limit the Standby consumption of the set, the main power supply is switched-off completely via a relay. Switch on the main supply: Standby-signal is low T7001 blocks T7000 conducts Relay contact 1002 is closed Main supply is connected to the mains
Personal notes
Switch off the main supply: Standby-signal is high T7001 conducts T7000 blocks Relay contact 1002 is opened Mains supply is isolated from the mains
R3005/6 is the sputtering resistor limiting the inrush current.
16
Chapter 6: POWER SUPPLY STANDBY POWER SUPPLY
MG2.1 E
STANDBY POWER SUPPLY
4 VMAIN = V(2100) UA 5 UMAIN UC 2101 3 1 G
5101
6107 5V STBY Usec 2104
3102 3101 UMAIN start 6105 7101
D 6 7102 S
3108 6108
UA
ON
OFF
UD Nx5V UMAIN t IPrim
t Isec
t0
t1
t2
Fig. 6.2
CL 86532047_006.eps 140798
MG2.1 E
17
Stand-by
The Standby power supply is a power supply of the SOPS type (self-oscillating power supply). The supply voltage is controlled through the controlled switching of the oscillator: Burst mode.
the gate as a result of which the fet will go into conductivity. This change is immediately fed back to the gate via the co-coupling coil, as a result of which an avalanche effect is created, driving the fed into saturation. As the gate voltage of the fet may maximally be 20V the feedback voltage must be limited. To solve this problem a CLAMP/LIMITER is added. CLAMPER : If the feedback voltage is negative D6105(15V zener) will conduct, and a current Iclamp will flow which will charge C2101 until the maximum negative value is reached. Because of this the co-coupling signal is elevated to -0.6V. LIMITER : If Ua is positive D6105 will zener, limiting the gate potential to the zener voltage of 15V. Remark: The gate potential is limited between -0.6V and 15V
Time interval t0-t1

At t0, the gate of fet 7102 receives a positive pulse. Because of this it is driven into conductance and Umain will be transposed across the primary coil of the transformer 5101, resulting in a linear increasing current running through the coil. The voltage across the co-coupling coil Ua is positive and will keep the fet in conductivity via C2101/R3102 for some time. The slope of the primary current is determined by the self-induction of the coil and the magnitude of the supply voltage. The maximum current is time-dependant t0-t1. The time is determined by the voltage across resistor R3108// 3118. This voltage is a measure for the current and if it increases above 1.4V, transistor T7101 will be driven into conductivity and consequently connect the gate of 7102 to earth. The timeduration t0-t1 (and as a consequence the maximum primary current) is inversely proportional to the value R3108//3118. At R3108//3118=7E5: Iprim_max=190 mA. The secondary coil has a negative voltage during the interval (t0-t1) as a result of which diode D6107 blocks.
Time interval t1-t2

Here the gate of fet T7102 is connected to earth via T7101, as a consequence of which the fet is driven into block state. This sudden current interruption causes the primary coil to be excited. The voltage on the drain of the fet increases. The secondary voltage Usec becomes positive. This causes D6107 to conduct, resulting in a secondary current. All energy which was stored in coil L5101 during t0-t1 is transfered into the load. Because of the transformer characteristics (from secondary to primary) a voltage difference will be transposed across the primary and the co-coupling coil. --> N * Usec where N is the winding ratio The voltage across the co-coupling coil Ua is negative and will keep the fet in blocked state.
Time t2
At t2, the current through the secondary coil dropped to 0 A. As a consequence, the voltage on the secondary and the primary coil decay and the coil is excited again. All voltages change polarity and through positive feedback due to the co-coupling coil the fet is driven into conductivity. The cycle is initiated once again. In order to start the oscillator, a start resistor R3101 is connected to Umain. This resistor will transpose a small voltage onto
18
MG2.1 E
6103
5102
5101 6107 5V STBY

UMAIN
2104
UOUT
RL
2101 3101 3102 3117 G 7101 7100 6105 3108 2102 3111 3106 7103 6108 3113 3109 3104 7104 6104 22V -20V 3114 3115 D 7102 S
3103 3107
Fig. 6.3
86532006_007.eps 190298
FEEDBACK STABILISATION (fig. 6.3 + 6.4)

The Standby Power Supply always oscillates at maximum power. The only limiting factor is the maximum primary current which has been pre-set with R3108//3118. Uout is determined by the ratio of R3113, R3114 and R3115. If the voltage across R3114 exceeds the threshold voltage of the diode of the optocoupler 7104 (1V) or, in other words, Uout exceeds 5V, the transistor of the optocoupler conducts. Through T7103, the feedback signal is amplified and ultimately when T7100 conducts, the gate of the fet is at earth potential. Because of this, the oscillator stops and the secondary voltage Uout decreases. Since there are no capacitors and there is a high amplificationfactor in the feedback circuit, the feedback is ultra-fast. This is why the ripple on Uout is minimal. The negative supply voltage (-20V) used in the feedback circuit originates from the co-coupling coil and is rectified through D6103. This has a stabilising value (in ratio to Uout). This output is loaded with R3111 in order to get a more stable output. Stabilisation is not effected through duty-cycle control but through burst-mode of T7101 Burst-mode is load dependant. (fig. 6.4 a+b). If the power supply is less loaded, the secondary voltage will have the tendency
to increase more rapidly. If the load on the power supply increases, then the oscillator stops less often, right up to the moment that the oscillator is operating continuously: Maximum load. If the power supply is now loaded even more, the output voltage will decay. The maximum load is determined by the maximum primary current set by R3108//3118.
MG2.1 E
19
5.01 Uout 5V 4.99 15V Ugate Fig. a 0V
Uout
5.01 5V 4.99 15V
Ugate Fig. b
0V
Fig. 6.4
CL 86532047_007.eps 140798
Remark concerning Safety Components (see fig. 6.3)

If the optocoupler would fail, the secondary voltage increases. This would have disastrous consequences since many ICs are fed with this 5V. In other words, very expensive repairs would be required. We already know, that the negative supply is directly dependent upon the secondary 5V, as a consequence of which the negative supply will increase proportionally as the secondary voltage increases. If the negative supply in the mean time reached -30V, D6104 will start to zener and as a consequence T7101 will start conducting. Basically, D6104 will take over the stabilisation task of the optocoupler, however, with a considerable spread. --> From -20V to -30V is a 50% increase : Thus Usec will increase from 5V to max. 7.5V For performance reasons R3117 is implemented. Together with the parasitic capacity of the gate of the mosfet, the switching speed of the mosfet is influenced (slowed down). As a result there will be some dissipation in the mosfet.
Personal notes
20
Chapter 6: POWER SUPPLY PICTURE TUBE DEGAUSSING CIRCUIT (fig. 6.5)
MG2.1 E
PICTURE TUBE DEGAUSSING CIRCUIT (fig. 6.5)
+5V-STANDBY
220K
3010
3011
3012
10K
BC847B
1K
BAS216
3016 7011 3017 47R 100R 6011 BAS216 7012 BC847B 6012 BAS216
6010 BAS216 BC857B 7013
6015 2 9584 1010 6014 JW
BAS216
1K
3015 100R
3014
7020
5501
2010
9515
3013
12u
2K2 2011
BC337-25
2509
470n 2506
100n
Rs Rp 3 +t 3 Rp
Rs SS +t
0303
5502
9516
12u
Vmains
3018
Fig. 6.5
86532006_049.eps 180298
PICTURE TUBE DEGAUSSING CIRCUIT(fig. 6.5)

When the mains-switch is used, the picture tube is degaussed. The relay 1010 will be closed through the one-shot circuitry and initially a considerable current will flow through the degaussing coil. Because of the temperature dependent resistors (PTCs 3506 and 3507) this current will rapidly decay to a minimal residual current. Since this residual current serves no purpose for degaussing and only consumes energy, the relay will isolate the degaussing circuit after about 20 to 30 seconds. R3506 (Rs) and R3507 (Rs) have a low ohmic value when the relay 1010 switches in. A peak current will flow through the degaussing coils. R3506 (Rs) and 3507 (Rs) will heat up, their resistance increases and the current decays to practically zero. R3506 (Rp) and R3507 (Rp) are thermally coupled to R3506 (Rs) and R3507 (Rs). These assure that R3506 (Rs) and R3507 (Rs) stay hot and thus high-ohmic. One-shot circuitry: When the set is switched on with the mainsswitch, +5V standby will start up. When the Standby Power Supply reaches 1.4V T7011 and T7020 will conduct. Through this, relay 1010 is energized, and degaussing can start. In the mean time C2010 is charging via R3010. When Uc exceeds 2.1V (be-junction of T7012, D6012, T7014) T7012 conducts and will switch on the thyristor-circuit (T7013, T7014). --> T=R3010*C2010=220k*220F=48 sec. The maximum voltage is 5V, so 2.1V is reached in about 1/2 T or in 24 sec.
Via D6010, R3016 the base voltage of T7011 is bled away, causing the relay to trip via T7020. Via D6011, R3017 the voltage Uc can never exceed 1.7V and likewise the control voltage of the thyristor falls away (this to limit power consumption in Standby-mode). --> Service Tip: To test if the degaussing circuit operates properly, R3016 could be disconnected.
100n
3507 1
3506 1
220u
1K
7014 BC847B
MG2.1 E
Chapter 6: POWER SUPPLY FFS POWER SUPPLY
21
FFS POWER SUPPLY
PRINCIPLE OF FFS POWER SUPPLY
+300V D C 7540 g d s Rb
Ugate 12V
U bat
Udrain 480V 300V 0V I prim
time
time
I sec
time
7520
7556
Usec 150V 0V -340V
time t0 t1 t2 t3 time
BLOCKGENERATOR 40kHz
OPTO-COUPLER
Fig. 6.6
CL 86532047_008.eps 140798
GENERAL
The FFS (Fixed Frequency Supply) is an isolated power supply using a transformer. Feedback from the output is effected with an optocoupler. The operating frequency is 40Khz and stabilisation is achieved by regulating the duty-cycle. The power supply is short-circuit proof and has over-, voltage- and over current protection. The FFS supplies the following voltages: +Vs (+16V) and -Vs (-16V) max 2.3A 8V6 max 0.5A 5V2 Vbat (141V) supply for the line deflection circuit and derived from that the supply for the tuner (33V)
and C. As the voltage across C is constant (Ubat) the voltage across the secondary coil is constant and a linear decreasing current will flow. All the energy stored in the transformer during t0-t1 is supplied to the load. Since the supply must be isolated from the mains, a transformer is used. This causes a transformer reaction to occur from the secondary to the primary coil during interval (t1-t2), causing the drain-voltage to increase to 300V+(N*Ubat)=480V were N is the winding ratio. At t2 the current through the secondary winding decayed to 0. The voltage across the secondary coil now becomes 0V, as a result of which the drain-voltage of the fet decreases to 300V. The capacitor now supplies energy to the load. At t3 the fet is again forced into conductivity, and the cycle starts anew.
PRINCIPLE OF FFS POWER SUPPLY (fig. 6.6)

At t0 a positive pulse reaches the gate of the fet, forcing T7540 in conductivity. The primary coil of the supply transformer will have 300V across it, causing a linear increasing current. The maximum current depends on the time-duration t0-t1. During the interval t0-t1 the duty-cycle is controlled via an optocoupler. The secondary coil now has a negative voltage causing the diode D to block. At t1 the negative pulse arrives at the gate of the fet, it blocks and de drain-voltage increases. The secondary voltage becomes positive, D conducts and a current will flow through Rb
22
Chapter 6: POWER SUPPLY FFS Power Supply
MG2.1 E
FFS Power Supply
6218/6220 VCC 4 3 2 12 7540 G S 1201 6425 VCC DEMAGN 5525 13 8 14 9 15 5226 2222 6213 1 D 2221 6223 7308 2201 8V6 2228 t -16V 5225 5V2 6222 2234 32V 1221 5550 11 10 2220 6219/6221 t 2203 -16V -32V V12 1220 2202 +16V V11 16V t0 t1 t2 t3
7212 MC 34063A DC-DC CONVERTOR CONTROL
6567 17 5567 2568 VBATT (140V) 2234 18 3569 VTUN (33V)
Fig. 6.7
86532006_010.eps 190298
PULSES ON THE TRANSFORMER 5550 (fig. 6.7)

During the time t1-t2 the fet 7540 blocks. The voltage on pin 17 of the transformer is stabilised to Vbat. All voltages have a fixed relation to this Vbat and are thus also constant. Only at overload conditions Vbat decays and so do all the secondary voltages. At that point in time, all diodes conduct, allowing the capacitors to charge up. During t2-t3 the capacitors supply energy to the load. The derived voltage, Vcc and Vdemag are used by the duty-cycle IC. Across each diode a capacitor is connected parallel for EMCreasons. At the 8V6-supply line a diode has been included in the earth route of 8V-stabiliser, increasing the stabilising voltage of 8V by 0.6V. For the 5V2 a special 8-pin DCDC converter is provided (MC34063A). Note: Due to possible overvoltage of +5V2 or +8V6 a lot of damage could be caused into the set. For this reason an OVPcircuitry has been added. The heart of ths OVP-circuitry is thyristor 7580. If triggered it will interrupt fuse 1201, causing 5V2 and 8V6 supply lines to be 0V. This will be sensed by the uC and the set will be switched to protection mode.
Personal notes
MG2.1 E
23
FFS Power Supply
3227
7212
6 (0,22E) 3225 7
3k3 3228 100k 2226 100n
5226
5225
+5.2V
MC34063
16V
3 6222 2234
2227
Fig. 6.8
CL 86532047_009.eps 051098
5V2 power supply (fig. 6.8)

The 5V stabilisation is done with a series-connected DCDCconverter. Principle: With IC7212, the 16V is switched with a frequency between 50 and 80 kHz. The duty-cycle control is dependent upon the supply voltage and the load. Operation: The supply voltage is inputted to pin 6 of IC 7212. The on-time of the switching transistor in the IC is dependent on the supply voltage and input current. This generates a dutycycle controlled square-wave voltage at the output of the IC. With the built up duty-cycle square-wave voltage, energy is built up in coil 5225, which is transferred to the load during the blocking state of the internal switching transistor. The IC will control the supply voltage until pin 5 has a voltage of 1V2. As a consequence of this, C2234 is charged via diode 6222. C2234 takes care of smoothing the 5V2-voltage. The diagram: Depending on the input current across R3225 a voltage will be measured. When it exceeds 0.3V, an over-current protection will be activated via pin 7 as a consequence of which the output voltage decreases. In the IC the 16V is switched with a frequency determined by the capacity connected to pin 3 (C2227). Through pin 5 the output voltage is fed back. There is a DC-feedback (via 3227) and an AC-feedback (via 3228 and C2226, integrator).
Personal notes
24

7520 MC 44603 15 3536 10 25 7 31 CURR SENSE + COMP FOLD BACK + 2.5V 2.5V 16 3537 10K DC PROT 13 3535 2535 820p 3539 10K 3556 100E 1 2538 2n2 2 7555 + 3538 1K 3 2.5V 3558 2K7 3559 470E 14 7556 +V +VB OPTO COUPLER Vbat 3555 160K 3570 100E 6571 5 S R FLIP FLOP Q
BUFFER
MG2.1 E
FFS Power Supply
REF
6570 STANDBY 3572 2K2
7550
3571 10K
2570 10n
Fig. 6.9
CL 86532047_010.eps 140798
IC MC 44603
THE OSCILLATOR (fig. 6.9) As Control-IC the MC44603 is used. The oscillator generates a saw-tooth pulse (pin 10), the frequency of which is set to 40Khz by C2531 and R3536.
Personal notes
MG2.1 E
25
FFS Power Supply
U10 OSCILLATOR 4.5V SET
Sct
UBAT UBAT 2V UOUT (PIN3)
RESET
UOUT (PIN3)
I PR
TIME
Fig. 6.11
CL 86532047_012.eps 140798
STABILISATION (fig. 6.9/ 6.10/ 6.11)

Vbat is controlled and stabilised to 141V with R3559. This control/stabiliser for Vbat ensures that also all secondary voltages are controlled and stabilised. Via a voltage devider circuitry, Vbat is fed into IC 7555. This is a reference-IC consisting of a transistor, the current of which is determined by the voltage originating from a comparator. This comparator is controlled through an internal reference voltage of 2.5V. The current through the transistor in IC7555 is also the current through the diode of the optocoupler. The voltage on pin 14 of Control-IC determines the duty-cycle on the output pin 3. The lower the voltage on pin 14, the larger the duty-cycle. This input is controlled by the optocoupler to stabilise the supply. The reference voltage on pin 16 is 2.5V and is determined by R3537. If the output voltage increases, the voltage on the reference of IC7555 increases as well, resulting in an increasing current through the diode of the optocoupler. The transistor of the optocoupler is more conductive as a result of which the voltage on R3538 increases. The voltage on pin 14 of IC7520 increases as a result of which the voltage on pin 13 decreases. The opamp is controlled via its inverting input while the gain amounts to: --> Gain R3535 / R3539 =1.5 Via a comparator the decaying voltage is compared with the current sense of pin 7. The reset pulse comes earlier, causing the flip-flop to change over earlier. This means that the conduc-
tivity time of the fet is shortened and that the output voltage will drop to its pre-set value. (fig. 6.11). The supply of the diode of the optocoupler originates from pin 13, transformer 5550. The 5V Standby is also used to supply the diode, so that the stabilising circuit will also work during start-up (otherwise the fet 7540 would be damaged).
26
MG2.1 E
FFS Power Supply
0043
6542 5542
*
2543 2n2
33K 3544 GND-SS
BYD33J 2542 220p
5544 90n
* CE422V
4 2544 2n2 3 2 13 p7
DRIVE
5550
11 10 12
5545
1 14 680R 3545 15 16 8 9 17 18 5567 p19 6567 BY229X-800 2568 6525 BYD33D 5525 2u2 3548 47R 100K 3568 15K 3569 22K 22K 330R 3234
+33V
2540
220p
* 7540 STW8NA60
1K
6545
BYV28
2541
470p 3541
2545
100K
3520
22K 3517
p6 BZV85-C5V6 6572
100p
Vbat
3540
3546
BZX79-C22
RES
SENSE
6520
2520
*
9540 9539 3537
3547
470p 2569 47u 3566
220u BZX79-C22 1N4148 6523 9523 6522 2525
2527 1n
3527
*
16
Vref
33R
* *
**
100n 2524
+16V
Rref
Vcc Iref Vref UVLO1 SUPPLY & enable INITIALIZATION BLOCK 18V
REFERENCE
2521 3531 1K2 100n
6521 BYD33D
3530 1R
3521 82K 2532 82p p10
8 Vdem in 0V2
DEMAGNETICATION
p20
MANAGEMENT Vdem out Iref
BLOCK
3532
Vosc prot
3536 2531 1n 22K 3579 1R p11
0V 9 Sync OSCILLATOR Vosc 10 2V6 CT 2V5 RF standby Iref 15 12 R Pstandby 0V

STANDBY
(REDUCED FREQUENCY)
Vc
2 16V
3526
2523 3518
2526 470p 3524 10R TCDT1102G 6524 BYV10-40 5 7556 1 3553 4K7 DRIVE 3552
Set Latch Reset
BUFFER
OUTPUT 3
*
1V6 p8
3567
7520 MC44603
2V5
16V9 1
5205
V0
GND Vovp out
4 0V
VREG 100R 2224 Vbat 100R 10K 2538 3538 3539 3556 2n2 1K 3557 3558 2K7 160K 3555
THERMAL
SHUTDOWN
Vref
Vcc
*
V0
2.5V
2V5 VOLTAGE 2535 3535 14 FEEDBACK
ERROR
OVERVOLTAGE MANAGEMENT
AMP
CURRENT SENSE
OVERVOLTAGE
*13
2V5
E/A OUT Dmax & SOFT-START CONTROL CURRENT SENSE INPUT Iref
PROTECTION UVLO1
6 2V1
470p
2528
FOLDBACK FOLDBACK INPUT
2555 3n3 2557 7555

1
Vref
Soft Start & Dmax
1V3 5
0V2
11
1V4
* * TL431CLP
3
3525 3523 2522 1n 3512 3522 220K
*
3529
*
3533
2K2
p9
3519
3559 2533
2
1M
*
V0
470R Vbat-adjust
SENSE
Fig. 6.10
CL 86532069_013.eps 051098
MG2.1 E
27
SLOW START and MAX DUTY-CYCLE (fig. 6.10)

When switching on the mains-switch, the start voltage for the IC is supplied by R3520 and C2525. When the supply is switched on, the primary of the transformer supplies the supply voltage of the IC via D6525 to pin 1. When switching on the supply, the output voltage Vbat is 0, forcing the supply to start with maximum duty-cycle, which would result in the peak current through the fet increasing too much. This is prevented by installing C2533 to pin 11. The voltage on pin 11 determines the maximum duty-cycle and is determined by a resistance R3519+R3533. By placing a capacitor across this resistor during starting, the voltage on pin 11 is virtually 0V and hence the maximum duty-cycle very small. This is known as a slow start.
Personal notes
OVER-CURRENT PROTECTION and FOLDBACK (fig. 6.10)

Over-current: The voltage across Rsense (Rsense = R3540// R3546//R3547) is a measure of the current flowing through the primary coil of the transformer 5550. This voltage is inputted to pin 7 of IC7520. Internally in the IC the maximum current is limited via the "current sense threshold" - pin of the IC (pin 7). Max. allowed voltage is 1V. The maximum current through the primary amounts to: --> 1V / 0.195 = 5A. If the power supply is loaded even more, the output voltage will decay. Foldback: During an overload condition, the primary current is maximally 5A. If the load increases more, the output voltage will decrease. This decrease in voltage is introduced via pin 8 TR5550, D6525, D6523, R3525, R3523 to pin 5 IC7520. If this voltage drops to below the foldback threshold of 1V, automatically the "current-sense threshold" is adapted. A decreased current-sense means that the power supply supplies less current and consequently also less output voltage. This results in an avalanche effect, causing the supply to rapidly trim down.
OVER-VOLTAGE PROTECTION (fig. 6.10)

When the voltage on pin 6 of the IC exceeds 2.5V the supply will be switched off. The voltage decays and the power supply will therefore start-up again. This is called hick-up of the power supply. This phenomena occurs when the feedback loop is interrupted.
28
MG2.1 E
FFS Power Supply
U DRAIN 480V 300V
0V
.8 IC7520 (Udem-in) PV
U GATE
t0 TIME
Fig. 6.12
CL 86532047_013.eps 140798
DE-MAGNETISATION SUPPLY TRANSFORMER (fig. 6.10, 6.12)

To avoid the fet 7540 from switching on too early, pin 8 of IC7520 (Control-IC) is offered information originating from pin 8 of Supply Transformer 5550 via R3521. The de-magnetisation level from the IC is set at 65mV. As long as this level is exceeded the fet will not again be driven into conductivity state. This means that the process waits until the transformer has passed on all energy to the secondary coil. In fig. 6.12 this is from t0 onwards.
Personal notes
THE OUTPUT (fig. 6.10)

Pin 3 of IC7520 is a high-current totempole output. This implies that the output resistance in both the 'on' and 'off' state is low, which is beneficial for the switching speed.
DC-PROTECTION / STANDBY (fig. 6.9)

When the DC-protection (Sound) is activated, T7550 conducts, as a result of which the current through the optocoupler increases considerably. This means that the supply voltage is trimmed back to 0V. This protection is activated when a DC component would find its way to the speakers.
MG2.1 E
29
ID 5550 6567 V Batt x = Power dissipation off 7540 (P1) without C and R
2504
3544
2569
VD
2543 2n2
6542
2542
7540
2544 2n2 5545
ID x = Power dissipation off (P2) with C and R
2540
3545 680E
6545
2545 100p
VD
3546// 3540// 3547//
6572 P2 < P1
Fig. 6.13
86532006_014.eps 190298
SWITCHING-OFF VOLTAGE (fig. 6.13)SWITCHING-OFF VOLTAGE (fig. 6.13)

The switch in the power supply is a mosfet which is rated for the maximum drain-source voltage of 600V. Without an additional circuit, a steep switching-off reactance would sweep the voltage to 700V. In order to protect the mosfet an extra circuit has been incorporated. Operation: When the mosfet blocks, the drain voltage increases, D6542 conducts and C2543 is charged. The reactance is dampened. When the mosfet conducts, C2543 is discharged through R3544, the primary coil of the transformer and the mosfet itself. C2543 is charged to a DC voltage of 500V(average value). R3544 dissipates about 2.2Watt (~ 11mA*200V). Disadvantage: R3544 is dissipating. Advantage: Mosfet is protected.
Personal notes
DV/DT LIMITOR (fig. 6.13)

Too rapid voltage fluctuations on the drain of the fet give a disturbed picture. When switching off the fet, very steep slopes are generated. These increases are limited without causing the fet to dissipate too much. When the fet blocks, C2544 is charged via D6545, limiting the slope. When the fet conducts C2544 is discharged through R3545.
30
Chapter 7: Tuner & IF Tuner
MG2.1 E
HIP
TUNER SAW VIDEO 2/3 IC7501 TDA9320H CVBS 13 HA/VA 60/61 I2C SAW SOUND 63/64 SOUND IF 5 49 50 R OTC G B LMN I2C BG 36/41 37/42 38/43 22 19 51 LF AM 5 V U V
Fig. 7.1
CL 86532047_014.eps 051098
A new tuner is introduced for MG2.1E: UV1316 Mk2. The tuner is I2C-controlled and has three bands: low/mid/high (see table).
Mid High
156 - 440.9375 MHz 441 - 865.25 MHz
Tuner Low
UV1316 Mk2 44 - 155.9375 MHz
The tuning is done by varying the current that flows via pin 9. The maximum voltage on this pin is limited by a zenerdiode of 33V. The voltage is derived from the Vbat via two resistors of 22 kohm. The IF frequency is dependent on the transmission standard:
SYSTEM
IF FREQUENCY MHz
Picture/soundcarrier sc1 5.5 6.5
Picture/soundcarrier sc2 5.74
Picture/soundcarrier dig 5.85 5.85
DESTINATION
B/G L
38.9 38.9
WEST EUROPE WEST EUROPE (only France) WEST EUROPE (only France) WEST EUROPE (UK) EASTERN EUROPE
L'
33.95
6.5
5.85
I D/K
38.9 38.9
6 6.5 6.24/6.74
6.55 5.85
MG2.1 E
31
Search command
Start search
1 Tuned to TV transmitter?
3 System L'?
2 System L'?
L'frequencies covered
6 Step 5 MHz in 62.5 kHz sub-steps
4 Step to next L' frequency?

N
5 Step 250 kHz in 62.5 kHz sub-steps
7
Y
8
N Y
Video recognition?
System L'?
9 Video recognition?
N
10 12 Find frequency
Y
13
Y
AFC crossing?
Video recognition?
14
Y
Frequency found?
N (Bad AFC crossing detected)
11 Step 62.5 kHz
(No more video identification)
Fig. 7.2
CL 86532047_015.eps 140798
32
MG2.1 E
'sc1/sc2' are the analogue sound carriers and 'dig' stands for the NICAM (digital) sound carrier. The IF-filter is integrated in one SAW (Surface Acoustic Wave) filter. The type of this filter is different, dependent of the standard(s) that has to be received. One extra filter (5103) (40.4 MHz) is necessary for L/L' sets with 6.5 MHz sound to suppress the neighbour channel. Two SAW filters are used: One for filtering picture-IF and the second-one for sound-IF. The output of the tuner is controlled via an IF-amplifier with AGC-control. This is a voltage feedback from pin 62 of the HIP to pin 1 of the tuner. AGC take-over point is adjusted via the service alignment mode 'Tuner AGC'. If there is too much noise in the picture, then it could be that the AGC setting is wrong. The AGC-setting could also be mis-aligned if the picture deforms with perfect signal. The IF-amplifier amplifies too much. The video IF-signal is fed to pins 2/3 of the PLL-controlled IFdemodulator. The voltage controlled oscillator of the PLL is adjusted via the service menu 'IF AFC'. If the alignment is correct then the displayed frequency in the installation menu is the same as the applied frequency from a generator. The external coil L5108 connected between pins 7/8 is used as reference. The demodulated IF-video signal is available at pin 10 of the HIP. In this videosignal there is a rest of soundcarrier, which is filtered by the sound traps 1106/1107. Then the signal is again fed into the HIP on pin 12 where the group delay can be corrected, dependent on the norm which is received. On pin 13 the CVBS-signal becomes available which is used for further processing in the television. Via TS7502 the signal is supplied to external 1 and back into the HIP on pin 14 to the source/ record selection. (See chapter 9 for further description.) In short: Video signal on pin 10, back-in on pin 12, out again pin 13, back-in on 14. So there are various pins where the video signal can be checked. To realise quasi split sound the IF-signal is fed to the HIP on pin 63/64 via SAW-filters 1104/1105. The FM (or AM for L-norm) -modulated signal is available on pin 5 and is fed to the audio demodulator MSP3410 (see chapter 8). TUNING PROCEDURE (fig 7.2) For search tuning two inputs are used: 1. Is there video recognition (sync detection (phi-1 lock) in the HIP) 2. Is there a carrier (AFC crossing; PLL-lock) The complete tuning procedure is illustrated in fig 7.2, but this is all inside the HIP. There is also automatic switching for the different videosystems.
Personal notes
MG2.1 E
Chapter 8: Sound MG2.1E Possibilities
33
+5V
+5V
7770 SEDSP *ONLY DOLBY 16 SSL 12 SSR 4800 A SUBWOOFER OUT (*DOLBY SETS) C AMPLIFIER
SELECT AUDIO CINCH 1/2
BLACK CINCH
RESET AUDIO P
57 7774 100 F 8 62
MSP CLOCK CLOCK
4801 9 SUBW DOLBY DSP 20 C 40/41
30 29 36 28
OUT WS IN
7751 MSP3410 61 SIF HIP LF AM
I2S bus 6 TV is center 7775 SW3 OPTION 13 7753 SW2 A VL AUDIO-OUT (CINCH) 2
18
25 23 ADC
DSP NICAM
LR AMPLIFIER
28 EXT1 EXT2 EXT3 FRONT 30 31 33 34 36 37 39 40
DAC
56 MAIN 57 LR 50 CL 51 14
DAC
7752 SW1
EXT2
DAC
47 TUNER 48 59 HP 60
EXT1
DAC
HEADPHONE
1751
Fig. 8.1
CL 86532047_016.eps 051098
There are three sound possibilities: Non DOLBY Virtual DOLBY (without surround speakers) Full DOLBY Prologic 5 channel ( optional 5+1)
DBE Equaliser Soundprocessing
In virtual DOLBY the surround signal is fed to the left and right to create the virtual effect. The surround signal is also fed to (black) cinch-outputs and the customer can connect surround speakers. Because of the different possibilities there are various versions for the amplifiers: No Dolby; DBE for L and R; no subwoofer No Dolby; L and R squeeters; subwoofer with DBE Virtual Dolby, no subwoofer Virtual Dolby, subwoofer Dolby prologic, no subwoofer (corded surround) Dolby prologic, subwoofer (corded surround) Future: Optional for cordless Dolby
The MSP3410D can demodulate the IF-sound signals: 2 carrier FM-sound and NICAM. It can also post process AM-sound. The sound-IF may be present between 0 and 9 MHz.
SYSTEM
FIRST CARRIER 6 Mhz 6 Mhz 5.5 MHz 5.5 MHz 5.5 MHz
SECOND CARRIER 5.74 MHz -
NICAM CARRIER 6.552 MHz 5.85 MHz 5.85 MHz 6.25MHz -
I mono I NICAM BG mono BG 2CS BG NICAM L NICAM M D/K Satellite Satellite
The HIP delivers the IF sound (FM) or the AM low frequent, also the external audio signals are fed to the MSP3410D with SEDSP (SAA7712H) Sound Effects Digital Sound Processing IC. The SEDSP is used for: DOLBY PROLOGIC decoder Incredible surround (also virtual Dolby)
4.5MHz 6.5MHz 6.5MHz 7.02MHz
7.2MHz
34
MG2.1 E
The MSP3410 has four analogue outputs: Main sound with Dolby decoded left/right Audio out to the cinch output (variable or constant) Audio out from tuner source is fed to EXT1 Headphone out
Personal notes
DOLBY PROLOGIC DECODING: The DOLBY PROLOGIC decoding (see fig 8.1) takes place in the SEDSP (SAA7712H) IC7770. The digital signal comes from the MSP3410 (IC7751) and the complete DOLBY PROLOGIC processing takes place in IC7770. Via the digital bus (I2S) the decoded left/right is fed back to the MSP3410 where L/R data is converted to analogue signals. The SEDSP has also two analogue outputs for Surround and one for Centre. The surround is fed to (black) cinch outputs. When the SEDSP is defective then there will be no sound. <- Service Tip In the circuit there is already an option for DIGITAL DOLBY (AC3). The biggest difference for AC3 is the stereo surround. The SEDSP has also the DBE (Dynamic Bass Enhancement) feature inside. DBE can influence the signal for the subwoofer. Another feature in the SEDSP is 5-band-equalizer for 4 channels. Only 3 channels are used (not for surround). There is a slow switch-on for the SEDSP via C2831 on pin 8. This means that with start-on the outputs are muted. In the diagram of fig 8.1 three switches are mentioned: Via SW1 audio signal is fed to EXT2 (VCR-scart). The EXT2-output is the same as the main sound, except when EXT2 is used as an input. In that case SW1 is switched and the front-end audio signal is fed to EXT2 (this to avoid oscillating sound). With SW2 audio is switched for the cinch outputs. From pins 56/57 the variable level is available; at the pins 50/51 constant level is present. There is a third input possible for surround. This is also variable level and the surround signals are fed to the pins 2/15 of IC7753. In this way there is an option to use an external amplifier for surround to have more surround volume. SW3 makes it possible to use the complete tv as centre speaker. Thus all speakers in the television give centre sound and at the cinch outputs variable L/R has to be available.
MG2.1 E
Chapter 9: Hip, I/O select, Video processing HIP
35
FE CVBS
CVBS FE OUT CVBS FRONT-END CVBS 1 (SC 1) R G
7501/TDA9320 H
CVBS INT CVBS 1 R1 IN G1 IN B1 IN FBL1 IN YOUT UOUT VOUT Y U V
(SC 1)
B FBL
CVBS 2 (SC 3) R G (SC 2) B FBL
CVBS 2 R2 IN G2 IN B2 IN
HIP
CVBS PIP PIP OUT CVBS FDS CVBS TXT
FBL2 IN
COMB OUT CVBS COMB Y COMB IN C COMB IN CVBS OUT CVBS SC2
Y/CVBS 3 (SC 2) C (SC 2)
Y/CVBS 3 C3 Y/CVBS 4 C4
Y/CVBS 4 (Front) C (Front)
Fig. 9.1
CL 86532047_017.eps 051098
General
The HIP (TDA9320H) has various inputs (see also fig 9.1). Full matrix switch with: 2 CVBS inputs 2 Y/C (or additional CVBS) inputs 1 CVBS front end input Two RGB inputs and 2 status-inputs
from front are fed to the HIP and front detection is also fed to the OTC. EXT 1 and 2 are both full SCART: Thus CVBS and RGB. The RGB-selection is done in the HIP. If both SCARTS have a RGB-input then EXT2 has the highest priority. EXT2 is meant for VCR and has therefore some additional signals in relation to EXT1. EXT2 has also the possibility for Y/C in/out and Easylink-Plus (P50). Y in/out is with pins 20/19 and chroma in/ out with pins 15/7. This is different in the GFL-chassis, there was only pin 15 used for C-in and C-out. Easylink is handled via pin 10 of the SCART and this is a bi-directional communication. From chassis GFL onwards Easylink was introduced. The next features are supported by Easylink: Signal quality and aspect ratio matching One touch play One touch text PIP Preset download WYSIWYR Automatic Standby
Outputs: Three separate switchable outputs can be used: 1 YUV-output is fed to the PICNIC 2 CVBS outputs: One for PIP/FDS (Full Dual Screen) and the other for output to EXT2 to have WYSIWYR (What you see is what you record)
For I/O-switching is referred to fig 9.3. The external signals are fed directly to the I/O part of the HIP with status from pin 8 of SCART. On the HIP there are two status inputs available (pins 15,17) with two voltage levels: 4:3 -> 2V2 16:9 -> 5V5
With Easylink-Plus is added: Country and language installation System Standby Intelligent set top box features NextView download Timer record control VCR control feature
The CVBS status from the third SCART (only CVBS-in) is fed to the OTC, because on the HIP there are only two inputs. This is also for SCART 3 detection of 4/3 and 16/9. The input signals
36
MG2.1 E
7501/TDA9320H
IF
Tuner
GD
HIP
PIP TXT Main Y C Y C Y C CVBS main
read_status 1
Ext 1
(Easylink)
read_status 2
Ext 2
PROC
FBX
TOPIC
HOP
proc
Ext 3
COMB Comb control Peaking IIC
Front
FBL1 FBL2
OTC
set_rgb_main
rgb1 rgb2
front_ detect
Easylink Interface
Fig. 9.3
CL 86532047_019.eps 051098
Video processing
In the HIP there is video identification but this is not used. The sandcastle-pulse of the HIP will not be used for synchronisation. The HOP will generate synchronisation signal derived from the feature box-(Picnic)signals. If a VCR is connected, there is also an automatic correction for macrovision. This is active for the external sources and the presets 0, 90-99. The Y/C switch in the HIP is controlled by the HIP itself (no external voltage). When a PAL- or NTSC-signal is received then the Y/C from the combfilter will be used and when SECAM is received, this will be processed internally. The comb filter has to be switched for PAL/NTSC by two lines: SYS1/SYS2 (pin 25 and 27 of the HIP). The voltages depend on the colour system that is received. The combfilter needs the subcarrier frequency as sample clock. That is why the subcarrier is coming out on pin 30 of the HIP.The truth-table for colour standard as function of SYS1/SYS2 is described:
Personal notes
colour standard PAL-M PAL-B/G/H/D/I NTSC-M PAL-N
SYS1 LOW LOW HIGH HIGH
SYS2 LOW HIGH LOW HIGH
MG2.1 E
37
SC
HA
VA
FBL EXT 1 R G EXT 2
CVBS/TERR
VIDEO IDENT
Y/CVBS
SYNC PROC
RGB/YUV SWITCH
B FBL EXT 2
Y FROM I/O Y/CVBS Y C Y/C SWITCH C/CVBS CHROMA DEC Y FILTERS Y DELAY Y
U YUV SWITCH U DELAY V
V Y FEAT U FEAT V FEAT
HIP (TDA 9320H) CHROMA PART

CVBS OUT Y C
COMB FILTER
SYS 1 SYS 2
Fig. 9.4
CL 86532047_020.eps 051098
PAL M/N is not used in Europe, so for European countries there are only two possibilities. The chrominance decoder in the HIP is full multistandard (see fig 9.4): PAL/SECAM/NTSC. Four different crystals can be connected to the pins 54-57 without any alignment. The crystals are also used as a reference for the synchronisation. The start-up of the sync is determined by a digital control circuit which is locked to the reference signal of the colour decoder. This crystal may only be replaced by the original one. If just a crystal is taken the internal capacitance is different and the effect will be that there is no colour. In the HIP a sync separation has been integrated; the HIP delivers the Ha and Va 50Hz/60Hz to the PICNIC. On pin 59 there is the 1fh sandcastle but this is not connected to any circuit and only used internally for the colour demodulator. The 2fh-sandcastle signal is generated by the HOP.
Personal notes
38
Chapter 10: Featurebox (integrated on SSP) 100 Hz featuring
MG2.1 E
M E M 1
BUS A Y DEC U DEC V DEC HA VA
BUS B
BUS C
BUS D Y FEAT U FEAT V FEAT HD1 VD1
PICNIC/7609/SAA4978H IC 100Hz CONFIGURATION

2
Fig. 10.1
CL 86532047_021.eps 140798
100 Hz featuring (fig 10.1)

In the MG-chassis the featurebox is integrated on the small signal panel. A new IC is used for the 100Hz conversion: the PICNIC. In the PICNIC the following functions are present: The ADC (was FRONTIC) The DAC (was ECOBENDIC) The 100Hz conversion (was ECOBENDIC) The Panorama mode (was PANIC) The noise limiter (DNR) (was LIMERIC) The contrast improvement (was SMARTIC met CPU)
Personal notes
All these functions are integrated in one IC SAA4978H, 160 pins QFP
Function 100 Hz Digital Scan
Chipset one memory + PICNIC Prozonic + two memories + PICNIC
fig 10.1 10.2
MG2.1 E
39
M E M 1
P R O Z N I C
M E M 2
BUS C Y DEC U DEC V DEC HA VA
BUS D Y FEAT U FEAT V FEAT HD1 VD1 PICNIC/7609/SAA4978H
IC DIGITAL SCAN
Fig. 10.2
CL 86532047_022.eps 140798
Picnic
The main task of the PICNIC is the conversion from 50Hz to 100Hz for YUV and HV-sync (see fig 10.1). In the PICNIC also integrated is the CPU with a ROM. This internal ROM is not always used and also external ROM IC7616 can be used. At a later stage it is the intention to use only the internal ROM. In the PICNIC there are three 9 bits ADCs present for Y,U,V. For digitising the Y (luminance) 9 bits are used, to realise a more detailed picture. The 9 bits are only internally used. Via dithering the 9 bits are reduced to 8 bits and that data is stored into the memory. The data in the memory is fed back to the PICNIC and via undithering the data is again reproduced 9 bits for processing. U/V (colour difference signals) is also sampled with 9 bits. These two 9 bit datastreams are multiplexed to 4 bits datastreams. This reduction can be allowed as the perception for colours by the human eye is less sensitive as for luminance. Sets with high specification have auto-DNR. The auto-DNR works together with the TOPIC who takes care of the sharpness control. The effect is:
is used to store one frame. For sets with digital scan the PROZONIC (IC7608 SAA4990H) has been added with two memoryICs (IC7606/7607 TMS4C2973 or IC7614/7615 MSM5412222). The housing of the TMS...version (smaller) or MSM... is different which can be seen in the print layout. In this way various memory suppliers can be used. The PROZONIC SAA4990. This is an abbreviation of PROgressive scan Zoom and Noise reduction IC. The functions of the PROZONIC are: Field rate up-conversion (50-100 Hz or 60-120Hz) Noise Reduction (DNR, Digital Noise Reduction) Movie Phase Detection Progressive Scan (= digital scan) Variable Vertical Sample Rate Conversion Synchronous No Parity Eight bit Reception an Transmission interface (SNERT-bus)
Checks that can be done for fault finding: If 3V3 is present for the PICNIC then the 12 MHz should work (1601). YUV has to be fed to the PICNIC via TS7610/ 7611/7612 and also Ha/Va (50 Hz sync) via R3628/3633. On the SNERT-bus (pins 1/2 of the PICNIC) there should be activity. Check the reset of the PICNIC pins 6/7. Via pin 6 the memory is reset. The YUV outputs are available at pin 12, 14 and 15.
signal good bad
DNR low high
sharpness high low
Digital Scan featuring

To the PICNIC external ICs are connected dependent of the features. If MG2.1E has only 100Hz then only one memory-IC
40
Chapter 11 The TOPIC (The most Outstanding Picture Improvement IC)
MG2.1 E
YIN
LUMINANCE VECTOR PROCESSING
Y DELAY
SPECTRAL PROCESSING
YOUT
U/V IN
COLOUR VECTOR PROCESSING
U/V OUT
LIGHT SENSOR AD3
MEASUREMENT AND DETECTION
WINDOW
SANDCASTLE
TOPIC/7402/TDA9178
Fig. 11.1
CL 86532047_023.eps 140798
Introduction
The TOPIC is an optional IC. It is not used in all MG2.1E sets. The first introduced sets will not have it. The PICNIC delivers the 100Hz YUV signal to the TOPIC (IC7402 TDA9178). The TOPIC (fig 11.1) can improve various items and has therefore various functions available: Luminance transient processor Chrominance delay circuitry Spectral processor Colour vector processor Measure and detection circuitry Measure window
Personal notes
The different items are explained now:
MG2.1 E
41
PAL-SIGNAL FIELD A
VIDEO INPUT
SANDCASTLE INPUT
V-PULSE INTERNAL
NOISE DETECTOR MEASURE
Fig. 11.2
CL 86532047_024.eps 140798
1. Luminance transient processor The luminance is measured within a window (internal controlled). Depending on the luminance contents, improvements are done to get the most details. This is called analogue histogram processing. The window can be controlled via I2C. Also black stretch is built-in to improve the contrast of the luminance signal. For this the lowest level of the signal is detected in the TOPIC. In the same window (as above) the black level is detected. If this black level differs from the blackclamping level, then the difference is partly compensated (black level offset). Another improvement for luminance is the gamma correction, but this is depending on the black level offset. 2. Chrominance delay This is necessary to compensate timing differences between luminance and chrominance. 3. Spectral processor The sharpness can be improved: Emphasise big black/ white transients with a "steepness control" and emphasise on details with "peaking control". CTI improves the colour transients. For saturated red and magenta the luminance sharpness is increased (colour dependent sharpness). 4. Colour vector processor Skintone correction: This is special for NTSC to mask transmission/HUE-control.
Green enhancement: Green with low saturation is more amplified. Blue stretch: Colours close to white are changed a little to blue, to get a brighter impression.
5. Measurement and detection (fig 11.2) The noise detector measures the noise in the frame flyback during one video line without videosignal (=black). The TOPIC takes the average of 20 frames. This average value can be read via I2C. The noise measurements is switched off when the videosignal comes from a VCR. These signals are not reliable. The TOPIC has three A/D converters. Only two of them are used. On pin 3 of IC7402 a voltage comes in from the light sensor. This voltage depends on the daylight-luminance. During daytime a higher contrast-level is needed than in the evening when it becomes dark. This is most convient for the customer. On pin 5 of IC7402 the beam current information (derived from EHT-info) is coming-in. Dependent of the beam current, YUV-levels can be adapted. Also the number of high frequencies are measured and there is a detection when the picture contents changes very rapid. All this information together is used for autoTV.
42
MG2.1 E
6. The TOPIC uses internal a window where the luminance pattern and blacklevel is measured. This window is defined such that subtitles, logos or black bars (for letter box) have no influence on the results measured. Results in the middle of the window have more influence on the postprocessing. On pin 1 of the TOPIC the sandcastle from the HOP is fed which is used as reference for timing. The clamping/blanking and vertical retrace are used.
Personal notes
MG2.1 E
Chapter 12 The HOP High-end Output Processor
43
IC 7300 / TDA9330H
Y, U, V FEAT RGB PIP RGB TXT VIDEO CONTROL
R G B
8V6
SUPPLY
TDA 9330 AH
HOP
DAC
HOP DAC
HD VD
GEOMETRY
EW-DRIVE VD NEG VD POS LINE DRIVE
SC 1FH/2FH
VFB HFB
DYN PHASE CORR.
FBCSO
PROT - FLASH - BEAM CURRENT - LDP
Fig. 12.1
CL 86532047_025.eps 140798
HOP
In the HOP the videoprocessor and digital deflection processor are integrated. The main functions of the HOP are: RGB interface for PIP (or dual screen) Second RGB interface for OSD/TXT Control of saturation, contrast and brightness Black/blue stretch (optional because this is already done by the TOPIC) Peak white limitation Cut-off control and white drive Beamcurrent limitation
Personal notes
44
MG2.1 E
7300 / TDA9330H
Fig. 12.2
CL 86532047_026.eps 051098
MG2.1 E
45
See figure 12.2 The YUV-input is converted to RGB-outputs. The RGB and fast blanking signals from PIP (or dual screen) are fed to the pins 30-33. In the HOP the RGB is converted to YUV, so there can be switched between PIP and the main picture. On pins 35-38 the RGB and fast blanking from the OTC (OSD and TXT) are inserted. Blue stretch measures the amplitudes of the three RGB signals. If one of these colour signals become more than 80% of the nominal value, then the amplification of red and green become a little less. This to reach a higher colour temperature. On pin 43 there is a peak white limiting signal-line (PWL). If the beamcurrent (EHT-info line) raises then the EHT-info voltage will decrease. There are two ways to control the PWL: Average limiting via R3420/C2422 Fast limiting via TS7424
Personal notes
46
MG2.1 E
BEAMCURRENT SWITCH-OFF PRINCIPLE
HOP
TDA9320H
40
Amplifiers
41
42
B CRT
(Mirror) BLC-INFO
44
3428 6429 5V6
1mA 3429 1mA 5mA FBCSO 7438 3430
Fig. 12.3
CL 86532047_027.eps 051098
Beam current switch off circuitry (see fig 12.3) Switching of TV due to mains switch off, or due to a flash (one with such energy-dissipation that the +141V is loaded significantly). Via pin 29 of the HOP (IC7300) the +141V is sensed via FBCSO-circuitry (see diagram A2 of chassis manual). At switch-off set, pin 29 of HOP-IC becomes high and the deflection will be on top of the picture tube (overscan). A current of about 7 mA will discharge the picture tube. Discharge takes place till the powersupply reaches the POR-level. Switching the TV to Standby (fig 12.3): First the HOP goes to Standby, the deflection will be positioned in top of the picture tube (overscan). The slow stop (is explained further on) of the HOP is started and a current of 2mA discharges the picture tube. The slowstop lasts 42 msec and the discharge takes 38 msec . Control of the discharge current is realised via pin 44 of the HOP. The current to pin 44 is constant during discharge (1 mA). A discharge of 2 mA flows through the RGB-amplifiers, 1 mA can flow through D6429, R3429. In the HOP a different cutoff control is introduced (fig 12.4 and 12.5):
Personal notes
MG2.1 E
47
U FEEDBACK
UWB UWG UWR UCOB UCOG UCOR IANODE 8 A FRAME 1 20 A FRAME 2
Fig. 12.4
CL 86532047_028.eps 140798
Two measurements are used: First a current of 8 uA (for cutoff) and second a current of 20 uA (for white drive) is fed to pin 44 of the HOP. This is done with the measurement pulses during the frame flyback. During the first frame three pulses are generated to adjust the cut-off voltage at a current of 8 uA. During the second frame three pulses with a current of 20 uA are generated (for white drive alignments). (If possible use here an oscilloscope picture measured at one of the cathodes of the CRT. Measure both frames!) <-- Service Tip With these two measurements the complete characteristic for the RGB-amplifiers is adjusted. So at start-up there is no monitor pulse anymore. At start-up the HOP measures the pulses which comeback via pin 44. The RGB-outputs have to be between 1.5V and 3.5V. If one of the outputs is higher than 3.5V or one of them lower then 1.5V the RGB-outputs will be blanked. Geometry part in the HOP (see fig 12.2): Synchronisation Line drive (HD) Frame drive (VD pos/neg) East/west drive Guarding protections
Personal notes
48
MG2.1 E
U FEEDBACK
R GB
R G B
FRAME 1
FRAME 2
Fig. 12.5
CL 86532047_029.eps 140798
Personal notes
Personal notes
MG2.1 E
49
16sec;; 50% TON TIME DRIVE SIGNAL 0 VEHT [kV] 32 15 15kV
START HOP SLOW START LINESTAGE
150msec TIME
Fig. 12.6
CL 86532047_030.eps 061098
All geometry control is done via I2C and the data is stored in the NVM (IC7008) of the SSP. Line drive is derived from an internal VCO of 13.75 MHz. As a reference an external resonator is used of 12 MHz (1305). The internal VCO is locked with the HD-pulse which comes from the PICNIC. The PHI-2 part in the HOP receives the HFB (pin 13) to correct the phase of the line drive. The EHT-info is supplied to pin 14 to compensate picture breathing depending on the beam current. (This is not used at the moment, therefore EHTcompensation in the service menu is put to zero)<--Service tip Picture breathing is compensated via the east/west circuitry. EHT varies also dependent of the beam current. For widescreen without load this is 31,5 kV and with load (1,5mA) 29,5 kV. On pin 9 the VFB comes in. If the VFB disappears, or takes longer then the sandcastle (SC) blanking, then the picture will be blanked (intern) by lifting the DC-level of the SC. The SCsignal is available for pin 9 of the TOPIC. Slow-start (fig 12.6) is realised in the start/stop part of the HOP (pin 5/29). The horizontal drive starts with a very short 'on'-time. The start-frequency is 2 times higher as the normal drive-frequency. The HOP also takes care of the slow-stop (fig 12.7). If the HOP is put to Standby then it takes 42 msec to reduce the T_on to zero.
Personal notes
50
MG2.1 E
16sec (; 50%) TON TIME DRIVE SIGNAL 0 TIME
VEHT [kV] 32 15 32kV
STOP HOP SLOW STOP LINESTAGE
38ms
42ms TIME
Fig. 12.7
CL 86532047_031.eps 061098
Protections/detections: Flash detection (see figure 17.4). When a flash occurs, the EHT-info will become negative very fast. Via D6340/6341 TS7341 starts to conduct. This makes pin 5 of HOP high. When pin 5 of HOP is high then the output (Hdrive) is immediate stopped. If H-drive stops then also pin 5 will be low again, which will reset the flash detection. A bit (FLS) will be set in an output status register, so via the microprocessor it can be seen when there was a flash. This FLS-bit will be reset when the microprocessor has read that register. Beam current protection. Via D6350 and TS7351. If the EHT-info becomes too low then D6350/TS7351 will start to conduct making the BC-prot high. The BC-prot is sent to the microprocessor who puts the TV into protection mode with a delay of 1 sec. An error code will be generated. Line drive protection (LDP) The current through the east/ west stage is measured. When this becomes too high then the protection has to be activated. Therefore the protection is fed back to pin 5 of the HOP. If LDP is activated the FLSbit will also be set but the software can detect whether is was a flash or a protection. In this case the FLS-bit will remain high and the set goes into protection. An error code will be generated. HFB protection If the HFB is not present then this is detected via the HOP. The microprocessor puts the TV into protection and reads a register in the HOP. An error code will be generated.
VFB protection If vertical flyback is missing or if the VFB takes longer than the V-blanking of the sandcastle, than the picture will be blanked and there is also a bit set in the HOP. The microprocessor detects this and puts the TV into protection. An error code will be generated.
The vertical oscillator is synchronised with the VD from the PICNIC. With R3323 the positive slope of the charge current is set, with C2323 the negative ramp of the current. The outputs (pins 1 / 2) are differential voltages Vdpos and Vdneg. These create differential currents which are fed to the vertical output stage. At pin 3 the E/W-drive is available. Pin 4 is a feedback input for the EHT-info. Depending on the beam current the vertical and horizontal deflection is kept constant to prevent pumping of the picture. Frame rotation (only for 16:9 sets): For frame rotation a control voltage is used from pin 25 of the HOP. This voltage can vary from 0.4V till 4V.
MG2.1 E
Chapter 13: PTP & SCAVEM The RGB amplifiers (fig. 13.1)
9336 3337 8K2 2337 7330 TDA6111Q 33n 6

VDDH VFB
5336 3331 120K +200A 9
2334
6U8 2331 4p7 3330 1K8 3332 2K7 3 VIN

VOC 8 IOM 5 CURRENT SOURCE GND VDDL MIRROR V BIAS VCN 7 MIRROR MIRROR
68p
3336
B-VC 3333 47R 3n3 2333
390R
2330
22p
680p
+12Vsvm
MIRROR
3338 3339 1K 2 2332 4n7 0031 2336 33n 4 +12V
1K
2338
1 VIP
DIFFERENTIAL STAGE
+3V
BANDWIDTH-LIMITING
7338 BC857B
3360 BLC-INFO 1K 4p7 2360 3361 82K 3363 6372 3347 3341 120K 7340 TDA6111Q 33n 6
VDDH VFB
5346 8K2 +200A 2341 9 4p7 3340 1K8 2K7 3342 6355 BAV21 6335 BAV21
VOC 8 IOM 5 CURRENT SOURCE MIRROR
KB 11
2344 2347 +200A
6U8
68p
3346
G-VC
MIRROR MIRROR
390R
BZX79-C6V8
9346
2340
22p
47R 3n3
2348
680p
1 VIP
DIFFERENTIAL STAGE MIRROR
BAV21 6345
3 VIN
V BIAS
VCN 7
3343
2343
+12Vsvm 3349 3334

GND VDDL
3348 3335 680R
0299-E 0298-E
KB 11
Blue
1K 1K 4 0032 2346 33n 3344 100R 3364 +12V 2 100R 4n7 2342
+3V
BANDWIDTH-LIMITING
7348 BC857B
KG 6
0299-D
Green 3345 680R

KR 8 KG 6
0298-D
0299-C
Red 3355 680R

KR 8
3354 100R
0298-C
9356 3357 3351 +200A 120K 2357 7350 TDA6111Q 33n 6 9

VFB VDDH
5356 8K2 2351 4p7 3350 1K8 3352 2K7 3 VIN

VOC 8 IOM 5 CURRENT SOURCE GND VDDL MIRROR V BIAS DIFFERENTIAL STAGE MIRROR VCN 7 MIRROR MIRROR
2354
6U8
68p
3356
R-VC 3353 47R
390R
2350
22p
2353 3n3
2358
680p
1 VIP
+12Vsvm 3359 1K 2352 4n7 4 0033 2356 33n +12V 2
3358
1K
BANDWIDTH-LIMITING
+3V 7358 BC857B
Fig. 13.1
86532006_055.ai 190298
51
52
MG2.1 E
As RGB amplifiers, three ICs type TDA6101 (or TDA6111) are used. Each amplifier consists of: A differential amplifier of which the positive input is connected to a reference voltage of 3V. An output stage.
Personal notes
The gain is determined by R3330 and R3331 (for the blue amplifier). The beam current comes from pin 5 and is added from the three colours in R3360. This is the measuring pulse information of the leakage current and the cut-off stabilisation. In the case of a high beam current, the RGB amplifiers concept without heatsinks are dampened by switching a capacitor, connected to the input, to earth via a transistor. This only occurs in the case of noise. This prevents the RGB amplifier of getting too warm.
MG2.1 E
Chapter 13: PTP & SCAVEM Principle of Scavem
53
Principle of Scavem
RES 2412
7414
2411
22n 2424 RES
100u 2423 RES
+13VD
3405
10R
2400
18K
3418 330R
RES 3420
9383 1 U10 3
2405 3p3 7400 BF199 B-VC 3403 2K2 2403 22p 2404 47u 5404
22n 2407
3417 3415 10R SC2 10R
BD140-16
3411
56K
10R
0383
3 2 1
7405 BF370
2420
330p
3408
47R
1K
5u6
3416 1K8
100u
3410
22u
+12Vsvm
2 5414 4
1N4148
1N4148
1u 2422 SC1
6410
6409
9384 SC3 2409 22n
47p
RES 9381 5400
3414 3400 +VD 4K7
3412
1K
180R
3404
18p R-VC 3401
2410 22n
56K
2K7 2402
100n 3407
330R
2K2 2406
330R
3419
3421
3406
G-VC
3402
56p
7415 BD139-16
3409
RES 2408
3413
4R7
3K3 2401 15p
1K
Fig. 13.2
CL 86532069_015.eps 010998
Scavem
The Scavem-circuitry is implemented in the layout of the picture tube panel. It is thus not an extra module. Scavem means SCAn VElocity Modulation. This means that the horizontal deflection is influenced by the picture content. In an ideal square wave, the sides are limited in slope by a limited bandwidth (5 MHz). Scavem will improve the slope as follows: At a positive slope, a scavem-current is generated which supports the deflection current. The first half of the slope the spot is accelerated and the picture is darker, while at the second half of the slope, the spot is delayed and the slope becomes steeper. At the end of the slope, the scavem-current decays to zero and the spot is at the original position. An overshoot occurs which improves the impression of sharpness. At the negative slope, the scavem-current counteracts the deflection. During the first half of the slope, the spot is delayed, the slope becomes steeper. During the second half the spot accelerates, the scavem-current is zero at the end of the slope.
Personal notes
TO SCAVEM COIL
54
MG2.1 E
Fig. 13.3
CL 86532047_032.eps 140798
MG2.1 E
55
Operation
Via the three resistors R3401, R3402, R3403, red, green and blue are added together and offered to the emitter TS7400. On the collector of this transistor, configured in a common base, the sum of these 3 signals is obtained. Via the emitter follower formed with TS7405, this signal is conveyed to the differentiator C2407, R3408 and R3409. Only the high frequencies are differentiated (small RC). The positive and negative pulses of this signal drive respectively TS7415 and TS7414 into conductivity. The DC setting of the output stage is set by R3410, R3411, R3412 and R3413. The working voltage of the transistors is settled at half the supply voltage. At the positive section of the pulse, the current flows through R3409, C3409, the scavemcoil and TS7415. At the negative section of the pulse, the current flows through R3409, C2409, de scavem-coil and TS7414. Both currents flow through R3409 and the voltage across this resistor is a measure for the scavem-current. This voltage is fed back via R3408, D6409 and D6410. In this way the feedback operates with an approx. 0.6V threshold. Because of this, the scavem-current is limited to 50mA.
Personal notes
56
Chapter 14: The line deflection Deflection
MG2.1 E
0315
1 2 3 4 5 6 7 8 9
A1-11 LINEDRIVE GND-DRIVE

+8V6 Vbat
5400 39u
2400
EW-DRIVE LDP A3-3
47u
2437
150K
3428
2u2
6407
6437
BYD33D
FBCSO
BYD33D
VDNEG A3-4
470R
3413
VDPOS
GND
+5V2
+13VD
6408
2436
100u
3432
3429
47K
47K
GND EHT-INFO
BAS216 7437 BC857B
L4 5411 L3 7421
150K
3437
3416
3415
GND 3436 FBCSO 3K3
1u
2418
*
1 5410 2 4 4416 47R CU15
9408
* *
2417
* *
5419 90n 9419
2438
3439
3438
33n
33K
3411
*
2412 33n
GND
3417
GND
GND
GND
* *
2414
2413
22u
33n
2416
L2 3406 47K 2411 L1 3414
GND
2409
47p
7409 BC547B
1N4148
6410
2408
BAS216
470R
6409
3407
3404
GND-DRIVE 3609
HFB
BZX284-C5V6 6609
10K
10n LINEDRIVE
100R 7411 BC635
7408 BC337-25
BAT254 2609
6608
3K3
From Linestage 2419/2420
GND
GND
GND
47p
47p
Fig. 14.1
CL 86532069_014.eps 051098
Driving the line output stage (fig. 14.1)

The HOP, which is located in the small-signal panel, supplies the line drive pulses to the base of T7409 on the large signal panel via connection 0315. When the H-drive pulse is high, T7409/7408 conducts. A constant DC voltage is applied across L5410. A linearly increasing current will start flowing through L5410. When switching on the set, the current through L5410 is supplied by the 5V2 power supply and taken over by the 13Vd from the line stage. When the H-drive pulse becomes low, 7408 blocks and as a result of this L5410 generates a high, positive voltage onto the collector of T7408. This voltage is transformed to the secondary coil and in that way drives T7421 into conductivity. Because of the storage time of the line transistor, L5410 cannot immediately transfer its energy, which may result in the collector of T7408 being subject to high voltage peaks. These voltage peaks are dampened by R3411 and C2412. When the H-drive pulse becomes high, T7408 is again driven into conductivity and pin 3 of L5410 becomes low. Through this, the line transistor blocks. L5411 serves to rapidly switch off T7421. Starting the line stage is done with the slow start principle. The HOP generates line driving pulses with a small duty-cycle and a higher frequency (about 2 x the normal line frequency); the "off"-time here is constant and the "on"-time increases gradually until the duty-cycle is 50% (normal condition). The transfer from start to normal condition takes ~ 150ms. When switching off, the same procedure is followed, but now in reverse sequence.
Personal notes
MG2.1 E
57
Deflection
PRINCPLE OF THE LINE OUTPUT STAGE
5430 I Defl
5430 I Defl
141V t1 t2
141V t2 t3
7421
6423
2425 2421 + 41V
+ 2420 6424
Line defl. + 2433 -
100V 7421 141V

+ 2420 -
6423
2425 2421 + -
Line defl. 2433
2426
5422
41V
6424
2426
5422
Fig. 14.2.1
86532006_019.AI 190298
Operation of the line output stage

period t1 - t2:
Start status: C2433 is charged to max. 141V(Vbat) TS7421 is driven into conductivity
Personal notes
We have 141V across L5422 and the deflection coil, divided according to their respective inductance, 100V across the deflection coil and 41V across L5422. This results in the spot moving from the centre of the picture to the right. (As long as C2421 is not charged to the voltage across L5422, D6424 will conduct). The voltage across C2421 is the same as for L5422 (- 0.6V).
period t2-t3:
The moment T7421 stops conducting, the flyback starts. The current through the line deflection coils continues to flow through C2425 and C2421. The current through L5422 continues to flow through C2426 and C2421. The energy stored in the line deflection coil is passed to C2425, and the energy of L5422 to C2426. An oscillation will occur (on average no current flows through C2421 and thus the voltage across this capacitor remains constant).
58
MG2.1 E
PRINCIPLE OF THE LINE OUTPUT STAGE
5430 I Defl 141V 141V
5430 I Defl
t3 t4
t4
t5
7421 + 2420 -
6423
2425 +2421 41V 2426
Line defl. 2433
7421
6423 + 2420 6424
2425
Line defl. 100V 141V 41V
6424
5422
+ 41V 2426
+ 2421 - 2433
5422
Fig. 14.2.2
86532006_021.AI 190298
period t3 - t4:
As for the period t2 - t3; but now the current flows in the opposite direction, since the voltage across C2425 and C2426 is higher than the voltage across C2433 and C2421.
Personal notes
period t4 - t5:
The coils want to maintain the negative current and charge the capacitors negative. Because of this, D6424 and D6423 conduct. There is 100V across the deflection coil and 41V across L5422. As both diodes conduct, we may consider the voltage to be a constant value. A linear current flows with the same changing characteristics as in period t1 - t2. The spot now moves from the extreme left to the centre of the picture. Before the current becomes zero and the spot is located in the centre of the frame, TS7421 reverts back into conductivity. First a short negative current will flow. The cycle starts anew.
MG2.1 E
59
Deflection
LINEARITY, S- AND MANNHEIM CORRECTION

HDEFL 5430 (Lot)
3609 HFB
2410
3431 2431
3430
2424
5421
5411 2417 3417 HDRIVE 7480 E/W-GATE
7421 2420
HDEFL - 1IN
3434
3435
2419 3489 6483
6421
2425
6425 6426
2433
5480
5422/24 6422 3 2426 4
2421 2 5422/24
3483 3484
Linearity Correction
Caused by serial losses in the line output stage
3425
3426
Mannheim-effect S-correction
X Y X
White horizontal lines
X>Y White vertical line
Deflection centre
Fig. 14.3
86532006_017.AI 190298
The deflection circuit

The linearity correction
A constant voltage on the horizontal deflection coil should result in a saw-tooth current. This however is not the case as the resistance of the coil is not negligible. In order to compensate for this resistance, a pre-magnetised coil L5421 is used. R3430, R3431 and C2431 ensure that L5421 would not excite because of its own parasite-capacitors. This L5421 is called the linearity coil.
the picture width. The east-west drive signal will ensure the largest picture width in the centre of the frame. Here the largest correction is applied.
Suppressing the Mannheim effect

When clear white lines are displayed, the high-voltage circuit is heavily loaded. During the first half of the flyback (t2 - t3), the high voltage capacitors are considerable charged. At that point in time, the deflection coil excites through C2425. This current peak, through the high-voltage capacitor, distorts the flyback pulse. The flyback pulse is branched from C2419 and sent to the HOP via plug 0311. This causes synchronisation errors, causing an oscillation under the white line. During t3 - t5 C2424 is charged via R3434 and R3435. At the moment of the flyback, C2424 is subjected to the negative voltage pulses of the parabola as a result of which D6425 and D6426 are conducting and C2424 is switched in parallel with C2433. This is the moment the high-voltage diodes are conducting. Now extra energy is available for excitation through C2425 and the line deflection. As a consequence the flyback pulse is less distorted.
The S - Correction
Since the sides of the picture are further away from the point of deflection than from the centre, a linear saw-tooth current would result in a non-linear image being scanned (the centre would be scanned slower than the sides). For the centre-horizontal line, the difference in relation of the distances is larger than those for the top and bottom lines. An S-shaped current will have to be superimposed onto the saw-tooth current. This correction is called finger-length correction or S-correction. C2433 is relatively small, as a result of which the saw-tooth current will generate a parabolic voltage with negative voltage peaks. Left and right the voltage across the deflection coil decreases, and the deflection will slow down; in the centre, the voltage increases and deflection is faster. The larger the picture width, the higher the deflection current through C2433. The current also results in a parabolic voltage across C2421, resulting in the finger-length correction, proportionally increasing with
60
Chapter 14: The line deflection East-West modulator
MG2.1 E
East-West modulator
HDEFL 5430 (Lot)
3609 HFB
2410 6 5430 (Lot)
3431 2431
3430
2424
5421
5410
5411 2417 3417
7421
2420
3434
3435
2419 3489 6483
6420
2425
6425 6426
2433
HDRIVE 7480 E/W-GATE 5480 5422/24 6422 3483 3484 3 2426 4 2421
2 5422/24
3425
3426
Fig. 14.4
86532006_015.AI 190298
The East-West modulator

The moment TS7480 is driven into saturation, C2421 will discharge during the flyback. As a consequence of which C2421 must be charged again during the scan via the conduction diode D6422 (as long as C2421 is not charged to the voltage across L5422, D6422 will conduct). The current in the deflection coil is therefore larger than the current flowing in L5422 (12). The voltage across the deflection coil increases, so the picture width increases. When TS7480 blocks, C2421 will not discharge anymore and the voltage across C2421 will remain constant. The result is that the voltage across the deflection coil is minimal. The voltage across the EW-coil, however, is maximal. The EW-coil (L5422) consists of a transformer: As the current through the coil 1-2 increases (smaller picture width), the current through coil 3-4 decreases. Because of the transformer characteristic a higher voltage will be subjected to coil 3-4, which will counteract the current. The current will diminish even further. When the current through coil 1-2 diminishes (larger picture width), the current through coil 3-4 increases.
Personal notes
MG2.1 E
Chapter 14: The line deflection EW-drive
61
EW-drive
EW CONTROL
EW
+13V d(Lot)
3489 3482 2481 3480 2 5480 1 6483
7480 3481 EW_DRIVE
2480
3485 7484-B
+ -
3486
3488
3493 LDP
6480
3483 3484
2482
Fig. 14.5
86532006_016.AI 190298
The EW Drive
The EW drive signal originates in the HOP and is supplied to TS7480. The shape of this signal determines the various geometric correction parameters: H amplitude EW-parabola EW-corner EW-trapezium
Personal notes
62
Chapter 14: The line deflection EW Protection
MG2.1 E
EW Protection
+13VD
BAV21
5422 4 3
9481
3489
3464
4K7
2481 470p 3480 100K 6479 BZX79-C47 7480 3481
5424
*
5480
4 3 CU15
**
BZX79-C5V6 BZX79-C4V7
GND
GND
6464
3482
47K
*
MTP3055EFI
2480
3485
*
6485 3490 220K
6465
*
3488 1K GND
1K
BZX79-C10
3486 100K
6480
3483
EW
3484
1u
GND
2482
PROTECTION
3498
+8V6
CU20
1 CU15 2
L5
6483
BAS216
6484 BAS216 6486 BAS216
3478 220R GND GND GND GND
220R
7484-B LM358N 7
L6 3493 1K LDP
3491 220K
6 4
2487
10u
2484
3492
4u7
EW-DRIVE
Is_correction
33K
GND
GND
GND
GND
Fig. 14.6
CL 86532069_016.ai 051098
The EW Protection
The EW current is measured via R3483//3484 and an integrator consisting of C2482 and R3486. The average voltage across C2482 is supplied to the protection circuit, built around opamp 7484-B. When the EW-current exceeds a certain value, the LDP line (LDP = line deflection protection) will be made high via this circuit. The LDP line is connected to the HOP and this activates the EW protection. Pin 6 of the opamp 7484 is set to a fixed voltage of 1.1V (derived from the 8.6V), through R3491 and R3492. Pin 5 of the opamp is offered the voltage across C2482. When the EW current exceeds a certain value, then Vpin5 > Vref. The output of the opamp, and thus the LDP line, will become high. The positive feedback via D6485 will cause the protection to stay activated, also when the EW-current decreases. D6484 limits the voltage on the input of the opamp to 0.6V above the supply voltage..
Personal notes
MG2.1 E
Chapter 14: The line deflection Beam Current
63
Beam Current
+200D
+VD
3468
Vbat
2440 1n5 3451
5468
+13VD
0324
1 2
BZX284-C27 3454
2450
100n 1400
3450
6453
3448
3457
47K
6441 BYD33J
*
+VD+dc
EHT-INFO
GND
*
BZX284-C12
* *
GND
+VD
9468 RES
FROM / TO 0224 OF
(GND-D)
3 4 5
HEATER (FILAMENT) +200D
2442
4u7
BAV21 6451
3455
3452
*
GND
* 5430
4
EHT
6454
GND GND
6 3443 6R8
+VD-dc
FOCUS G2
TO CRT PANEL TO 0334 OF
9450
BAS216
TO CRT
470R 6452
3459
2448
3449
3458
2454
100n
2449
10
2457
Is_correction
*
GND
1 3 2 5 8
GND
GND
GND
* 9451
5460 1460
2460 1n5 6460
+13VD
2461
BYV27-200 MP200 2463 1n5 6463 BYV27-200
GND
11
470u
+13V-LOT
GND 9
HFB+13V
3466
GND 5466
3m3
12
2462
L7 HEATER (FILAMENT)
3467
* 9466 *
9452 5462 3463 1R 3462 1R 2465 1n5 6462
-15V-LOT
2466
470u
BYV27-200
Fig. 14.7
CL 86532069_012.eps 051098
Beam Current correction

The EHT-info at point 10 of the LOT is dependent on the value of the beam current and the voltage devider R3450 - 3451 3452. The EHT-info is fed to the HOP to trim the contrast and to compensate for the changes in picture-width as a function of the EHT-info, when the high-voltage is decreased. D6453 and D6454 limit de EHT-info to max. 27.6V. This is required in order to prevent the EHT-info from becoming unduly negative at the junctions of black to white, which would result in an erroneous flash detection. The EHT-info is integrated via C2457 and sent to the gate of the EW-fet (7480) as a DC-voltage to correct the EW-current. Since the internal resistor of the LOT does not have a linear characteristic as a function of the beam current, a strongly changing picture content (for instance a change-over from black to white, or vice versa ) would result in an unstable picture-width correction. In order to prevent this, the integrator resistor has been made dependent on the beam current. In the case of a limited beam current, the EHT-line is strongly positive, causing D6451 and D6452 to conduct; thus R3449 will be switched in parallel with 3457. In order to realise Is-correction because of details in the picture (for instance a thin black line in a white background) parallel to the integrator resistor, a frequency-dependent impedance has been added (R3448 and C2448).
DC shift
Correcting the horizontal deflection frame is done with the DCshift module. The Vd + dc and the Vd - dc are smoothed. Depending on the fitting of 9030 and/or 9031 located on an DCshift panel extra positive or negative DC-current will be sent through the deflection coil. This results in a horizontal shifting of the deflection window.
FBCSO circuit (fixed beam current switch off) (see fig 14.1)
This circuitry is intended to detect voltage drops on Vbat and to send them to the HOP in order for the protection to be activated. The circuit is built around TS7437 and operates as follows: Under normal conditions, the base of TS7437 is at a voltage of Vbat/10. When, as a result of a decrease in Vbat, (when switching off or at a high voltage flash-over) the voltage on the base of TS7437 drops to under 8V, TS7437 will conduct and the FBSCO-line will become high. When Vbat is normal again, the transistor will block again and the FBSCO-line will become low. Vbat and the 8V6 both originate from the same power supply, but the decrease in Vbat occurs faster than a 8V6-decrease. In order to be certain that the transistor will be driven into conductivity before the 8V6 decays, the C2437 circuit has been added. This ensures a quick reaction to a Vbat decrease. The line stage supplies the various secondary voltages signals:
Secondary line voltages (see fig. 14.7)
64
Chapter 14: The line deflection Beam Current

EHT, Focus and Vg2-voltage + 200V for the CRT panel (pin 7 LOT) +13Vd for the CRT panel (pin 8 LOT) +13Vlot for the frame output stage (pin 8 LOT) HFB + 13V for the N/S panel (pin 8 LOT) Heater-voltage (pin 12 LOT) -15Vlot for the frame output stage (pin 9 LOT) Vd + dc (pin 4 LOT) and Vd - dc (pin 7 LOT) for DC shift panel EHT-info (pin 10 LOT). With an increasing beam current, the voltage on pin 10 of the LOT and across C2450 decreases.
MG2.1 E
Personal notes
The EHT-info is used for the following purposes: Via the HOP the contrast can be adjusted down when the beam current is too high. Via the "Is-line" the picture width can be adjusted back when the picture bellows Via the HOP the horizontal shift can be adjusted when the LOT is loaded excessively
MG2.1 E
Chapter 15 The Frame output stage
65
Chapter 15 The Frame output stage
VFB 6617
+13V-LOT
BYD33D 6614 2615 BYV27-200 9614 100u
3614 1K
6619 1N4148
BZV85-C8V2
7600 TDA8177 VB
6
VSUPO
6618
VSUP
FLYB
2613
470p
VDPOS
3613 1K
1 INPOWER AMPLIFIER
FLYBACK GENERATOR OUT 5 THERMAL PROTECTION
4622
5617
VDNEG
3617
820R
2612
470p
3612
GND
2618
100n
2620
VB
VB
3620
10u
2616
100n
2617
220n
10K
220R
3619
1R5
1K
3618
7 IN+
220R
6620
3610
90n
BYD33D
VB -15V-LOT 3611
0325
3 2
3601
3602
3603
1R
1R
VB VB +13V-LOT
VB
Vdefl-1
1R
820R
9621
Vdefl-2
0326
1 2
F-pin
-15V-LOT
220K
3441
2445
470p
3445 4 2 7440-A LM358N
7441 BC547B
HFB+13V
DAC-HOP
3440 47K 3442
0390
1 2
2443
3433
100n
10K
220K
3447
1 +13V-LOT
VB
VB VB 3446 BC557B 7442
2444
1u 3444
VB
VB
33K
-15V-LOT
Fig. 15.1
86532006_048.eps 190298
Output stage
The frame output stage is driven by the HOP which has 2 symmetrical saw-tooth voltages (Vdneg and Vdpos) via connection 0315. The shape and amplitude of these signals are determined in the HOP according to the geometrical settings. The frame output stage is fed with the +13Vlot and the -15Vlot. The output of the amplifier is 0Vdc, so it does not require a coupling capacitor.
Flyback generator
During the scan, a supply voltage of +13V and -15V is sufficient to respond to the slow change in current. The flyback output puts a negative voltage of -15V to pin 3 of IC7600. Because of the voltage drop across D6618, C2615 is charged to 19V. During the flyback the change in current per time unit is much larger so that a higher voltage is required. The flyback generator will generate a pulse of +13V. Added to the charge on C2615 this will give a flyback voltage of 32V.
back to the (-)-input of the amplifier via R3611. The amplitude of the saw-tooth voltage at the input determines the ultimate picture height. By shifting the total input signal upwards or downwards, a vertical shift of the picture is obtained. The vertical linearity is determined by the shape of the saw-tooth voltage. C2612 and C2613 serve to prevent oscillations. C2617 and R3617 form a filter for the high frequencies and in that way also prevent oscillations. Peak voltages at the output, as a result of a possible flash, are dampened by the clamp circuit consisting of C2620, D6620 and R3620. R3618 and R3619 are dampening resistors. If the bridgewire 9621 is omitted, a North South correction panel can be connected with connection 0326.
Frame rotation
Earthmagnetism can cause a certain picture rotation, depending on the position of the TV-set. In order to compensate for this, a picture rotation circuit is built with IC7440 and an amplifier (7441/7442). Via its DAC output, the HOP supplies the opamp 7440 a certain DC voltage (min. 0.4V to max. 4V). The opamp has a gain of ~ 4.7 x . The output of the opamp drives, via TS7441/TS7442, a DC-current through a coil fitted to the CRT (plug 0390). The DAC-voltage has been selected such that the magnetic field generated is of the same strength as the earthmagnetism, however, working in the opposite direction. The DAC-voltage is set during installation of the set via the installation menu. In order to effect a positive and a negative correction the + input of the opamp is set to a DC voltage of 1.7V.
Amplifier
The vertical flyback pulse (VFB) is fed to the HOP via D6619. The output of the amplifier supplies a saw-tooth current through the vertical deflection coil (which is connected to the amplifier with connection 0325). The current through the deflection coil is measured across R3601//3602//3603. This voltage is fed
66
Chapter 16 Audio Amplifiers
MG2.1 E
+VS +7V7 SOUND ENABLE 3751 3750 7790 3752 3749 7740 TDA 2616 Q A= 30db + 3789 2 2756 2732 3732 3733 2733 9 8 A= 30db + 3762 2782 2754 6770 5V 2792 -VS 6769 2V7 2784 -7V7 2757 3763 2760 3783 SUBW 3782 L 3764 A 7796 7761 3765 3786 3768 7762 3770 3767 DC PROT 6768 2V7 2791 6767 5V 3769 5V STBY 2783 +7V7
2730 3730 3731 2731
R SS/C
3766
3788
Fig. 16.1
CL 86532069_011.eps 051098
Introduction
The sound amplifier is formed by one or more integrated power amplifier ICs, sometimes connected via a DBE-filter. Four (4) different configurations are possible: Stereo amplifier with 2 full-range speakers (Non-Dolby) Stereo amplifier with 2 squeeters and subwoofer (Non-Dolby) Stereo amplifier with 2 full-range speakers and 1 centre speaker (Dolby) Stereo amplifier with 2 squeeters, one centre speaker and a subwoofer (virtual Dolby)
speaker. This protection circuit checks the following 3 functions: Via R3765 and R3766 a virtual earth is imposed on point A. When one of the supplies deviates, point A will assume a DC-voltage. In the case point A is positive, T7796 is driven into conductivity. If point A is negative, 7761 will conduct. Conductivity of one of these transistors will ensure that T7762 conducts and that the DC-PROT signal will be high. The DC-prot ensures that the supply is rapidly trimmed back via R3786 and R3788 we also check the derived 7.7V supply-voltages. via R3764, R3763, R3782, R3783 each output of the amplifier is also checked for DC-output. Capacitor C2760 ensures that only DC-signals at point A will activate the protection.
SUPPLY (fig. 16.1)

The supply of the opamps is build up symmetrically and is derived from the +16V and -16V supply. The +7.7V and - 7.7V are derived through two 5V stabilisers (6767, 6770) of 5V. To obtain 7.7V, the earth outputs of the stabilisers are connected to a 2.7V zener (6769, 6768).
TDA2616 AMPLIFIER
The heart of the sound amplifier is the integrated stereo-amplifier IC, the TDA2626. Some characteristics are: The amplifier is set at a 30dB gain. A boucherot-filter is connected to the output of the amplifier to suppress high-frequency oscillations (for L out this is C2757, C2756, R3789) The mute-circuit.
DC-PROTECTION (fig. 16.1)

Because of the symmetrical supply, a DC-blocking capacitor between the amplifier and the speaker is not required. A DCprotection must always prevent a DC-current from flowing through the speakers. This, after all, would be the end of the
MG2.1 E
67
LM833 + 3710 UIN 100K 2710 33n 10K 2711 220n 2715 3713 2716 3711 UOUT
3714
6701 6700
3712
FILTER 1
8K2
FILTER 2
Fig. 16.2
86532006_032.eps 050298
The Sound-enable signal is derived from the microprocessor on the small signal panel and runs to the mute-input (pin 2) of the TDA2616. The sound-enable signal is inverted through T7790, as a result of which at a high level of the sound-enable signal, current is sinked from pin 2 of the TDA 2616 and the IC mutes. This mute is switched in when the set is switched on or off, avoiding a plop being heard.
Personal notes
68
MG2.1 E
AMPLIFICATION FILTER 1 0
50HZ AMPLIFICATION FILTER 2
50HZ
TOTAL AMPLIFICATION COMPLETE FILTER-CIRCUIT 0
50HZ Frequency
Fig. 16.3
86532006_033.eps 061098
DBE (dynamic bass enhancement)

DBE (= Dynamic Bass Enhancement) is a circuitry which extra amplifies the bass tones. This extra amplification is required for sets with a subwoofer and full-range speakers. DBE will only be used on those sets. The basic circuitry: (fig. 16.2+16.3). Filter 1 and filter 2 in fig. 16.2 show a characteristic as displayed in fig. 16.3. This active filter is responsible for the amplification of the low frequencies. To avoid the amplifier from clipping during strong signals, two diodes are fitted across C2716. These diodes will conduct during strong signals, as a result of which feed-back will increase and amplification will decrease (the peak is flattened). It is not noticeable that in that case the DBEfunction is partly disabled, since strong bass-tones do not necessarily require selective amplification.
Personal notes
MG2.1 E
69
NON DOLBY 2 x 15 W
(ANALOG) SSP LSP 3700 DBE 75Hz/+6.5dB 3701 2700 2730 3730
7740
30dB
3V AC
3731
2731
20K
(ANALOG) 3702 2730 3732

30dB
DBE 75Hz/+6.5dB 3703 2702
3V AC
3733
2733
20K
Fig. 16.4
86532006_023.AI 061098
THE 4 DIFFERENT POWER AMPLIFIER CONFIGURATIONS

2X15W: stereo amplifier with 2 full-range speakers (Non-Dolby)
R3700 and R3701 ensure a voltage division of the audio signal from the small-signal panel. To the left and right output, fullrange speakers are connected. This is why a DBE-conversion is performed on both speakers. Before the signals are fed into the amplifier, it will first go through a high-pass filter (fo=30 Hz).
Personal notes
70
MG2.1 E
NON DOLBY 3 x 15 W
7740 SSP LSP 3700 2730 3730
30dB
LSQ
3V AC
3701
2700
3715
3731
2731
20K
3702
2732
3732
30dB
RSQ
3V AC
3703
2702
3716
3715
3733
2733
20K
3718 2714 3717

+
(ANALOG)
7750 2734 3734

30dB
7710 B
3719
DBE 50Hz/+12dB
2712
2719
subwoofer
3735
2735
20K
Fig. 16.5
CL 86532047_034.eps 061098
3X15W: Stereo amplifier with 2 squeeters and subwoofer (Non-Dolby)

The channels left and right are build up in the same way as for the 2X15W. Only DBE is not installed, since we incorporate squeeters instead of full-range speakers and thus do not need a bass signal on L and R. This is also the reason why the highpass filters are configured differently (fo=200Hz). In the case of non-Dolby sets, the small-signal panel only supplies the left and right outputs. If we want a subwoofer-signal, its must be made. Via R3715 and R3716 left and right are added and passed through a low-pass filter. This filter has 2 stages, one 2nd orderand one 1st order-filter. Together they make a 3rd order-filter with a very steep slope at 160Hz. A subwoofer is designed to reproduce the low tones, this is why a DBE-function is added to the circuitry. Before the signal is fed into the amplifier, it first passes a high-pass filter with a cross-over frequency of fo=30Hz. The plug of the subwoofer is turned around, since the signal was inverted in the low-pass filter and must be inverted again to be in phase again.
Personal notes
MG2.1 E
71
3 x 15 W DOLBY
(Including digital DBE) SSP 2K7 750mV LSP 3K9 470E
30dB
7740 L / R
1K
3V AC
L/R
100p
6K8
1n5
20K
3723 2 2 390mV 3704

+
(ANALOG) 2736 3736
7750
7710 A
180K
3705
2704
400mV
DBE 75Hz/+6,5dB
30dB
3725
3737
2737
20K
2,5V
Fig. 16.6
86532006_025.AI 061098
3X15W: Stereo amplifier with 2 full-range speakers and 1 centre speaker (Dolby)
The signal routing left and right is comparable with the non-Dolby version (3X15W), while only the input circuit is different, as the signal-amplitude is only 750mV is (there is already a voltage-divider on the small-signal panel). We do not have a DBEfunction on the large-signal panel, although we do have fullrange speakers. This, because the small signal panels of the Dolby-sets are equipped with a SEDSP with 2 digital DBEs on board, performing the DBE-function digitally. The centre signal is amplified in IC7710-A since the level of the small-signal panel is insufficient. Amplification (factor 2) is done with an opamp. Now the signal is sufficient to use an analogous DBE (the SEDSP only has 2 digital DBEs on board, which are already in use for L and R). Before we feed the centre signal into the amplifier, it is first passed through a high-pass filter with a cross-over frequency fo=30Hz.
Personal notes
72
MG2.1 E
4 x 15 W DOLBY
(Including digital DBE) SSP 2K7 750mV L/R LSP 1K 1 470E

30dB
7740 LSQ / RSQ
6K8
3V AC
1K
4n7
1n5
20K
3723 2m2 390mV C 180K 3704

+
(ANALOG) 2736 3736
7750
7710 A
3705
2704
3725
3737
2737
400mV
DBE 75Hz/+6,5dB
30dB
20K
2,5V 3713 2714 390mV 2706 3707 3717

+
(ANALOG) 3719 2734 3734

30dB
7710 B
3706
2717
SW 390mV
2719
3735
2735
DBE 75Hz/+6,5dB
SW
20K
2,5V
Fig. 16.7
86532006_024.AI 061098
4X15W: Stereo amplifier with 2 squeeters, one centre speaker and a subwoofer (virtual Dolby)
Left, right and centre are comparable with the 3X15W Dolby version, but because a subwoofer with squeeters is used here, these three channels do not require DBE. The high-pass filters in front of the amplifier have a cross-over frequency of fo= 200Hz. The subwoofer signal is comparable with the 3X15W non-Dolby version.Since the digital DBE of the SEDSP (on small signal panel) is used, no analogue DBE-circuitry (or large signal panel) is installed on this amplifier.
Personal notes
MG2.1 E
Chapter 17 Protection structure

3V3 St-by NVM 5V2 I2C3 OTC (3) St-by 5V2 I/O video I/O audio Tuner Picnic Prozonic FBX (10) (11) (5) (50) (51) (77) 8V6 6052 HIP ITT EDRIC LTP (15) (25) (26) (21) 5V2 (68) DC prot (76) AUDIO FBCSO BC (74) (66) fast I2C2 BC info 7438 7351 8V6 7341 + 7484 1V EHT info E/W Hor. defl. HFB 6341 33V
200V EHT FIL -13V +13V -15V
73
ST24E16 (1) ST24E32 (2)
Protectionstructure MG2.1E
(65) slow
I2C1
Mainswitch 1050 IR +5Vst-by 6570 8V6 5V2 +(16V) green red 6051 7021 Mains St-by 5Vst-by
(67) 7050 IR 6571 7000/ 7001
140V FFS
33V
tuner
6350 27V
Vert. defl. VFB
FBSCO
LDP (73)
I2C
RGB
HFB (71) DEFLECTION VFB (70)
6758
Video control
HOP (20)
Fig. 17.1
CL 86532047_035.eps 140798
Protection introduction
In fig 17.1 the protection diagram is drawn. MG2.1E has only one microprocessor (OTC) . The microprocessor and the NVM are supplied with 3.3V, also in Standby mode. The Standbycommand from the OTC is fed to TS7000/7001 that switches on the main power supply via relay 1002. Standby-command is also fed to the power supply for fast switch-off. In case of protection the power supply is switched of via the Standby line. In MG2.1E protection is possible due to 3 possible causes: I2C-related Via the OTC Via the HOP
Personal notes
74
MG2.1 E
I2C drivers
Start
Start cond. OK
Y
Free the bus
5X
Y
Send adres data
General I2C error
Slow (65) Fast (66)
ACKN
Y
Check device
5X
Stop
Bus blocked
Y
Free bus
Device I2C error
Slow TEA 6422 Tuner Picnic Prozonic I/O video FBX PROT (11) (5) (50) (51) (10) (77)
Fast LTP Dolby ITT HIP HOP (21) (26) (25) (15) (20)
NVM-bus NVM (1) (2)
Fig. 17.2
CL 86532047_036.eps 140798
MG2.1 E
75
Protections via I2C

When the TV-set is on then every 200msec a number of registers are refreshed. I2C protection becomes active if one of the SDA- or SCL-lines has short-circuit to earth or there is a shortcircuit between SDA and SCL. Also a missing power supply for one of the ICs will generate an I2C error. There are different device error codes for as well the slow as the fast I2C bus.
Personal notes
76
MG2.1 E
Software filter protections on OTC
Input from DC prot BC prot 8V6 - 5V2 LDP
Prot counter = 0 start 200ms timer
ESD refresh
Read HOP status
FLS =1
Y
Flash refresh
Check Prot at 200ms timer
Prot active?
Y
Prot counter +1
Stop timer
Return
Prot. C >5
N
Goto protection
DC-PROT BC-PROT LDP IF FLS = CONT HIGH 8V6 IF DCPROT = ACT 5V2 IF DCPROT = ACT
(76) (74) (73) (68) (67)
Fig. 17.3
CL 86532047_037.eps 061098
MG2.1 E
77
Protections via inputs of the OTC (see flow chart

The inputs of the OTC are ESD-protected by means of diodes (BAW56). The cathodes of these diodes are a good test points for these inputs. <--- Service Tip. In case of a protection, all protection lines to the OTC will be checked 5 times (with a repetition time of 200 msec). If after 1 sec the protection is still active then the TV-set will go into protection (blinking LED and the TV is switched to Standby). In case of a flash or an ESD, there is first an ESD-refresh. When a flash or an ESD occurs, it is possible that some settings of IC's are lost. Therefore new initialisation is needed for: HOP-HIP-MSP3410-SEDSPTEA6417-TEA6422-TOPIC-PICNIC-Tuner.
Personal notes
78
MG2.1 E
E.W. drive 6480 10V
E/W
3483// 3484
6485
3490 HOP + 3493 6344 (5) LDP (73) START/ STOP H DRIVE
3491 8V6 220K 1V 3492 33K
8V6
8V6
3340 EHT info (FLASH)
6340
6341 7341 8V6 8V6 OTC 7351 (74) BC-prot
6350 27V
3350
3352 3353
Fig. 17.4
CL 86532047_038.eps 061098
MG2.1 E
79
Protections
The following protections are implemented: 8V6 and 5V2 protection (fig 17.1) The pins 105 and 106 sense the voltages. If one of them is absent, the protection will be activated. Beam Current protection (fig 17.4) If the beam current becomes too high the protection has to be activated for protection of the picture tube. This is detected at the small signal panel via D6350 and TS7351. FBCSO = fixed beam current switch off. The 140V-line on LSP is monitored. DC hardware protection (error 76) (see also fig 17.6) In MD2/GFL there was no separate indication for this. This has to be a fast protection, otherwise the loudspeakers are damaged or one of the amplifiers can become too hot. DCprot is fed to the OTC, but also to the main supply (FSS) for switching off the power supply. The OTC keeps the set in protection (blinking red led).
Personal notes
The protection is activated via TS7761/7762/7796 in case of: Unbalance between +Vs and -Vs Unbalance between +7V7 and -7V7 DC voltage at one of the outputs
80
MG2.1 E
HFB horizontal fly-back

HOP 2 HFB (71) Hdefl
7421 5410 2420 Hdrive
3353
2419
VFB vertical fly-back

HOP 6758 2 VFB (70)
27V
100 8V2
F R A M E
Vpos Vneg
7600 PA
Flyback gen
Thermal prot
Vdefl
Fig. 17.5
CL 86532047_039.eps 140798
MG2.1 E
81
Protections via HOP

The following protections are present: LDP (line deflection protection) Two protection lines come in on pin 5 of the HOP (fig 17.4): Flash detection is detected via D6341 and TS7341. In case of a flash pin 5 becomes high and the Horizontal Drive (HD) stops. The FLS-bit is set in a register of the HOP. A flash is only shortly present. With a "flash refresh" (see flowchart fig 17.3) the FLS-bit is reset and the line output stage is started again via a slow start (chapter 12) Also to pin 5 the E/W-protection is fed. The current in the east/west stage is measured via R3483/R3484. In case of fault condition the voltage is too high. This is sensed at the +input of the op-amp IC7484 and compared with 1V. If the +input is above this 1V, then the E/W-protection is activated. The output of the op-amp is fed back via R3490/D6485 to keep the input high. The line drive is stopped because the LDP input is high. Also in this situation the FLS-bit is set, but after the refresh the FLSbit remains high. That makes the OTC conclude that there must be a protection. This algorithm is also illustrated in flowchart of figure 17.3. Protections via the status register of the HOP Every 200 msec the register in the HOP is read via I2C by the OTC. In case of a protection via one the inputs to the HOP (VFB, HFB) a bit is set to indicate what was wrong. In fig 17.5 the circuitry related to VFB and HFB is visualised. HFB (horizontal flyback) Missing horizontal flyback pulses are detected via the HOP. Error code 71 is generated and the TV switches into protection. VFB (vertical flyback) Vertical flyback is also fed back to the HOP. The picture will be blanked if the vertical flyback pulses are missing. This is done to prevent the picture tube from burning in. The set will go into protection after one second.
Personal notes
82
MG2.1 E
7556 1002 6570 7550 7001 7000
Main supply FFS
Vbatt 8V6 5V2 +Vs (16V) -
STANDBY + DC PROT
220V
6571
AUDIO DCprot (76) P 7761 7796 7762 +Vs +7V7 L R
5VST-by
2700 S -Vs -7V7 C
Fig. 17.6
CL 86532047_040.eps 140798
Service mode via 0356 connector SSP.

Via the service plug O356 on the SSP (short circuit 1-2: Service Default Mode; short circuit 2-3: Service Alignment Mode) ALL software controlled protections are de-activated. (featureboxprotection, 5V2, 8V6, DC-prot, BC-prot, VFB, HFB, LDP). Therefore it is only allowed for Service people to enter this mode. You must be aware what you are doing. For recognition: IF PROTECTION IS OVERRULED THE LED WILL BLINK ORANGE IN STEAD OF RED. Real Hardware-protections as DC-prot, HFB and LDP will always monitor the set-situation. So also with a non-working micro controller these protections are functional. The hardwareprotections VFB and BC-prot stay de-activated in servicemode.
Personal notes
MG2.1 E

Note:
83
Stepwise start-up explanation

Via ComPair the stepwise startup (see also chapter 4) can be realised. This is very helpful when a protection is activated.
State
Description mode
Display leds
Errorcode possible None
When set is in stepwise-mode and due to stepping-up a protection is activated, the set really will go into protection (blinking red led). The set will not leave the stepwise-mode however. By stepping up the set can be activated again, until state X, where protection was activated. At state (X-1) diagnostic measurements can be performed.
Low Power Standby/ uC in Stby High Power Standby/ set in Stby Supply on. Protections 5V2, 8V6, DCProt activated. ICs initialized. (Sound) Protection 3V3 activated EHT startup. No blackcurrent stabilisation. Protections VFB, HFB, LDP, BC-prot activated (blanked picture) TV operates, unblanked picture
Red on
Personal notes
Red 0.5Hz None
Orange/ Green 0.25 Hz Orange/ Green 0.5 Hz
67,68,76
plus 77
Orange/ Green 2 Hz
plus 70,71,73,74
Orange/ Green 10 Hz
Stepwise shutdown explanation
Mode / state
Description mode TV operates, unblanked picture No blackcurrent stabilisation. All protections are enabled ICs stay initialized. (Sound). All protections are off High Power Standby/set in Stby Low Power Standby/uC in Stby
Display leds (Note *) Orange/ Green 10 Hz
Prot. de-activated None
Orange/ Green 2 Hz
None
Orange/ Green 0.5 Hz
74,73,71,70
Red 0.5Hz
77,76,68,67
Red on
None
In this stepwise shutdown mode, mode 2 is skipped. (ICs can not be de-initialized).
84
MG2.1 E

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1

Chapter 2 Mechanical instructions

Removing the rear cover

Side I/O assembly

Service position bottom side (only for LSP)

Service position top side

Chapter 2 Mechanical instructions

Removing the LSP from LSP-bracket

Removing the top control board

Top control board

Removing the mains switch/LED board

Removing the LSP-top bracket

Mounting the rear cover

New tools and service features

DNR noisy signal good signal high low

Sharpness low high

1010 degaussing +t Rs +t Rp 7020

7213 start 7020 7020 7808 +8V6

TL431 Blockdiagram supply-part

+5V2 Hdefl 7421 2432/2434

7600 TDA8177 +13V

-15V Vdefl Blockdiagram deflection

Chapter 4 Service modes / Compair

Step-wise start-up/Stepwise shutdown (feature of Compair)

Chapter 5: Control and teletext 5.1 Control part

Chapter 5: Control and teletext 5.1 Control part

SAA 5800 OTC 2.5

77 8V6 3V3 105 OSD/TXT 78 79 80

RAM_DE CASHN CASL RaSN WE

ROM CE ROM CS 23 11 ROM 16Mbit (2Mbyte)

40 43 42 41 12 14 FLASH RAM EPG

RAM TXT CONTROL

Chapter 5: Control and teletext 5.1 Control part

Chapter 5: Control and teletext 5.1 Control part

Realisation of nexTView in MG2.1E

Chapter 5: Control and teletext 5.1 Control part

73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103

active low active low 3V3 gnd analogue analogue analogue

A16 A0 A15 A1 A14 VDDP2 VSSP2 A2 A13 A3 A12 A4 A11 A5 A10 A6 A9

Chapter 6: POWER SUPPLY GENERAL

Chapter 6: POWER SUPPLY GENERAL

3003 7000 2007

7001 3008 STBY 2009 3009

Chapter 6: POWER SUPPLY MAINS FILTER

R3005/6 is the sputtering resistor limiting the inrush current.

Chapter 6: POWER SUPPLY STANDBY POWER SUPPLY

STANDBY POWER SUPPLY

4 VMAIN = V(2100) UA 5 UMAIN UC 2101 3 1 G

6107 5V STBY Usec 2104

3102 3101 UMAIN start 6105 7101

UD Nx5V UMAIN t IPrim

Chapter 6: POWER SUPPLY STANDBY POWER SUPPLY

Time interval t0-t1

Time interval t1-t2

Chapter 6: POWER SUPPLY STANDBY POWER SUPPLY

5101 6107 5V STBY

FEEDBACK STABILISATION (fig. 6.3 + 6.4)

Chapter 6: POWER SUPPLY STANDBY POWER SUPPLY

5.01 Uout 5V 4.99 15V Ugate Fig. a 0V