Pseudo nMOS and Dynamic Logic

Presentation by:
Dr. S. KIRUBA VENI
Asso. Prof/ECE
SSN College of Engineering
Session Meta Data
Author Dr. S. KIRUBA VENI

Version No 1.1

Release Date 23-07-2019

Reviewer
Revision History
Date of Revison Details Version Number

23-07-2019 1.1
Session Objectives
 To learn the working of pseudo nMOS.
 To understand the concepts of dynamic logic.
Session Outcomes
 At the end of the session, students will be able to
 Understand the operation of pseudo nMOS
 Analyze the advantages and disadvantages of
various dynamic logic
Outline
 Pseudo nMOS
 Dynamic logic
 Non-ideal effects
 Pass transistor logic
 Summary
 Pseudo-nMOS
❑ In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON
❑ In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of
1.8
pulldown network
1.5
load
P/2 1.2
P = 24
Ids Vout 0.9

Vout 0.6
P = 14
16/2 0.3
P =4
Vin
0
0 0.3 0.6 0.9 1.2 1.5 1.8
Vin
 Pseudo-nMOS G a t e s
❑ Design for unit current on output
to compare with unit inverter. Y
❑ pMOS fights nMOS inputs
f

Inverter NAND2 NOR2

gu = 4/3 gu = 8/3 gu = 4/3

gd = 4/9 2/3 gd = 8/9 gd = 4/9
gavg = 8/9 Y g = 16/9 gavg = 8/9
2/3 A avg 2/3
pu = 6/3 8/3 pu = 10/3
Y Y p u = 10/3
A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9
pavg = 12/9 pavg = 20/9 pavg = 20/9
 Pseudo-nMOS Design
❑ Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS
❑ G = 1 * 8/9 = 8/9 In1 1
Y
❑ F = GBH = 8H/9 H
Ink 1
❑ P = 1 + (4+8k)/9 = (8k+13)/9
❑ N=2
4 2H 8k  13
❑ 1/N
D = NF + P = 
3 9
 Pseudo-nMOS P o w e r
❑ Pseudo-nMOS draws power whenever Y = 0
– Called static power P = IDDVDD
– A few mA / gate * 1M gates would be a problem
– Explains why nMOS went extinct
❑ Use pseudo-nMOS sparingly for wide NORs
❑ Turn off pMOS when not in use

en
Y
A B C
 Ratio Example
❑ The chip contains a 32 word x 48 bit ROM
– Uses pseudo-nMOS decoder and bitline pullups
– On average, one wordline and 24 bitlines are high
❑ Find static power drawn by the ROM
– Ion-p = 36 A
❑ Solution:

Ppull-up  VDD Ipull-up  36 µW

Pstatic  (31  24)Ppull-up  1.98 mW
Cascode Voltage Switch Logic

➢ Cascode Voltage Switch Logic (CVSL ) seeks the performance of ratioed circuits without the
static power consumption.
➢ It uses both true and complementary input signals and computes both true and
complementary outputs using a pair of nMOS pull-down networks.
➢ The pull-down network f implements the logic function as in a static CMOS gate, while f
uses inverted inputs feeding transistors arranged in the conduction complement.
➢ For any given input pattern, one of the pull-down networks will be ON and the other OFF.
➢ The pull-down network that is ON will pull that output low.
➢ This low output turns ON the pMOS transistor to pull the opposite output high.
➢ When the opposite output rises, the other pMOS transistor turns OFF so no static power
dissipation occurs.
✓ CVSL has a potential speed advantage because all of the logic is performed with nMOS
transistors, thus reducing the input capacitance.

✓ As in pseudo-nMOS, the size of the pMOS transistor is important.

✓ It fights the pull-down network, so a large pMOS transistor will slow the falling transition.
Unlike pseudo-nMOS, the feedback tends to turn off the pMOS, so the outputs will
eventually settle to a legal logic level. A small pMOS transistor is slow at pulling the
complementary output high.

✓ In addition, the CVSL gate requires both the low- and high-going transitions, adding more
delay. Contention current during the switching period also increases power consumption.
✓ Pseudo-nMOS worked well for wide NOR structures. Unfortunately, CVSL also requires the
complement, a slow tall NAND structure. Therefore, CVSL is poorly suited to general NAND
and NOR logic. Even for symmetric structures like XORs, it tends to be slower than static
CMOS, as well as more power-hungry.
✓ However, the ideas behind CVSL help us understand dual-rail domino and complementary
pass-transistor logic discussed in later sections.
Dynamic Circuits

➢ Ratioed circuits reduce the input capacitance by replacing the pMOS

transistors connected to the inputs with a single resistive pull-up.
➢ The drawbacks of ratioed circuits include slow rising transitions,
contention on the falling transitions, static power dissipation, and a non-
zero VOL.
➢ Dynamic circuits circumvent these drawbacks by using a clocked pull-up
transistor rather than a pMOS that is always ON.
Dynamic Circuits

➢ Figure 6.21 compares (a) static CMOS, (b) pseudo-nMOS, and (c) dynamic
inverters.

➢ Dynamic circuit operation is divided into two modes, shown in Figure 6.22.
➢ During precharge, the clock (J) is '0,' so the clocked pMOS is ON and initializes
the output Yhigh.
➢ During evaluation, the clock is '1' and the clocked pMOS turns OFF.
➢ The output may remain high or may be discharged low through the pull-down
network. Dynamic circuits are the fastest commonly used circuit family because
they have lower input capacitance and no contention during switching. They also
have zero static power dissipation.
 Dynamic Logic
❑ Dynamic gates uses a clocked pMOS pullup
❑ Two modes: precharge and evaluate

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

F ig 6 . 2 1
 Precharge Evaluate Precharge

Y
F ig 6 . 2 2
However, they require careful clocking, consume significant dynamic power, and are
sensitive to noise during evaluation.
In Figure 6.21(c), if the inputs is '1' during precharge, contention will take place
because both the pMOS and nMOS transistors will be ON.
When the input cannot be guaranteed to be '0' during precharge, an extra clocked
evaluation transistor can be added to the bottom of the nMOS stack to avoid
contention as shown in Figure 6.23.

The extra transistor is sometimes called a foot. Figure 6.24 shows generic footed and
unfooted gates .
Logical Effort
 Monotonicity
❑ Dynamic gates require monotonically rising inputs
during evaluation

– 0 -> 0
– 0 -> 1 A

– 1 -> 1
– But not 1 -> 0 violates monotonicity
during evaluation
A

 Precharge Evaluate Precharge

Output should rise but does not

 M o n o t o n i c i t y Woes
❑ But dynamic gates produce
monotonically falling
outputs during evaluation
❑ Illegal for one dynamic gate
to drive another!

A=1

  Precharge
Precharge Evaluate
Evaluate Precharge
Precharge
Y
Y
A X
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot
 Domino Gates
❑ Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
 Precharge Evaluate Precharge

domino AND
W

W X Y Z X
A
B Y
C

Z

dynamic static
 
NAND inverter  
A W X A X
H Y =
B H Z B Z
C C
 Domino Optimizations
❑ Each domino gate triggers next one, like a string of
dominos toppling over
❑ Gates evaluate sequentially but precharge in parallel
❑ Thus evaluation is more critical than precharge
❑ HI-skewed static stages can perform logic


S0 S1 S2 S3
D0 D1 D2 D3

Y
H


S4 S5 S6 S7
D4 D5 D6 D7
 Dual-Rail D o m i n o
❑ Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
❑ Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs

sig_h sig_l Meaning

Y_l  Y_h
0 0 Precharged
inputs
0 1 ‘0’ f f

1 0 ‘1’ 

1 1 invalid
 E x a m p l e : AND/NAND
❑ Given A_h, A_l, B_h, B_l
❑ Compute Y_h = AB, Y_l = AB
❑ Pulldown networks are conduction complements

Y_l  Y_h
= A*B A_h = A*B
A_l B_l B_h


 E x a m p l e : XOR/XNOR
❑ Sometimes possible to share transistors

Y_l  Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h


 Leak age
❑ Dynamic node floats high during evaluation
– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds
❑ Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper
 1 k
X
H Y
A 2
2
 Charge Sh a r i n g
❑ Dynamic gates suffer from charge sharing




Y A
A
A x CY
Y
Y
B=0 Cx Charge sharing noise

CY
Vx  VY  VDD
C x  CY
 Secondary Precharge
❑ Solution: add secondary precharge transistors
– Typically need to precharge every other node
❑ Big load capacitance CY helps as well

secondary
 precharge
Y transistor
A x
B
 Noise Sensitivity
❑ Dynamic gates are very sensitive to noise
– Inputs: VIH  Vtn
– Outputs: floating output susceptible noise
❑ Noise sources
– Capacitive crosstalk
– Charge sharing
– Power supply noise
– Feedthrough noise
– And more!
 Po w e r
❑ Domino gates have high activity factors
– Output evaluates and precharges
• If output probability = 0.5,  = 0.5
– Output rises and falls on half the cycles
– Clocked transistors have  = 1
❑ Leads to very high power consumption
 Domino Summary
❑ Domino logic is attractive for high-speed circuits
– 1.3 – 2x faster than static CMOS
– But many challenges:
• Monotonicity, leakage, charge sharing, noise
❑ Widely used in high-performance microprocessors in
1990s when speed was king
❑ Largely displaced by static CMOS now that power is
the limiter
❑ Still used in memories for area efficiency
Pass T r a n s i s t o r C i r c u i t s
❑ Use pass transistors like switches to do logic
❑ Inputs drive diffusion terminals as well as gates

❑ CMOS + Transmission Gates:

– 2-input multiplexer
– Gates should be restoring
S S

A A

S Y S Y

B B

S S
 L EA P
❑ LEAn integration with Pass transistors
❑ Get rid of pMOS transistors
– Use weak pMOS feedback to pull fully high
– Ratio constraint

S
A
S L Y
B
 CPL
❑ Complementary Pass-transistor Logic
– Dual-rail form of pass transistor logic
– Avoids need for ratioed feedback
– Optional cross-coupling for rail-to-rail swing

S
A
S L Y
B
S
A
S L Y
B
 Pass T r a n s i s t o r S u m m a r y
❑ Researchers investigated pass transistor logic for
general purpose applications in the 1990’s
– Benefits over static CMOS were small or negative
– No longer generally used
❑ However, pass transistors still have a niche in
special circuits such as memories where they offer
small size and the threshold drops can be managed
Summary
➢Ratioed circuits reduce the input capacitance by replacing
the pMOS transistors connected to the inputs with a
single resistive pull-up.
➢The drawbacks of ratioed circuits include slow rising
transitions, contention on the falling transitions, static
power dissipation, and a non- zero VOL.
➢Dynamic circuits circumvent these drawbacks by using a
clocked pull-up transistor rather than a pMOS that is
always ON.
Test your Understanding
• List the advantage and disadvantage of dynamic
logic.
• Explain the non-ideal effects of dynamic logic.
• Brief the operation of CPL.