Ca Is1200

CA-IS1200U, CA-IS1200G
上海川土微电子有限公司 Version 1.01, 2022/12/20
CA-IS1200 Isolated Amplifier for Current Sensing

magnetic changes. The high common-mode transient
1 Key Features
immunity (CMTI) means that the CA-IS1200 devices
• Differential Input Voltage Range: ±250 mV transmit correct signals through isolation barriers and are
• Fixed Initial Gain: 8 suitable for industrial motor controls and drives which
• Low Input Offset and Drift: ±1 mV (max) at 25°C, ±4 require high-voltage and high-power switching. The internal
μV/°C (max) input common-mode overvoltage and missing high-side
• Low Gain Error and Drift: supply voltage detection functions contribute to fault
±0.5% (max) at 25°C, ±50 ppm/°C (max)
diagnostics and system safety.
• Low Nonlinearity and Drift:
0.01% (typ) for Full Scale, ±1 ppm/°C (typ)
The CA-IS1200 devices are packaged in 8-pin DUB or wide-
• 3.3-V or 5-V Operation for Both High- and Low-Side
body SOIC packages and specified over the extended
• High CMTI: ±150 kV/µs (typ)
• Wide Operating Temperature Range: –40°C to 125°C industrial temperature range of –40°C to 125°C.
• Safety-Related Certifications (Pending)
▪ 7070-VPK (CA-IS1200G) Isolation per DIN V VDE V Device Information
0884-11 (VDE V 0884-11): 2017-01
▪ 5000-VRMS (CA-IS1200G) Isolation for 1 Minute PART
PACKAGE BODY SIZE (NOM)
per UL 1577 NUMBER
▪ CQC and TUV Certification Approvals CA-IS1200U DUB8 (U) 9.20 mm × 6.62 mm
2 Applications
CA-IS1200G SOIC8-WB (G) 5.85 mm × 7.50 mm
• Industrial Motor Controls and Drives
• Isolated Switch Mode Supplies
• Uninterruptible Power Supplies
Simplified Schematic
3 Description
Isolated Supply Low-side Supply
The CA-IS1200 devices are high-precision isolated amplifiers
and optimized for shunt-resistor-based current sensing. VDD1 VDD2
Low offset and gain error and drift guarantee that
Isolation Barrier
VINP VOUTP
measuring accuracy is maintained over the entire operating
Rshunt
temperature range. ADC
VINN VOUTN
The CA-IS1200 devices utilize silicon oxide (SiO2) isolation
barriers and support up to 3750-VRMS (CA-IS1200U) or 5000- GND1 GND2
VRMS (CA-IS1200G) galvanic isolation per UL 1577. This CA-IS1200

technology separates high- and low-voltage domain to
protect lower-voltage parts from damage and provides low
emissions as well as strong anti-interference capability from
Copyright © 2021, Chipanalog Incorporated

上海川土微电子有限公司
Version 1.01, 2022/12/20 上海川土微电子有限公司
4 Ordering Guide
Table 4-1 Ordering Guide for Valid Ordering Part Number
Ordering Part Number Specified Input Range Isolation Rating Package
CA-IS1200U ±250 mV 3750 VRMS DUB8
CA-IS1200G ±250 mV 5000 VRMS SOIC8-WB
2 Copyright © 2021, Chipanalog Incorporated

Table of Contents
1 Key Features .......................................................1 9.1 System Overview .............................................. 16
2 Applications ........................................................1 9.2 Feature Description .......................................... 16
3 Description .........................................................1 9.2.1 Analog Input ..................................................... 16
9.2.2 Signal Transmission Across Isolation Barrier .... 16
4 Ordering Guide ...................................................2 9.2.3 Fail-Safe Output ............................................... 17
5 Revision History ..................................................3 10 Application and Implementation ................ 19
6 Pin Descriptions and Functions ............................4 10.1.1 Typical Application for Current Sensing ....... 19
7 Specifications......................................................5 10.1.2 Choose Proper Rshunt .................................... 19
7.1 Absolute Maximum Ratings1 ...............................5 10.1.3 Input Filter ................................................... 20
7.2 ESD Ratings..........................................................5 10.1.4 Power Supply Recommendations ................ 20
10.1.5 Output Filter ................................................ 20
7.3 Recommended Operating Conditions .................5
10.1.6 Error Analysis in Voltage Sensing ................. 21
7.4 Thermal Information ...........................................5
10.1.7 Caution ........................................................ 21
7.5 Power Ratings......................................................5
11 Package Information .................................. 22
7.6 Insulation Specifications .....................................6
11.1 8-Pin DUB Package ............................................ 22
7.7 Safety-Related Certifications ...............................7
11.2 8-Pin Wide Body SOIC Package ......................... 23
7.8 Electrical Characteristics .....................................8
12 Soldering Information ................................ 24
7.9 Typical Characteristics .......................................10
8 Parameter Measurement Information ............... 15 13 Tape and Reel Information ......................... 25
9 Detailed Description ......................................... 16 14 Important Notice ....................................... 26
5 Revision History
Revision Description Rev Date Page
Version 1.00 NA NA
Version 1.01 Changed POD and Type reel information 2022/12/20 21,22,24
Copyright © 2021, Chipanalog Incorporated 3

6 Pin Descriptions and Functions
VDD1 1 8 VDD2 VDD1 1 8 VDD2
VINP 2 CA-IS1200U 7 VOUTP VINP 2 CA-IS1200G 7 VOUTP

Top View Top View
VINN 3 (Not to Scale) 6 VOUTN VINN 3 (Not to Scale) 6 VOUTN
GND1 4 5 GND2 GND1 4 5 GND2
Figure 6-1 CA-IS1200 Top View
Table 6-1 CA-IS1200 Pin Description and Functions

NAME PIN NUMBER TYPE DESCRIPTION
VDD1 1 Power High-side power supply, 3 V to 5.5 V
VINP 2 Input Noninverting analog input
VINN 3 Input Inverting analog input
GND1 4 Ground High-side ground
GND2 5 Ground Low-side ground
VOUTN 6 Output Inverting analog output
VOUTP 7 Output Noninverting analog output
VDD2 8 Power Low-side power supply, 3 V to 5.5 V

7 Specifications
7.1 Absolute Maximum Ratings1
PARAMETER MIN MAX UNIT
VDD1, VDD2 Supply voltage2 –0.5 6.5 V
VINP, VINN Analog input voltage GND1 – 6 6.5 V
VOUTP, VOUTN Analog output voltage GND2 – 0.5 VDD2 + 0.53 V
IIN Input current to any pin except supply pins –10 10 mA
TJ Junction Temperature 150 °C
TSTG Storage Temperature –65 150 °C
NOTE:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. All voltage values are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
3. Maximum voltage must not exceed 6.5 V.
7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins ±4000
VESD Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins ±2000
7.3 Recommended Operating Conditions

PARAMETER MIN NOM MAX UNIT
VDD1 High-side supply voltage, with respect to GND1 3.0 5.0 5.5 V
VDD2 Low-side supply voltage, with respect to GND2 3.0 3.3 5.5 V
TA Ambient Temperature –40 125 °C
7.4 Thermal Information

VALUE VALUE
THERMAL METRIC UNIT
(U) (G)
RθJA Junction-to-ambient thermal resistance 73.3 110.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 63.2 51.7 °C/W
RθJB Junction-to-board thermal resistance 43.0 66.4 °C/W
ψJT Junction-to-top characterization parameter 27.4 16.0 °C/W
ψJB Junction-to-board characterization parameter 42.7 64.5 °C/W
RθJC(bottom) Junction-to-case (bottom) thermal resistance NA NA °C/W
7.5 Power Ratings

PARAMETER TEST CONDITIONS VALUE UNIT
VDD1 = VDD2 = 5.5 V 129.25
PD Maximum power dissipation for both sides mW
VDD1 = VDD2 = 3.6 V 76.32
VDD1 = 5.5 V 85.25
PD1 Maximum power dissipation for high-side mW
VDD1 = 3.6 V 50.40
VDD2 = 5.5 V 44.00
PD2 Maximum power dissipation for low-side mW
VDD2 = 3.6 V 25.92

7.6 Insulation Specifications
VALUE VALUE
PARAMETR TEST CONDITIONS UNIT
(U) (G)
Shortest terminal-to-terminal distance through
CLR External clearance1 6.1 8 mm
air
Shortest terminal-to-terminal distance across the
CPG External creepage1 6.8 8 mm
package surface
DTI Distance through the insulation Minimum internal gap (internal clearance) 28 28 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 > 600 V
Material group According to IEC 60664-1 I I
Rated mains voltage ≤ 300 VRMS I-IV I-IV
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 400 VRMS I-IV I-IV
Rated mains voltage ≤ 600 VRMS I-III I-III
DIN V VDE V 0884-11:2017-012
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1414 1414 VPK
AC voltage; Time dependent dielectric
1000 1000 VRMS
VIOWM Maximum working isolation voltage breakdown (TDDB) Test
DC voltage 1414 1414 VDC
VTEST = VIOTM,
t = 60 s (qualification);
VIOTM Maximum transient isolation voltage 5300 7070 VPK
VTEST = 1.2 × VIOTM,
t= 1 s (100% production)
Test method per IEC 60065, 1.2/50 μs waveform,
VIOSM Maximum surge isolation voltage3 5000 6250 VPK
VTEST = 1.6 × VIOSM (qualification)
Method a, After input/output safety test
subgroup 2/3,
≤5 ≤5
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
qpd Apparent charge4 Vini = VIOTM, tini = 60 s; ≤5 ≤5 pC
Vpd(m) = 1.6 × VIORM, tm = 10 s
Method b1, At routine test (100% production)
and preconditioning (type test)
≤5 ≤5
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
CIO Barrier capacitance, input to output5 VIO = 0.4 × sin (2πft), f = 1 MHz ~1 ~1 pF
VIO = 500 V, TA = 25°C > 1012 > 1012
RIO Isolation resistance5 VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011 > 1011 Ω
VIO = 500 V at TS = 150°C > 109 > 109
Pollution degree 2 2
UL 1577
VTEST = VISO, t = 60 s (qualification),
VISO Maximum withstanding isolation voltage 3750 5000 VRMS
VTEST = 1.2 × VISO, t = 1 s (100% production)
NOTE:
1. Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
2. This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
3. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
4. Apparent charge is electrical discharge caused by a partial discharge (pd).
5. All pins on each side of the barrier tied together creating a two-terminal device.

7.7 Safety-Related Certifications
VDE (Pending) UL CQC (Pending)
Certified according to DIN V VDE V 0884- Recognized under UL 1577 Component Certified according to GB4943.1-2011
11:2017-01 Recognition Program
Certification number: Certification number: Certification number:
E511334-20200520

7.8 Electrical Characteristics
All minimum and maximum specifications apply from TA = –40°C to 125°C, VDD1 = 3 V to 5.5 V, VDD2 = 3 V to 5.5 V, VINP = –250 mV to 250 mV, and
VINN = GND1 = 0 V (unless otherwise noted). All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Maximum input voltage before clipping
VClipping VINP – VINN ±320 mV
output
VFSR Specified linear full-scale input range VINP – VINN –250 250 mV
VDD1 –
VCM Operating common-mode input voltage (VINP + VINN) / 2 to GND1 –0.16 V
2.1
VCMOV Common-mode overvoltage threshold (VINP + VINN) / 2 to GND1 VDD1 – 2 V
Hysteresis of common-mode over-
VCMOV_HYS 100 mV
voltage threshold
Initial, at TA = 25°C,
VOS Input offset voltage –1 ±0.05 1 mV
VINP = VINN = GND1
TCVOS Input offset voltage drift –4 ±1 4 μV/°C
DC, VINP = VINN –98
CMRRIN Input common-mode rejection ratio dB
fIN = 10 kHz, VINP = VINN –98
CIN Single-ended input capacitance fIN = 275 kHz, VINN = GND1 2 pF
CIND Differential input capacitance fIN = 275 kHz 1 pF
RIN Single-ended input resistance VINN = GND1 19 kΩ
RIND Differential input resistance 22 kΩ
VINP = VINN = GND1,
IIN Input current –41 –30 –24 μA
IIN = (IINP + IINN) / 2
TCIIN Input current drift ±1 nA/°C
IINOS Input offset current ±5 nA
BWIN Input bandwidth 1000 kHz
ANALOG OUTPUT
Gain1 Initial, at TA = 25°C 8 V/V
EG Gain error Initial, at TA = 25°C –0.5% ±0.05% 0.5%
TCEG Gain error drift –50 ±15 50 ppm/°C
NL Nonlinearity 2 –0.03% ±0.01% 0.03%
TCNL Nonlinearity drift ±1 ppm/°C
Output noise VINP = VINN = GND1, BW = 100 kHz 330 μVRMS
VIN = 500 mVpp, fIN = 10 kHz, BW =
THD Total harmonic distortion –85 dB
100 kHz
VIN = 500 mVpp, fIN = 1 kHz, BW = 10
83
kHz
SNR Signal-to-noise ratio dB
VIN = 500 mVpp, fIN = 10 kHz, BW =
68
100 kHz
At VDD1, DC –100
At VDD1, 100-mV and 10-kHz ripple –90
PSRR Power supply rejection ratio3 dB
At VDD2, DC –100
At VDD2, 100-mV and 10-kHz ripple –98
VCMOUT Common-mode output voltage 1.39 1.45 1.51 V
VFAILSAFE Fail-safe differential output voltage VCMOV ≤ VCM or VDD1 missing –2.53 –2.43 V
VOUTP or VOUTN shorts to VDD2 or
IOSC Output short-circuit current ±13 mA
GND2
ROUT Output resistance On VOUTP or VOUTN < 0.2 Ω
BWOUT Output bandwidth (–3 dB) 250 310 kHz
|GND1 – GND2| = 1.5 kV; See Figure
CMTI Common-mode transient immunity 100 150 kV/μs
8-1
POWER SUPPLY
VDDUV VDD undervoltage threshold VDD1 or VDD2 rising 2.5 2.7 V

3.0 V ≤ VDD1 ≤ 3.6 V 9.3 14.0
IDD1 High-side supply current mA
4.5 V ≤ VDD1 ≤ 5.5 V 10.7 15.5
3.0 V ≤ VDD2 ≤ 3.6 V 5.2 7.2
IDD2 Low-side supply current mA
4.5 V ≤ VDD2 ≤ 5.5 V 5.7 8.0
VINP = 0 to 0.25 V step;

tr Rise time of VOUT (10% – 90%) 1.2 μs
See Figure 8-2
VINP = 0.25 V to 0 step;
tf Fall time of VOUT (90% – 10%) 1.2 μs
See Figure 8-2
tPD VIN to VOUT signal delay (50% – 50%) Output unfiltered; See Figure 8-3 1.5 2.1 μs
VDD1 = 0 to 3 V step and 3.0 V ≤
tAS Analog settling time 500 μs
VDD2, to VOUT valid (0.1% settling)
NOTE:
1. The gain is defined as the slope of the optimum line derived by the method of least squares between differential input voltage (VINP –
VINN) and differential output voltage (VOUTP – VOUTN) over the specified input range.
2. Nonlinearity is defined as a fraction of the half of the peak-to-peak value of differential output voltage deviation divided by the full-scale
differential output voltage.
3. This parameter is input referred.

7.9 Typical Characteristics
All typical specifications are at VINP = –250 mV to 250 mV, and VINN = GND1 = 0 V, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted).
Figure 7-1 Gain Error vs Temperature Figure 7-2 Gain Error vs VDD1
Figure 7-3 Gain Error vs VDD2 Figure 7-4 Input Offset vs Temperature
Figure 7-5 Input Offset vs VDD1 Figure 7-6 Input Offset vs VDD2

Figure 7-7 Total Harmonic Distortion vs Temperature @ fIN = 10 kHz Figure 7-8 Total Harmonic Distortion vs VDD1 @ fIN = 10 kHz
Figure 7-9 Total Harmonic Distortion vs VDD2 @ fIN = 10 kHz Figure 7-10 SNR vs Temperature @ fIN = 1 kHz
Figure 7-11 SNR vs Temperature @ fIN = 10 kHz Figure 7-12 SNR vs VDD1 @ fIN = 10 kHz

Figure 7-13 SNR vs VDD2 @ fIN = 10 kHz Figure 7-14 High-Side VCMOV vs Temperature
Figure 7-15 High-Side VCMOV_HYS vs Temperature Figure 7-16 Low-Side VCMOUT vs Temperature
Figure 7-17 Low-Side VCMOUT vs VDD2 Figure 7-18 Output Rise and Fall Time vs Temperature

Figure 7-19 Output Rise and Fall Time vs VDD2 Figure 7-20 VIN to VOUT Signal Delay vs Temperature
Figure 7-21 VIN to VOUT Signal Delay vs VDD2 Figure 7-22 Supply Current vs Temperature
Figure 7-23 Supply Current vs Supply Voltage Figure 7-24 Normalized Gain vs Frequency

Figure 7-25 Input CMRR vs Frequency Figure 7-26 PSRR vs Frequency
Figure 7-27 VOUT vs VIN Figure 7-28 Input-Referred Noise Density vs Frequency
Figure 7-29 Nonlinearity vs Temperature Figure 7-30 Nonlinearity vs Supply Voltage

8 Parameter Measurement Information
Isolated Supply Low-side Supply
VDD1 VDD2
Cdep2
Isolation Barrier
VINP VOUTP
Differential
Cdep2 Vout
Probe
VINN VOUTN
Oscilloscope
GND1 GND2
High
Voltage
Differential
Probe
High Voltage Surge Generator 1
Note:
1. The High Voltage Surge Generator generates repetitive high voltage surges with > 1 kV amplitude and < 10 ns rise time or fall time to generate
common-mode transient noise with > 150 kV/μs slew rate.
2. Cdep is the 0.1~1 μF decoupling capacitor.
Figure 8-1 Common-Mode Transient Immunity Test Circuit
0.25 V
VINP - VINN
0V
VOUTP 90%
10%
VOUTN
tr tf
Figure 8-2 Rise and Fall Time Test Waveforms
0.25 V
VINP - VINN 50%
0V
tPD
VOUTP
50%
50%
VOUTN
Figure 8-3 Delay Time Test Waveforms

9 Detailed Description
9.1 System Overview
The CA-IS1200 devices are high-precision isolated amplifiers designed for shunt-resistor-based current sensing. The functional
block diagram of this device is shown in Figure 9-1. At high side, the fully differential amplifier pre-amplifies the measuring
voltage across a shunt resistor and then drives a 2nd-order Sigma-Delta (ΣΔ) modulator. This modulator converts the analog signal
to a digital bitstream. For transmission across the SiO2-based isolation barrier, the digital stream is further modulated with a
high-frequency carrier using a simple on-off keying (OOK) modulation scheme. The receiver (RX) recoveries the modulated signal
to the original digital bitstream at low side. After processed by a 1-bit digital-to-analog converter (DAC), the digital bitstream is
sent to an active low-pass filter to produce the analog output. For synchronization of the whole chip, the clock is generated at
low side and sent back to high side ensuring that all clocks come from one source.
VDD1 VDD2
Barrier
High Side Low Side
UVLO clk
RX TX
OSC
VINP VOUTP
2nd-Order
1-bit DAC
Active
Sigma-Delta TX RX Low-Pass
Modulator Filter
VINN VOUTN
VCMOV
Isolation
VREF_HS UVLO VREF_LS

Detector
GND1 GND2
Figure 9-1 Functional Block Diagram of CA-IS1200
9.2 Feature Description

9.2.1 Analog Input
The CA-IS1200 device utilizes a fully differential amplifier stage to pre-amplify the measuring voltage across the shunt resistor.
The nominal gain of the front-end differential amplifier is 4, contributing part of the total gain and ensuring that the 2 nd-order
Sigma-Delta modulator is not saturated when the analog input is within the specific input voltage range. This gain is set by the
internal high-precision resistor network. The tens-of-several-kΩ input resistance means it can bring in more gain error and offset
if CA-IS1200 devices are applied in measurement where the input signal sources are high-impedance (refer to Error Analysis in
Voltage Sensing for detailed information).
The ESD structure of CA-IS1200 supports the absolute maximum analog input voltage (with respect to GND1) to range from
GND1 – 6 V to VDD1 + 0.5 V. To guarantee the long-term reliability and device performance, the differential analog input voltage
and the input common-mode voltage of CA-IS1200 must be kept within the specific range.
9.2.2 Signal Transmission Across Isolation Barrier

The CA-IS1200 devices utilize a simple on-off keying (OOK) modulation scheme to transmit the digital bitstream across the SiO2-
based isolation barrier which supports up to 3750-VRMS (CA-IS1200U) or 5000-VRMS (CA-IS1200G) galvanic isolation between
high- and low-voltage domain. The block diagram of an isolation channel is shown in Figure 9-2. As shown in Figure 9-3, the
transmitter (TX) modulates the digital bitstream with a high-frequency carrier when the signal is HIGH while sends no signal

when the signal is LOW. The receiver (RX) demodulates the signal across the isolation barrier and reproduces the digital bitstream
faithfully. The isolation channel adopts fully differential capacitive-coupled structure which is insensitive to common-mode
transient noises, thus the CMTI performance can be maximized. This structure and related circuitry also provide low emissions
and strong anti-interference capability from magnetic changes.
Transmitter (TX) Receiver (RX)
Schmitt
Trigger
SiO2-Based
TX IN Modulator Isolation Demodulator Drv RX OUT
Barrier
High-Freq
Carrier
Figure 9-2 Block Diagram of an Isolation Channel
TX IN
Signal Across
Isolation Barrier
RX OUT
Figure 9-3 Conceptual Operation Waveforms of OOK Modulation Scheme
9.2.3 Fail-Safe Output

The CA-IS1200 devices have fail-safe output function which is activated in two conditions:
• The high-side power supply is missing;
• The common-mode input voltage VCM exceeds the common-mode overvoltage threshold VCMOV.
As shown in Figure 9-4 and Figure 9-5, the fail-safe output is a more negative differential output voltage which can be
distinguished from the negative clipping output voltage. This function contributes to fault diagnostics and system safety.

Figure 9-4 Typical Fail-Safe Output Figure 9-5 Typical Negative Clipping Output

10 Application and Implementation
10.1.1 Typical Application for Current Sensing
High Voltage High-Side
Bus Gate Drive Supply
3.3 V or 5 V
Gate Driver R3
QH
C4 C5
D1 C3 C2 0.1 μF 2.2 μF
2.2 μF 0.1 μF VDD1 VDD2
Rshunt
Isolation Barrier
VINN VOUTP
R1 R4
C1 C6 ADC
VINP VOUTN
Low-Side R2 R5
Gate Drive Supply
GND1 GND2
Gate Driver CA-IS1200

AGND
Load QL
PGND PGND
Figure 10-1 Typical Application for Current Sensing
The typical application for current sensing is shown in Figure 10-1. The CA-IS1200 device is used to amplify the voltage across
the shunt resistor (Rshunt) and transmit it to the low-voltage side for control circuit to process. The differential input and the high
CMTI of CA-IS1200 ensure the reliable and accurate measurement in the high-noise and high-power switching applications such
as industrial motor drives. The voltage of Rshunt with respect to PGND varies from 0 V to the high voltage bus when switching,
thus isolation is required. The CA-IS1200 devices support up to 3750-VRMS (CA-IS1200U) or 5000-VRMS (CA-IS1200G) galvanic
isolation, making them suitable for these high-voltage industrial applications.
In a three-phase motor drive application, this circuit could be repeated three times and one for each phase in order to measure
each phase current.
10.1.2 Choose Proper Rshunt

The value chosen of shunt resistor is a trade off between power dissipation and measuring accuracy. Small value resistors
minimize power dissipation, while large value resistors take advantage of the full performance input range of the Sigma-Delta
modulator.
Consider the following restrictions to choose proper value of the shunt resistor Rshunt:
• The voltage drop across Rshunt caused by the nominal measured current is within the linear differential input voltage range
VFSR;
• The voltage drop across Rshunt caused by the maximum allowed current must not exceed the maximum input voltage
before clipping output |VClipping|.
For best performance, place the shunt resistor close to the inputs of CA-IS1200 and keep the layout of both connections
symmetrical. This ensures that any noises occurring at high side are coupled equally to the inputs and would be rejected as a

common-mode signal. Kelvin connection is recommended between Rshunt and the inputs of CA-IS1200 to remove the impact
from any voltage drops across the trace and leads.
10.1.3 Input Filter

The typical input bandwidth of CA-IS1200 is 1 MHz. A first-order passive RC low-pass filter could be placed between Rshunt and
the inputs to narrow the input bandwidth. Choose R1 = R2 = 10 Ω and C1 = 20 nF could provide a cutoff frequency of approximately
400 kHz. R1 and R2 should be low-value enough compared to the input impedance of CA-IS1200 to reduce gain error.
10.1.4 Power Supply Recommendations

The high-side power supply of CA-IS1200 could be generated directly derived from the high-side gate drive power supply by
utilizing a Zener diode (D1) to produce a 3.3-V or 5-V (±10%) voltage. And a low-ESR decoupling capacitor of 0.1 μF (C2) is
recommended to place as close as possible to the VDD1 pin of CA-IS1200. Additional 2.2-μF capacitor (C3) is recommended for
better filtering to the high-side power-supply path.
Similarly, a 0.1-μF decoupling capacitor (C4) followed by an additional capacitor (C5) from 2.2 μF to 10 μF should be placed as
close as to the VDD2 pin of CA-IS1200 to filter the low-side power supply path.
High Voltage Bus VDD1
R11
High Side Front-End
R21 R51
IINP
R41
VINP
R31 VCM = 1.875 V
VINN R42
R32
R52
R61
IINN
To VCMOV Detector
GND1 R62
PGND
Figure 10-2 Typical Application for Voltage Sensing
10.1.5 Output Filter

Another first-order passive RC low-pass filter could be placed between the outputs of CA-IS1200 and the ADC to satisfy the
potential requirement for anti-aliasing filtering. The characteristics of this filter depends on the structure and sampling frequency
of the ADC. Choose R4 = R5 = 4.7 kΩ and C6 = 180 pF could provide a cutoff frequency of approximately 94 kHz.

10.1.6 Error Analysis in Voltage Sensing
The CA-IS1200 devices may also be used in the applications of voltage sensing as shown in Figure 10-2. The resistors R11, R21 and
R31 make up the resistor divider to scale down the high voltage from bus. Typically, the value of R11 and R21 is much larger than
R31 to keep the input voltage of CA-IS1200 within the specific range.
In CA-IS1200, resistors R41 and R51 (or R42 and R52) are used to set the gain of front-end amplifier. The typical values are R41 = R42
= 12.5 kΩ and R51 = R52 = 50 kΩ. Resistors R61 and R62 are used to sense the common-mode voltage of the input in CA-IS1200.
The typical values are R61 = R62 = 100 kΩ.
First, consider the situation in which R32 is not used. Additional gain error and offset would arise in these applications for CA-
IS1200. On the one hand, the limited input impedance of CA-IS1200 is parallel with the external sensing resistor R31, resulting in
impedance change and thus additional gain error. On the other hand, the output common-mode voltage VCM of the front-end
differential amplifier in CA-IS1200 is biased to 1.875 V, which would generate bias current IINP and IINN flowing through the front-
end resistor network. The bias current IINP also flows through R31 while IINN flows directly to PGND in the case of omitting R32,
which results in unbalance and thus additional offset.
To eliminate the effect of the bias current, resistor R32 equal to sensing resistor R31 is recommended to be added between VINN
and PGND. The resistor R31 would bring in additional gain error EGA and could be calculated as Eq. 1 describes.
EGA = R31 / (R31 + R41) (Eq. 1)
To reduce the effect of this gain error, the value of R31 should be chosen much smaller compared to R41. And this gain error could
also be minimized by the system-level gain calibration.
10.1.7 Caution
Do not leave the inputs of CA-IS1200 floating. If the VINP and VINN are left floating, the input common-mode voltage would be
pulled to a high level by internal bias, which could activate the fail-safe mode under certain power supply and may lead to
system-level abnormal reaction (refer to Fail-Safe Output for detailed information).

11 Package Information
11.1 DUB8 Package
The figure below illustrates the package details for the CA-IS1200U isolated amplifier in an 8-pin DUB package. The values for
the dimensions are shown in millimeters.

11.2 Wide Body SOIC8 Package
The figure below illustrates the package details and the recommended land pattern details for the CA-IS1200G isolated amplifier
in an 8-pin wide-body SOIC package. The values for the dimensions are shown in millimeters.

12 Soldering Information
TP
TP-5°C
tP
Max. ramp-up rate = 3°C/s Max. ramp-down rate = 6°C/s
Package surface temperature
TL
tL
Tsmax
Tsmin
ts
25°C Time
Time from 25°C to peak temperature TP

Figure 12-1 Soldering Temperature Curve
Table 12-1 Soldering Temperature Parameters

Profile Feature Pb-Free Soldering
Ramp-up rate (TL = 217°C to peak TP) 3°C/s max
Time ts of preheat temp (Tsmin = 150°C to Tsmax = 200°C) 60~120 seconds
Time tL to be maintained above 217°C 60~150 seconds
Peak temperature TP 260°C
Time tP within 5°C of actual peak temp 30 seconds max
Ramp-down rate (peak TP to TL = 217°C) 6°C/s max
Time from 25°C to peak temperature TP 8 minutes max

13 Tape and Reel Information
REEL DIMENSIONS TAPE DIMENSIONS
A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
*All dimensions are nominal
Reel Reel Pin1

Package Package A0 B0 K0 P1 W
Device Pins SPQ Diameter Width Quadran
Type Drawing (mm) (mm) (mm) (mm) (mm)
(mm) W1 (mm) t
CA-IS1200U DUB U 8 800 330 24.4 10.90 9.60 4.30 16.00 24.00 Q1
CA-IS1200G SOIC G 8 1000 330 16.4 11.95 6.15 3.20 16.00 16.00 Q1

14 Important Notice
The above information is for reference only and is used to assist Chipanalog customers in design and development. Chipanalog
reserves the right to change the above information due to technological innovation without prior notice.
Chipanalog products are all factory tested. The customers shall be responsible for self-assessment and determine whether it is
applicable for their specific application. Chipanalog's authorization to use the resources is limited to the development of related
applications that the Chipanalog products involved in. In addition, the resources shall not be copied or displayed. And Chipanalog
shall not be liable for any claim, cost, and loss arising from the use of the resources.
Trademark Information
Chipanalog Inc. ®, Chipanalog® are trademarks or registered trademarks of Chipanalog.
http://www.chipanalog.com


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CA-IS1200U, CA-IS1200G

上海川土微电子有限公司 Version 1.01, 2022/12/20

CA-IS1200 Isolated Amplifier for Current Sensing

temperature range. ADC

VRMS (CA-IS1200G) galvanic isolation per UL 1577. This CA-IS1200

Copyright © 2021, Chipanalog Incorporated

2 Copyright © 2021, Chipanalog Incorporated

Copyright © 2021, Chipanalog Incorporated 3

6 Pin Descriptions and Functions

VDD1 1 8 VDD2 VDD1 1 8 VDD2

VINP 2 CA-IS1200U 7 VOUTP VINP 2 CA-IS1200G 7 VOUTP

GND1 4 5 GND2 GND1 4 5 GND2

Figure 6-1 CA-IS1200 Top View

Table 6-1 CA-IS1200 Pin Description and Functions

4 Copyright © 2021, Chipanalog Incorporated

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Power Ratings

Copyright © 2021, Chipanalog Incorporated 5

6 Copyright © 2021, Chipanalog Incorporated

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8 Copyright © 2021, Chipanalog Incorporated

VINP = 0 to 0.25 V step;

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10 Copyright © 2021, Chipanalog Incorporated

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12 Copyright © 2021, Chipanalog Incorporated

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Figure 7-25 Input CMRR vs Frequency Figure 7-26 PSRR vs Frequency

Figure 7-29 Nonlinearity vs Temperature Figure 7-30 Nonlinearity vs Supply Voltage

14 Copyright © 2021, Chipanalog Incorporated

Isolated Supply Low-side Supply

High Voltage Surge Generator 1

Figure 8-3 Delay Time Test Waveforms

Copyright © 2021, Chipanalog Incorporated 15

VREF_HS UVLO VREF_LS

Figure 9-1 Functional Block Diagram of CA-IS1200

9.2 Feature Description

9.2.2 Signal Transmission Across Isolation Barrier

16 Copyright © 2021, Chipanalog Incorporated

Transmitter (TX) Receiver (RX)

Figure 9-2 Block Diagram of an Isolation Channel

Figure 9-3 Conceptual Operation Waveforms of OOK Modulation Scheme

9.2.3 Fail-Safe Output

Copyright © 2021, Chipanalog Incorporated 17

18 Copyright © 2021, Chipanalog Incorporated

Gate Driver CA-IS1200

Figure 10-1 Typical Application for Current Sensing

10.1.2 Choose Proper Rshunt

Copyright © 2021, Chipanalog Incorporated 19

10.1.3 Input Filter

10.1.4 Power Supply Recommendations

High Voltage Bus VDD1

R31 VCM = 1.875 V

Figure 10-2 Typical Application for Voltage Sensing

10.1.5 Output Filter

20 Copyright © 2021, Chipanalog Incorporated

EGA = R31 / (R31 + R41) (Eq. 1)