JVC GR-DVL9800 Technical Guide

VIDEO TECHNICAL GUIDE
DIGITAL VIDEO CAMERA
GR-DVL9800
NTSC/PAL
COPYRIGHT 2000 VICTOR COMPANY OF JAPAN, LTD.
March 2000
INDEX
SECTION 1 OUTLINE OF THE PRODUCTS
1.1 DIFFERING POINTS BETWEEN MODELS .........................................................................1-1 1.1.1 Table list differing points between models (GR-DVL9500/GR-DVX7/DVM70/GR-DVL9800) .........................................................1-1
SECTION 2 EXPLANATION OF NEW TECHNOLOGIES

2.1 NEW TECHNOLOGIES EMPLOYED IN GR-DVL9800 ........................................................2-1 2.1.1 Double duties as a digital movie camera and a digital still camera .................................2-1 2.1.2 1/3"-type Progressive scan CCD having 680,000 (*800,000) pixels ...............................2-2 2.1.3 High resolution system printing function.........................................................................2-8 2.1.4 Analog input terminal .....................................................................................................2-8 2.2 EXPLANATION OF DCF ......................................................................................................2-9 2.3 EXPLANATION OF DPOF....................................................................................................2-12
SECTION 3 EXPLANATION OF ELECTRICAL CIRCUIT

3.1 CIRCUIT OUTLINE ..............................................................................................................3-1 3.1.1 Basic block diagram.......................................................................................................3-1 3.2 EXPLANATION OF CCD CIRCUIT.......................................................................................3-2 3.2.1 CCD OPERATIONS.......................................................................................................3-2 3.2.2 EXPLANATION OF CCD DRIVE CIRCUIT ....................................................................3-4 3.3 EXPLANATION OF CAMERA CIRCUIT ...............................................................................3-7 3.3.1 Signal flow in GR-DVL9800 ...........................................................................................3-7 3.3.2 Camera section CPU functions ......................................................................................3-13 3.4 EXPLANATION OF DECK CIRCUIT ....................................................................................3-36 3.4.1 PLL operation ................................................................................................................3-36 3.4.2 Deck section CPU functions...........................................................................................3-38 3.5 EXPLANATION OF POWER SUPPLY CIRCUIT ..................................................................3-55 3.5.1 Power supply circuit block diagram ................................................................................3-55 3.5.2 Power supply section IC function ...................................................................................3-57
INDEX-1
SECTION 1 OUTLINE OF THE PRODUCTS

1.1 DIFFERING POINTS BETWEEN MODELS
1.1.1 Table list differing points between models (GR-DVL9500/GR-DVX7/DVM70/GR-DVL9800) (1/3)
Model Function Battery GR-DVL9500 BN-V607 (7.2V 770mAh) BN-V615 (7.2V 1540mAh) GR-DVX7/GR-DVM70 BN-V507 (7.2V 700mAh) BN-V514 (7.2V 1400mAh) GR-DVL9800 BN-V607 (7.2V 770mAh) BN-V615 (7.2V 1540mAh) BN-V628 (7.2V 2800mAh) new Continuous shooting time: when VF is used: BN-V607: 1hr.20min. BN-V615: 2hrs.40min. BN-V628: 4hrs.30min. BN-V856: 9hrs. when LCD is used: BN-V607: 1hr.5min. BN-V615: 2hrs.10min. BN-V628: 3hrs.50min. BN-V856: 7hrs.30min. Yes: AA-V67 adaptable batteries: BN-V607/BN-V615/BN-V628 quick charge battery: BN-V628 charging current: 770mA(BN-V607/BN-V615) 1300mA(BN-V628) Approx.620g (without cassette,MMC and battery) Approx.700g (incl. cassette,MMC and battery) 0.55" 180k pixels H. resolution: 400 lines Polycrystal silicon transistor 3.5" 200k pixels H. resolution: 440 lines Polycrystal silicon transistor 1/3 680k(*800k) Effective Video 360k(*420k) DSC XGA 630k(*740k) Progressive scan CCD JVC original Complementary Color filter moving and still images Yes: Vertical 2x, Horizontal 2x, 4x Excess pixels method Yes F1.8 f=5.0 to 50mm Filter diameter 37mm
Continuous shooting time: when VF is used: BN-V607: 1hr.5min. BN-V615: 2hrs.10min. BN-V856: 7hrs.30min.
Continuous shooting time: when VF is used: BN-V507: 1hr.5min. BN-V514: 2hrs.10min. BN-V840: 5hrs. BN-V856: 8hrs.30min. when LCD is used: BN-V507: 55min. BN-V514: 1hr.55min. BN-V840: 4hrs.30min. BN-V856: 7hrs.30min. No
when LCD is used: BN-V607: 50min. BN-V615: 1hr.40min. BN-V856: 6hrs. Quick charging No
Weight
Approx.650g (without cassette and battery) Approx.730g (incl. cassette and battery) 0.55" 113k pixels H. resolution: 260 lines Polycrystal silicon transistor 3.8" 112k pixels H. resolution: 240 lines Amorphous silicon transistor 1/3 380k(*450k) Effective 360k(*420k) Progressive scan CCD JVC original Complementary Color filter
Approx.435g (without cassette,MMC and battery) Approx.520g (incl. cassette,MMC and battery) 0.55" 180k pixels H. resolution: 400 lines Polycrystal silicon transistor 2.5" 180k pixels H. resolution: 400 lines Polycrystal silicon transistor 1/4 680k(*800k) Effective 340k(*400k)
Viewfinder
LCD monitor
Image device
Progressive scanning moving and still images High speed recording Yes: 2x DIS Spotlight (to darken quickly) Lens specification Magnification method No F1.8 f=5.0 to 50mm Filter diameter 37mm
DSC only (Rapid mechanical shutter) No Excess pixels method F1.8 f=3.6 to 36mm Filter diameter 27mm
Table 1-1-1 Table list differing points between models (GR-DVL9500/GR-DVX7/DVM70/GR-DVL9800) (1/3)
1-1
Table list differing points between models (GR-DVL9500/GR-DVX7/DVM70/GR-DVL9800) (2/3)

Model Function Sensitivity GR-DVL9500 12 Lux (Gain up mode: AGC) AGC: AGC ON + slow shutter OFF 6 Lux (Gain up mode: Auto) Auto: AGC ON + slow shutter 1/30 1 Lux (P.AE/EFFECT: SLOW 10x) SLOW 10x: slow shutter 1/6 Optical zoom: 10X Digital zoom: 4X/20X Max.zoom: 200X No 1/60(*1/50), 1/100, 1/250, 1/500 GR-DVX7/GR-DVM70 18 Lux (Gain up mode: AGC) AGC: AGC ON + slow shutter OFF 9 Lux (Gain up mode: Auto) Auto: AGC ON + slow shutter 1/30 1.8 Lux (P.AE/EFFECT: SLOW 10x) SLOW 10x: slow shutter 1/6 Optical zoom: 10X Digital zoom: 4X/10X Max.zoom: 100X GR-DVL9800 25 Lux (Gain up mode: AGC) AGC: AGC ON + slow shutter OFF 12 Lux (Gain up mode: Auto) Auto: AGC ON + slow shutter 1/30 2.5 Lux (P.AE/EFFECT: SLOW 10x) SLOW 10x: slow shutter 1/6 Optical zoom: 10X Digital zoom: 4X/20X Max.zoom: 200X Yes: 0.7x 1/60(*1/50), 1/100, 1/250 (1/500 was deleted) BLACK/WHITE/BK&WH (MOSAIC Fader was deleted) OFF/5S/ANIM. (5SD was deleted) "5S" was moved from P.dial to Menu. AUTO/ON/OFF
Zoom ratio
PS WIDE Shutter speed Fader Scene
BLACK/WHITE/BK&WH/MOSAIC 5S/5SD/ANIM.
Date/Time Auto Flash Snapshot
ON/OFF Yes: Auto/ON/OFF Red-Eye reduction: ON/OFF 6 mode with Frame Full Negative/Positive (during recording) Pin-up Pin-up 4-division Pin-up 9-division Yes (SP 32kHz only) Yes (SP only) No
Yes: Auto/ON/OFF/Auto Red-Eye Yes: Auto/ON/Auto Red-Eye The flash is closed: OFF 5 mode with Frame Full Pin-up Pin-up 4-division Pin-up 9-division 6 mode with Frame Full Negative/Positive (during recording) Pin-up Pin-up 4-division Pin-up 9-division Yes Dual: Video recording on the tape DSC(VGA) recording on the MMC Yes (Excluding Nega-Posi) Yes: press "INDEX SCREEN" Storage Media: MMC File system: JPEG (DCF compliant) Picture quality: 3 mode
Audio dubbing Insert editing Dual Shooting
No No Snapshot REC select: Tape/ Tape & Card selectable Yes Storage Media: MMC File system: JPEG Picture quality: 3 mode
Snapshot in PB Snapshot search DSC Recording function
Yes (Excluding Nega-Posi) No No
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Table list differing points between models (GR-DVL9500/GR-DVX7/DVM70/GR-DVL9800) (3/3)

Model Function DSC Playback function No GR-DVL9500 GR-DVX7/GR-DVM70 Index Playback: Yes Slide show: Yes Special Effect: Monotone/Sepia Multi-Image: same4/16 selected4 Protecting Images: Selected image Deleting Images: Selected/All Copying Image: Tape to MMC MMC to Tape GR-DVL9800 Index Playback: Yes Slide show: No Special Effect: Monotone/Sepia Multi-Image: same16 Protecting Images: Selected image Deleting Images: Selected/All Copying Image: Tape to MMC(VGA) MMC(XGA/VGA) to Tape 5sec DPOF setting: 1 print for each Selecting and No. of prints Yes Yes Yes In/Out Yes In/Out Yes In/Out Yes In/Out Yes (shared with Edit terminal) Yes (shared with JLIP terminal) Yes Yes (using the PC terminal) No Yes: for an optional Printer Multimedia Navigator Ver2.0 JLIP Video Capture Ver3.1 JLIP Video Producer Ver2.0 Picture Navigator for Win Ver2.1 Picture Navigator for Mac Ver2.1 NewSoft Presto! Mr.Photo Ver1.6 PhotoAlbum Ver2.0 ImageFolio Ver4.1.7 PC Cable: 2.5 - D-sub 9pin JLIP Cables: 3.5 4pin-4pin EDIT Cables: 3.5 4pin-2pin
Headphone terminal
Yes (shared with AV terminal)
only Docking Station only Docking Station only Docking Station only Docking Station only Docking Station only Docking Station (using the PC terminal) Yes: IrTran-P Multimedia Navigator Ver1.0 JLIP Video Capture Ver3.0 JLIP Video Producer Ver1.1 Picture Navigator for Win Ver2.1 Picture Navigator for Mac Ver2.1 NewSoft Presto! Mr.Photo Ver1.2 PhotoAlbum Ver1.5.7 ImageFolio Ver4.1.6
Ext. Mic. input terminal Yes AV output terminal AV input terminal S output terminal S input terminal JLIP terminal Edit terminal PC terminal Digital still output DV in/out IrDA Printer terminal JLIP related JLIP Video Capture Ver2.1 JLIP Video Producer Ver1.1 Yes (shared with HP terminal) No Yes No Yes (shared with Digital still output) Yes No Yes (shared with JLIP terminal) Yes No No
NewSoft Presto! Mr.Photo Ver1.2 PhotoAlbum Ver1.5.7 ImageFolio Ver4.1.6
JLIP-PC Cable: 3.5 - D-sub 9pin PC Cable: 2.5 - D-sub 9pin (with level converter) JLIP Cables: 3.5 4pin-4pin EDIT Cables: 3.5 2pin-2pin EDIT Cables: 3.5 2pin-2pin JLIP ID number RTC backup Reset SW 06
Equipped with secondary battery Equipped with secondary battery Yes: only for clear of Date/Time No
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SECTION 2 EXPLANATION OF NEW TECHNOLOGIES

2.1 NEW TECHNOLOGIES EMPLOYED IN GR-DVL9800
2.1.1 Double duties as a digital movie camera and a digital still camera 1. Function as a digital still camera The GR-DVL9800 is capable of still picture recording in the high resolution XGA size 1024 768 pixels in addition to the VGA size 640 480 pixels that is generally adopted for previous models. This performance is realized by the technology that employs the new progressive scan CCD having mass pixels (to be explained later) and process the whole image area including camera shake compensation area as a still picture area. As the recording media, two kinds of Multimedia cards (to be abbreviated as MMC in the following) are to be used, namely, the 4MB MMC is supplied as the standard MMC and the 8MB MMC is supplied as the optional MMC. Number of still pictures that can be recorded in the 4MB MMC or 8MB MMC varies depending on the image size and picture mode (resolution). The following table shows approximate number of storable pictures by image size and picture mode (resolution).
Image size VGA XGA Capacity 4MB 8MB 4MB 8MB Picture mode (resolution) Fine (F) 25 cuts 50 cuts 10 cuts 20 cuts Standard (S) 40 cuts 80 cuts 16 cuts 32 cuts Economy (E) 65 cuts 130 cuts 32 cuts 64 cuts
Table 2-1-1 Approximate number of storable pictures The image filing system of the GR-DVL9800 conforms to the DCF (Design rule for Camera File system) of the camera file system standard. With rapid popularization of the digital still camera in recent years, the users have greatly requested compatibility of digital picture data and related products so that they can use digital data more widely such as playback by other digital camera, direct output by digital printer, data processing by mobile personal computer, etc. regardless of brands and models. Under those circumstances, the DCF standard provides detailed rules for the image file management system for the digital still camera and related products. The image filing system of this model also conforms to the DPOF (Digital Print Order Format) standard that is provided for the print service industry for memorizing data on desired cuts for printing and desired number of each print in the storage media. 2. DUAL MODE for simultaneous recording of images as both motion picture and still pictures The GR-DVL9800 employs a new function that enables the user to record image as still pictures on the MMC while recording the same image on the tape as usual video recording. Since the STILL picture button and TRIGGER button of this model can be operated individually, only still pictures are recorded on the MMC without video recording on the tape when the STILL picture button is pressed. If the STILL picture button is pressed during usual video recording, scene at a decisive moment is recorded on the MMC as a still picture while the image is continuously recorded as a motion picture. However, the shot recorded as a still picture during video recording is processed as the VGA-sized image only. Moreover, for checking the scene to be recorded as a still picture, a supplementary small screen appears in respective corners of the viewfinder and monitor screens in the DUAL mode as shown in the figure below. Pressing the STILL picture button halfway actuates this function, and pressing the button to the extent records the scene on the MMC.
Main Picture Video
Sub
Still Picture
Fig. 2-1-1 VF/monitor screen

2-1
2.1.2 1/3"-type Progressive scan CCD having 680,000 (*800,000) pixels

EIS area Optical Black 1002 962
662 (*782)
654 (*774)
480 (*576)
962 654 (*774) Effective area PS-Wide / DSC-XGA 720
Effective area Video / DSC-VGA
Fig. 2-1-2 Effective image area of CCD 1. XGA image size still picture recording The GR-DVL9800 employs a CCD having 680,000 (*800,000) pixels in whole, however, 720 480 (*720 576) pixels among 680,000 (*800,000) pixels are used as the image size for DV tape recording according to the DV standard. The area that the optical black is reduced from the whole image area of the CCD is called the EIS (Electrical Image Stabilizer) area. In practice, camera shake is compensated by changing the location of the effective image area 720 480 (*720 576) according to information on camera shake detection. Generally, the pixel of a CCD used for the video camera is not square but it is oblong for improving resolution in the horizontal direction, and the aspect ratio of 4:3 (breadth to length) is made by the whole construction of the pixels 720 480 (*720 576). If data on video recorded image is transferred to a personal computer or digital still camera as its aspect ratio is 4:3, there occurs some trouble caused by difference in aspect ratio between the digital video camera and the personal computer/digital still camera for which square pixels are used. Therefore, the square grid conversion is carried out for recording as the VGA size 640 480 on the MMC. For recording the image as the XGA size on the MMC, the whole effective image area 962 654 (*962 744) including the EIS area is used. At that time, the image data is converted into the XGA size 1,024 768 by the image density conversion. The JPEG data compression is carried out for recording image data on the MMC and image the data is saved as a JPEG file. The difference in the three picture quality modes of fine, standard and economy originates from the difference in the compression ratio. Therefore, the size of a file varies depending on the picture quality mode and the number of storable images accordingly varies by mode. 2. Progressive super wide mode (PS wide mode) Since the progressive super wide (PS wide) mode utilizes the whole effective image area including the EIS area, it realizes an extra wide-angle 0.7 time as wide as the optical wide-end position. In other words, this mode is equivalent to a 0.7 time wide-angle conversion lens if it is attached to the lens. However, the electronic zoom function is unavailable in this mode. Therefore, this mode gives a 14-times zoom ratio in total (0.7 to 10 times). The usual shooting mode in which the actual image area is cut out of the whole effective image area as a result of the camera shake compensation. The PS wide mode cuts the actual image area out of the whole effective image area according to the zoom ratio and reduces the cutout image to the usual size 720 480 (*720 576) by digital processing.
2-2
Cutting out an effective area at the FMC(EIS)
Effective area EIS area Reducing the size of picture by FMC
Normal size Picture area is extended beyond the optical wide angle using EIS area.
200 X Digital Zoom
10 X Optical Zoom
1 X Digital Wide
0.7 X
PS Wide Mode : Total 14 X

Note 1) Digital zoom cannot be used when the PS-WIDE mode is set. Note 2) EIS cannot be used when the PS-WIDE mode is set.
Fig. 2-1-3 PS wide mode
2-3
3. New high-speed recording and progressive slow-motion playback In addition to the usual horizontal 2 double speed recording mode, this model performs vertical 2 and 4 high-speed recording. Therefore, the user can enjoy a high-speed recording of 240 (*200) frames per second at the 4 mode as well as slow-motion playback of fine and clear picture. In the usual CCD operation, the signal charged for a field period 1/60 (*1/50) second is read out for 1/60 (*1/50) second. However, in the high-speed recording mode the signal charging time for 1 field is shortened to 1/120 (*1/100) second or 1/240 (*1/200) second, and the signal readout time must be also shortened. If signal readout is operated for the whole CCD area, it requires raising the signal transfer rate 2 times or 4 times as fast as the usual. Speedup of signal transfer needs improvement of the signal processing circuit, and if such the product is manufactured, it is unsuitable for general use because of the production cost. If it is possible to process charge signal of the whole CCD area, a special VTR is needed to record such the mass image data. This model adopts a new technology that charges in a part of the CCD area is read out at the usual speed while draining out charges in the other part at a high speed. Therefore, image data for 2 frames or 4 frames can be recorded in the area for 1 field that is divided into 2 or 4 for this video recording. By the way, the following explains difference of the high-speed recording from the high shutter speed recording. In the high shutter speed recording, the exposure time is shortened from the standard 1/60 (*1/50) second to 1/250 second and so on as same as the high-speed recording. However, the high shutter speed recording takes 1/60 (*1/50) second to read out the charge for 1 field. In other words, number of frames that are read out for a second is 60 though the exposure time for each frame is shorter than the standard mode. Therefore, the high shutter speed recording is suitable for recording a fastmoving object and playing it back in still mode. This model provides two kinds of high shutter speeds, namely, 1/100 second and 1/250 second, but 1/100 second is provided for flicker prevention under the fluorescent light. Either of the above-mentioned recording modes needs sufficient lighting, because exposure time is comparatively shorter than the standard mode and the sensitivity is accordingly lowered.
1 field VD
Normal 1/60 (*1/50)
2X High Speed 1/120 (*1/100) 4X High Speed 1/240 (*1/200) Read Out Timing 1/240 (*1/200) 1/240 (*1/200) 1/240 (*1/200) 1/120 (*1/100)
Fig. 2-1-4 Signal charge of CCD in high-speed recording

2-4
1 field VD
Normal 1/60 (*1/50)
1/250 High shutter speed 1/250 Reset Read Out Timing
Fig. 2-1-5 Signal charge of CCD in high shutter speed recording In the high-speed video recording, the recording area is a rectangular part in the vertical center in the horizontal 2 mode, or an oblong part in the horizontal center in the vertical 2 mode, or a small part in the center of the image area in the 4 mode. However, the actual areas used for the respective modes are smaller than 1/2 and 1/4 of the effective image area, because a certain period of time is needed to drain out waste charges at a high speed.
Additional functions of area selecting and 4X PS-CCD 2X Horizontal

High speed sweeping area Image area High speed sweeping area
New 2X Vertical 4X
4X mode Image area
High speed sweeping area
2X Vertical mode Image area
Fig. 2-1-6 Actual image area in high-speed recording

2-5
Image data that is processed at a rate of 120 or 240 frames per second cannot be recorded on the video tape or output as video signal. Therefore, the area for 1 field is vertically or horizontally divided into two to record two frames as usual video signal in the 2 speed recording mode, or divided into four to record four frames as usual video signal in the 4 speed recording mode. Images of high-speed video recording, playback by another DVC and DV output are shown in the upper part of the following figure. The monitor out images in EE or playback using this camera appears only the first frame on the screen and then it is masked by the upper and lower sides or right and left sides or by all sides as the lower part of the following figure.
Normal
60(*50) frames/sec
2X Horizontal
120(*100) frames/sec
2X Vertical
4X
Images recorded on the TAPE
(PB by other DVC or DV OUTPUT)
VIDEO OUTPUT or LCD MONITOR of GR-DVL9800
Fig. 2-1-7 Recording and playback images of high-speed recording mode The progressive slow-motion playback function realizes smooth slow-motion playback of a video picture of fast-moving object that is recorded at the high speed of 120 or 240 frames per second. The slow-motion playback rate of this model is 1/8 as slow as the standard. When video picture that is recorded at the standard speed is played back in slow-motion, one frame is played back repeatedly 8 times by memorizing the frame. When video picture that is recorded at the high speed, two different frames are repeatedly played back 4 times respectively in case of the 2 speed recording, or four different frames are repeatedly played back 2 times respectively in case of the 4 speed recording.
2-6
Field image of 2X Horizontal mode recording
1/60
Arrenging images at FMC in Camera section

A B B B
1/60
1/60
1/60
1/60
1/60
1/60
1/60
1/60
1/8 Slow-Motion Playback

Fig. 2-1-8 Progressive slow playback (picture of horizontal 2 speed recording)
A B
Field image of 2X Vertical mode recording
1/60

A B B B
1/60
1/60
1/60
1/60
1/60
1/60
1/60
1/60

Fig. 2-1-9 Progressive slow playback (picture of vertical 2 speed recording)
2-7
Field image of 4X mode recording
1/60

B C C D
1/60
1/60
1/60
1/60
1/60
1/60
1/60
1/60

Fig. 2-1-10 Progressive slow playback (picture of 4 speed recording) 2.1.3 High resolution system printing function The GR-DVL9800 has the printer terminal and the serviceable printing function that enables the user to print out the picture with ease just by connecting a cable between this camera and the exclusive printer for it. Moreover, the GR-DVL9800 is provided with the functions to input image data, to convert image data properly for printing, to carry out printing operation, which functions are generally provided in the printer side. Therefore, the user can enjoy printing out with the feeling for use of an accessory because he can get the exclusive digital printer at a comparatively low price. 2.1.4 Analog input terminal The GR-DVL9800 is provided with the analog input terminal. Therefore, important and commemorative analog video pictures recorded previously can be dubbed and saved as digital video pictures with this camera.
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2.2 EXPLANATION OF DCF

"DCF" is an abbreviation for "Design rule for Camera File system" that provides the standard and rules to transfer image files and image-related files among digital still cameras (to be abbreviated as DSC in the following) and related appliances for printing image recorded by the DSC by digital printer or other purposes. The DCF also provides the standard of directory and file construction for efficient recording and management of image data on the removable memory such as the MultiMedia Card (to be abbreviated as MMC in the following). Explaining the directory and file construction of image data to be recorded on the MMC in brief, the directory and file construction is made up by three layers; the first is the DCIM directory, the second is DCF directory under the DCIM, and the third is the image file under the DCF as shown in Fig. 2-2-1. Regarding the directory construction first, there is the DCF image route directory named "DCIM" (Digital Camera Images) just under the route directory as shown in Fig. 2-2-1. Further, there are multiple directories to save image files called the DCF directory just under the DCIM directory. Each DCF directory must be named in 8 characters (Roman letters and Arabic numerals - the same in the following), in which the high order 3 characters must be numbered by 100 to 999 (numbers from 000 to 099 are unusable) that represents the directory number. Other 5 characters of the rest are to be used for arbitrary naming with capital letters and digits of condensed type face. Image files are stored in the DCF directory. Each image file must be named in 8 characters (as said above), in which the first to the fourth characters must be entered by arbitrary condensed capital letters/numerals and the rest must be entered in number from 0001 to 9999 (0000 is unusable). Each image file is identified by this 8 characters. The extension to be used for the image file is "JPG".
MMC
DCIM 100JVCGR DVC00001.JPG
DVC00002.JPG DCF DIRECTORY DCF IMAGE DIRECTORY IMAGE FILE DVC00003.JPG
DVC09999.JPG
101JVCGR
DVC00001.JPG
Fig. 2-2-1 Directory and file construction of MMC
2-9
One DCF directory is capable of storing 9999 image files. If it is tried to store 10000 or more image files in one DCF directory, the 10000th and further image files are stored in the next DCF directory. 900 DCF directories (No. 100 to 999) can be contained in one MMC. According to the DCF standard, the GR-DVL9800 determines the DCF directory name and image file name as shown in Fig. 2-2-2.
DCF IMAGE DIRECTORY DCF DIRECTORY IMAGE FILE NAME EXTENSION
DCIM - 100J V C G R - D V C 0 0001. J P G

Directory Number 100 - 999 File Number 0001 - 9999
When the DCF directory is full of image files (9999 files), a new DCF directory is set up for the 1000th and further image 10000th and further image files and it is named 101JVCGR.
Note: If there is an image file that is not the 9999th image file but is numbered "9999" (DVC09999) in a DCF directory (in other words, there are not 9999 image files in the directory actually), a new DCF directory is opened for the following image files.
Fig. 2-2-2 DCF directory name and image file name used in the DVL9800 When seeing the still picture index screen, such the identification name as "100-DVC00002" or "100DVC00007" is appearing in it. This represents a DCF directory number and image file number. There is an index number of three digits appearing in the upper part of each still picture index screen, however, the index number is not always the same as the image file number. In case of the left picture of Fig. 2-2-3, for example, the index number of 001 is selected but the image file number is 0002. The right picture shows the same, namely, the selected index number is 006 but the image file number is 0007. In the case still pictures are saved on a blank MMC (nothing is recorded on it), the index number of each picture corresponds to its image file number. However, if some image file is erased from the DCF directory, the image file number differs from the index number as shown in Fig. 2-2-3. Such the inconsistency results from that the index number is moved up by one each time an image file is erased but the image file number remains as it was after the image file is erased. However, if the image file of the last index number is erased and a new image file is saved, the index number of the erased file is taken over by the new image file. Taking the case of Fig. 2-2-3 for example, assume that the image file of the index number 006 that is the last index number is erased and a new image data is saved, the new image file is numbered 007 for its image file number.
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Fig. 2-2-3
Still picture index screen
When an image file is played back by the digital still camera, two numbers appear in the upper right part of the screen and lower left part respectively. The number in the lower left represents the index number of the image file currently in playback and number of still pictures (image files) saved already. In case of Fig. 22-4, 8/8 indicates that the picture currently in playback is the 8th of 8 pictures saved on the MMC. The number appearing in the upper right corner represents the DCF directory name and image file number. In case of Fig. 2-2-3, the picture currently in playback is the 9th image file saved in the DCF directory named 100JVCGF. Be careful not to mistake this indication for the meaning that 9 image files have been saved in the capacity for recording 100 image files. Moreover, keep it in mind that the index number is moved up when some image file is erased from the memory but the image file number is not moved up in the same case. Taking Fig. 4 for example, the index number is 8 but the image file number is 0009. Explaining again, the index number is not always corresponding to the image file number.
Fig. 2-2-4 Screen of still picture playback by DSC
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2.3 EXPLANATION OF DPOF

DPOF (Digital Print Order Format) means the automatic print data format to be used for printing pictures taken by the digital still camera (to be abbreviated as DSC) by the digital printer. The DPOF file is saved together with image files in a detachable memory such as the MultiMedia Card (to be abbreviated as MMC). If the user specifies desirable frames and number of prints of each picture to be printed out by marking while checking playback images on the DSC monitor, the specified data (frames to be printed out and number of prints of each frame) are recorded in the DPOF file. Since the DPOF file is saved in a detachable memory such as the MMC, the user is required only to bring the storage media (such as the MMC) in a print service shop to get desirable number of printouts of specified pictures. The DPOF file is named "Autprint.mrk" and it is saved in the MISC directory in the MMC root directory. The MISC directory is prepared in the same hierarchy as the DCIM (Digital Camera Images) directory, however, no MISC directory is prepared if no data is recorded in the DPOF file.
Fig. 2-3-1 DPOF directory Data in the DPOF file is written in the text style, namely, data on the items of the HEADER section are written first and those of the JOB section second as shown in Table 2-3-1. Among the items shown in Table 2-3-1 the item number 4 of the HEADER section and item number 5 of the JOB section are not used for the model GR-DVL9800.
HEADER section [HDR] Data common to all prints of the DPOF file are saved in this section. 1. Version of the DPOF file. 2. Product name that was used to save the DPOF file last. 3. Date and time when the DPOF file was saved last. 4. Information on the user (address, name, telephone number). [JOB] A JOB section is prepared for each picture. 1. Product ID. 2. Specified image file to be printed out. 3. Specified number of printouts. 4. Specified print type. 5. Other specifications (cropping, rotation, dating, etc.).
Contents
JOB section
Contents
Table 2-3-1 Contents of DPOF file

2-12
Fig. 2-3-2 shows an example of a DPOF file made up by the GR-DVL9800. In this example, the data in the [HDR] section show that the version of the DPOF file is 1.00 and the file was made up by a JVC DV camera at 09:32:46 (hour: minute: second), December 9, 1999, while the data in the [JOB] sections show that the two image files of DVC00001.JPG and DVC00005.JPG are specified to make one printout each.
Fig. 2-3-2 DPOF file
2-13
SECTION 3 EXPLANATION OF ELECTRICAL CIRCUIT

3.1 CIRCUIT OUTLINE
3.1.1 Basic block diagram
0 8 CCD
IC4201 OPTICAL BLOCK
V1A,V2A,V2C,V3A,SUB
0 1 MAIN
TBCI(12) AD(10) 108MHz TBCO(12) OUT_Y(4),OUT_C(4)
0 7 MONITOR
IC7300
R G B
IC3801
ANALOG VIDEO I/O
DV_R-Y, DV_B-Y DV_Y DV_C
LCD_B-Y, LCD_R-Y LCD_Y
PS_CCD
V1B,V2B,V3B,VB
CCD_OUT
CDS/AGC A/D
AFZ_DATA
LCD DRIVER
IC3701
VIDEO AMP
MONI LCD PANEL
H1, H2, RG
X4301
IRIS PWM
IC4301
CAMERA_DSP
TBC_DYO(4),TBC_DCO(4)
VINC
TBC_VRT,VRB
TBC_SDO
VINY
IC4102 V.DRV IC4101 V.DRV
VD, HD
DYO(4),DCO(4) DYI(4),DCI(4) CA_DS_Y(8), CA_DS_C(8) DS_CA_Y(8), DS_CA_C(8) BUS(16)
TBC_SDI
EXT_V_IN EXT_Y_IN EXT_C_IN EXT_IN_L S_IN_L
IC7400 LCD DRIVER
R G B
IC5001
TG
FCK DATA
VF LCD PANEL
EXT_IN_H
CK72
IC1002
OSD_DATA
SP
IND,FRG
FOCUS (4)
ZOOM (4)
DRIVE+,-
0 2 DSC
IC4802,IC4803 IC4804,IC4805 IRIS DRIVER
IRIS_O/C
36A
ON SCREEN LCDIND_R,_G,_B,LCDFRG
Y_GCTL,C_GCTL
72MHz VCXO IC5402
PC
IC5401
0 6 JACK
J601
Y_OUT C_OUT
S_IN/OUT
IC3002
RD(16)
1 4 VCO
IRIS PWM
IC3101
1394PHY
TPA+,TPATPB+,TPBJ602
IC3401
EVR DAC
AFZ_DATA
RA(10)
16M DRAM
H_GAIN,H_OFFSET
IC3001
PHY_D(4)
DV_IN/OUT
IC4851
FOCUS DRIVER & ZOOM DRIVER IC1004
AFZ_DATA
DECK_DSP
IC3201
PBO PBDATA ADDT(16) DODAT AIDAT
IC3301 IC3501
DVANA
PB_ENV ATFO VIDEO HEAD 1F 1S 2F 2S
IC1003 E 2P R O M
RTC
32kHz
DVEQ
HSE ADDT(16)
HSE
REC AMP & PB AMP
IC1201
M_OUT1, M_OUT2
X1002
S_DT_OUT
SHUTTER MDA
S_OPEN S_CLOSE
IC1001
SYSCON CPU
S_DT_IN AD(16) M32_DT_OUT M32_DT_IN
IC1401
DECK CPU
ADDT(16) ANA_DATA AU_LCD_IN MDA_IN
RECC_ADJ ANA_DATA MAIN_VCO,FS_PLL,ATF_GAIN
0 9 PRE/REC
V_OUT AV_IN/OUT
RXD
TXD
IC1009
SRV_RX TXD SRV_TX
IF_TX
STROBE SENSOR SECTION
STO_OFF STO_OPEN STRB_AD
S_OPEN,S_CLOSE
STRB_CHG SENSPULS GATEPULS
REM_OUT
IF_RX
RXD
IC2101
AUDIO A/D, D/A
HP_OUT
SENS_EVR
EXT_MIC
0 5 FRONT 0 6 JACK
MIC_AU / R PB_AU / R PB_AU / L
J604 GND
IC8002
S_D(16) S_A(12)
MIC_AU / L
IC1302
PC_TX PC_RX
PC
TX RX EDIT
IC8001
J603 RX TX GND
16M SDRAM
C_COIL_U C_COIL_V C_COIL_W AO_SIG / L LINE_IN / L
CAP MOTOR
JLIP_RX JLIP_TX
JLIP
SDI SRCLK XSDEN DREQ
IC8004
32D(16) 32A(25) 32A(19)
SPK+,SPK-
DSC_IF
8M FLASH
FADE_CTL
AO_SIG / R
IC2201
AU_LCD_IN
LINE_IN / R HP_SIG / L HP_SIG / R EX_MIC / L
MDA_IN
IC1601
MDA
D_COIL_U D_COIL_V D_COIL_W
DRUM MOTOR
MMC_DATA MMC_CMD MMC_CS MMC_CLK MMC_CD
JLIP_L
J605
IC8003
M32_RX CPU
MIC UNIT INT_MIC / R
AUDIO AMP
PRN_RX PRN_TX P_ON_L
M32_RX M32_TX
PRIN. OUT
EX_MIC / R INT_MIC / L
LOAD_FWD LOAD_REV
LOAD MOTOR
0 2 DSC
MMC
0 4 MDA
Fig. 3-1-1 Basic block diagram
3-1
3.2 EXPLANATION OF CCD CIRCUIT

3.2.1 CCD OPERATIONS 1. Table of CCD specification
Type Total pixels Effective pixels Unit cell size Optical black Dummy bits Color filter 1/3-type Progressive Scan CCD 1002(H) 662(V) approx. 680,000 pixels *1002(H) 782(V) approx. 800,000 pixels 962(H) 654(V) approx. 630,000 pixels *962(H) 774(V) approx. 750,000 pixels 5.1 5.6 m *5.1 4.7 m H direction: front 4 pixels, rear 36 pixels V direction: front 6 pixels, rear 2 pixels H direction: front 4, rear 36 V direction: front 6, rear 3 W,G,Cy,Ye complementary filter Note: * for PAL model
Table 3-2-1 CCD specification 2. CCD optical black assignment

FHOB 4 BHOB 36
BVOB 2
H.Dummy bits 2 962 Optical black
654 (*774) Effective area
FVOB 6
V.Dummy bits 3 1002
H.Dummy bits 6
H.Dummy bit 1
Fig. 3-2-1 Optical black assignment
3-2
3. CCD pin assignment and block diagram

Photo Sensor
Vertical Shift Register
9 10 11 12 13
V1A V1B V2A V2B V2C V3A V3B VB
PW
3 Output
14 15 16
VO OD
4 1
Horizontal Shift Register
2 R
5 PT
6 SUB
7 H2
8 H1
Fig. 3-2-2 CCD pin assignment and block diagram 4. Table of CCD pin functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OD R PW VO PT SUB H2 H1 V1A V1B V2A V2B V2C V3A V3B VB Label In/Out In In In Out In In In In In In In In In In In In Output drain Reset gate clock P-Well (GND) Signal output Protect P-Well bias Substrate (over flow drain) Horizontal register transfer clock (2) Horizontal register transfer clock (1) Vertical shift register transfer clock (1A) Vertical shift register transfer clock (1B) Vertical shift register transfer clock (2A) Vertical shift register transfer clock (2B) Vertical shift register transfer clock (2C) Vertical shift register transfer clock (3A) Vertical shift register transfer clock (3B) Vertical shift register transfer clock (B) Description
Table 3-2-2 CCD pin functions

3-3
3.2.2 EXPLANATION OF CCD DRIVE CIRCUIT Note: Asterisked data in parentheses is for PAL version.
CCD
V2C V1A V2A V3A V1B V2B V3B SUB H1 H2 H2 VB
IC4201
CDS AGC A/D
ID1 ID2
Y/C PROCESS
IC4101
V.DRV_1
IC4102
V.DRV_2
DS1,DS2 ADCLK
IC4301
CAMERA_DSP
SUB
V1A CH1 V2A
V1B CH2 V2B
V2C
V3A
V3B
RG
H1 H2
IC5001 TG
DATA DCLK CS
VB
FCK (36MHz) HD,HDIN,VD,VDIN
CK72IN
X'tal 108MHz
SSG
from SYSCON
72MHz VCXO IC5402
PC IC5401
36A (36MHz)
X4301
Fig. 3-2-3 CCD drive block diagram The main role of the TG IC5001 is to generate various CCD drive pulses and it supplies them directly to the CCD or the V. DRIVER's. This IC operates timing with the 72 MHz master clock coming from the CK72IN, and the phase of the 72 MHz master clock is locked by the 36 MHz that the 108 MHz clock oscillated by the X'tal X4301 is divided by the SSG in the IC4301. On the other hand, the TG outputs the 36 MHz FCK to the SSG, which generates the horizontal reference pulse HD, HDIN and vertical reference pulse VD, VDIN and returns those pulses to the TG. The H1 and H2 are horizontal register drive pulses which are directly input to the CCD. The V1, V2 and V3 are vertical register drive pulses which are input to the CCD through the V. DRIVER's IC4101 and IC4102. The vertical transfer system is not the two-line mixing system but the three-phase drive system. The V1, V2 and V3 are basically the three-phase drive pulses, however, the V1A/V1B, V2A/V2B/V2C/VB, V3A/V3B are the same pulses in usual (except the high-speed recording mode in which the pulse mode may vary in part). Moreover, the TG generates the sampling pulses for the CDS and clock for the A-D converter, both of which are output to the IC4201. The odd line and even line identification signals are also output from this TG to the Y/C PROCESS block of the IC4301. Each mode of the TG is set according to the serial data supplied from the SYSCON.
3-4
Normal(EIS) reading out

High speed transfer (162-n)
All area reading out 962
962 492 (*584) 654 (*774)
High speed transfer (n lines)
Fig. 3-2-4 Normal read-out
Fig. 3-2-5 All area read-out
As compared with the previous progressive scan CCD that has two horizontal registers for reading all pixel data, this CCD has only one horizontal register. Therefore, this CCD can output pixel data for two lines in one horizontal period because of its double horizontal drive speed. The horizontal signal output timing of this CCD is as shown in the following figure. In case of the figure, the period of the HDIN is twice the HD.
HD
HDIN
1st Line OB 962 pixels OB
2nd Line 962 pixels OB
3rd Line 962 pixels
Fig. 3-2-6 Signal read-out timing in horizontal The vertical signal read timing in the usual readout mode is as shown in the figure below. 492 (*584) lines that are effective lines among all lines are read out, and other lines in the upper and lower parts are transferred at a high speed. If the camera shake compensation function (EIS) is activated at that time, the start point to read out effective lines is changed according to the EIS information. In other words, EIS in the vertical direction is roughly operated by the control of the point at which the CCD starts reading effective lines. The FMC block inside the CAMERA-DSP operates fine adjustment and cutout of the horizontal direction. Reading out of 492 (*584) lines is enough to operate fine adjustment, and the vertical line number is converted to the 480 (*576) line after EIS processing. Also the horizontal pixel number is converted to the 720 pixel. When the camera shake compensation function is inactivated, the start point to read out effective lines is fixed.
1 VD/VDIN 246 (*292) HD 492 (*584) Lines 262.5 (*312.5)
V-OB
High speed transfer
V-OB
Fig. 3-2-7 Normal read-out timing in vertical

3-5
In the all pixels readout mode, the whole 654 (*774) lines are read out in a period of 340.5 HD (*404.5HD). 654 lines are passed through the EIS and then the CAMERA DSP sends them to the DSC section in case of the NTSC system, otherwise 774 lines are converted to 768 lines deleted 6 lines at the EIS in case of the PAL system. The vertical signal read timing is as shown in the following figure.
1 VD 187 (*227) VDIN 340.5 (*404.5) HD 262.5 (*312.5) 525 (*625)
327 (*387) HD 654 (*774) Lines BVOB:2 FVOB:6
Fig. 3-2-8 All area read-out timing in vertical The arrangement of color filter on this progressive scan CCD are as shown in the following figures.
774 773 772 771 770 G Cy W Ye G W Ye G Cy W G Cy W Ye G W Ye G Cy W G Cy W Ye G W Ye G Cy W G Cy W Ye G W Ye G Cy W G Cy W Ye G W Ye G Cy W
654
W Ye G Cy W
G Cy W Ye G
W Ye G Cy W
G Cy W Ye G
W Ye G Cy W
G Cy W Ye G
W Ye G Cy W
G Cy W Ye G
W Ye G Cy W
653 C y 652 W
651 Ye 650 G
5 4 3 2 1
Cy W Ye G Cy
Ye G Cy W Ye 2
Cy W Ye G Cy 3
Ye G Cy W Ye 4
Cy W Ye G Cy 5
Ye G Cy W Ye
Cy W Ye G Cy
Ye G Cy W Ye
Cy W Ye G Cy
Ye G Cy W Ye
5 4 3 2 1
Cy W Ye G Cy
Ye G Cy W Ye 2
Cy W Ye G Cy 3
Ye G Cy W Ye 4
Cy W Ye G Cy 5
Ye G Cy W Ye
Cy W Ye G Cy
Ye G Cy W Ye
Cy W Ye G Cy
Ye G Cy W Ye
958 959 960 961 962
958 959 960 961 962
Fig. 3-2-9 Color filter arrangement in NTSC
Fig. 3-2-10 Color filter arrangement in PAL
The relation between the color line ID (ID1, ID2) and the signal output of CCD is as shown in the following figure.
HDIN V.Line (n 0) CCD OUTPUT 4n+1 Cy,Ye,Cy,Ye... 4n+2 G,W,G,W... 4n+3 Ye,Cy,Ye,Cy... 4n+4 W,G,W,G...
ID1
ID2
Fig. 3-2-11 Signal output and color line ID

3-6
3.3 EXPLANATION OF CAMERA CIRCUIT

3.3.1 Signal flow in GR-DVL9800 1. Signal flow in DSC picture recording mode
ANALOG VIDEO I/O JCP8019
D/A
Y/V C DV_IF IN
Y C R-Y B-Y
A/D A/D
YC SEPA
DEC
FRAME TBC
DV_IF OUT
ENC
D/A D/A D/A
AV OUT & MONI/VF
OUT_Y(4) OUT_C(4)
TBC_DYO(4) TBC_DCO(4)
TBCO(12)
TBCI(12)
E-E Monitor out
AD(10)
CAM_DSP JCY0119 DYO(4) DCO(4) 1394PHY
PS CCD
CDS AGC A/D
DV IN/OUT TAPE REC
Y/C
FMC/EIS
DVIO
DYI(4) DCI(4)
DECK DSP
HSE PBDATA
SRAM
DRAM 8Mb x 2
SRAM E-E Monitor out NTSC :720x480 PAL :720x576
AUTO
SSG
CA_DS_C(8) CA_DS_Y(8)
DSC Recording VGA NTSC:720x480 PAL:720x576 XGA NTSC:960x654 PAL:960x768 DSC_IF JCY0121-4
DS_CA_C(8) DS_CA_Y(8)
VERTICAL Lines Convert
VGA 640x480 XGA 1024x768
HORIZONTAL 720640 9601024
VERTICAL 576480 654768
LINE MEM
SDRAM CTL
S_DQ0-15
SIGNAL SELECTOR
HORIZONTAL Pixels Convert
JPEG
VGA NTSC:640x480 PAL:640x576 XGA NTSC:1024x654 PAL:1024x768 JPEG Compression
SDRAM
DMA CAMERA CPU

ADR0-15
CPU IF
IC inside configuration
M32DT_IN
SERIAL I/O_0
M32DT_OUT M32_CLK
CAMERA CPU
MMC_SO
RXD
SERIAL I/O_1 UART_1
MMC_SI MMC_SCLK
MMC
PC/JLIP
TXD
PRN_RX PRN_TX
M32_RX M32_TX
Save a JPEG file into the MMC
UART_2 BUS IF
A5-30 D0-15
FLASH ROM
PRINTER
SDI
PRINTER IF
M32Rx/D CPU
Make a JPEG file and Add a thumbnail
Fig. 3-3-1 Signal flow in DSC picture recording mode

3-7
In the DSC recordings, video signal coming from the CCD is Y/C-processed in the CAM DSP and then saved in the DRAM by the FMC. In the E-E mode, signal to be saved in the memory is repeatedly written and read, and the read signal is output to the monitor through the ANALOG VIDEO I/O IC. Signal to be output to the monitor is read out of the memory by interlaced scanning, and the image size is reduced by the FMC prior to signal output if the picture recording mode is set for the XGA size. Next, when the STILL picture button is pressed half, signal saved in the DRAM is repeatedly read out to the monitor while suspending new data write in it. Therefore, the image can be checked on the monitor before recording because the image data is not written on the MMC at that time. When the STILL picture button is pressed full, image data saved in the DRAM is read out through other output port with non-interlacing and sent to the DSC IF. At that time, the image size is the VGA (720 480 pixels for the NTSC, or 720 576 pixels for the PAL) or XGA (960 654 pixels for the NTSC, or 960 768 pixels for the PAL). The DSC IF first carries out horizontal image density conversion so that 720 pixels is converted into 640 pixels for the VGA size or 960 pixels into 1024 pixels for the XGA. Next, it converts 576 pixels into 480 pixels for the PAL VGA size or 654 pixels into 768 pixels for the NTSC XGA size without conversion of the vertical lines of the NTSC VGA size and PAL XGA size. As a result, the pixel density of the VGA size becomes 640 480 pixels and that of the XGA size becomes 1024 768 pixels for both the NTSC and PAL in common. After that, the image data is once saved in the SDRAM and then compressed by the JPEG circuit. The JPEG-compressed data is again saved in the SDRAM. In the previous models the M32Rx/D CPU carries out JPEG-compression with the software, however, this model carries out JPEG-compression by the hardware of the DSC IF at a comparatively higher processing speed than the previous models. The JPEG-compressed data is sent to the memory built in the M32Rx/D CPU through the DMA and BUS IF. Reading necessary programs out of the FLASH ROM, the M32Rx/D CPU additionally processes the image data for the header and thumbnail for preparing it as a JPEG file, which is saved in the MMC through the SERIAL I/O 1. In the DUAL mode, operation of the FMC of the CAM DSP circuit is slightly different. That is to say, image data to be recorded on the tape, in other words image data to be output to the DECK DSP, is not saved in the DRAM but output directly to the DECK DSP, because image data must be continuously recorded on the tape regardless of DSC recording operation. Therefore, the dual mode not only disables the digital effect such as digital zoom, etc. but also limits the image size of DSC recording to the VGA size only. When the STILL picture button is pressed half to check the E-E still picture on the monitor screen, the image output from the DRAM is reduced to be shown in the slave screen appearing small in the monitor screen.
3-8
2. Signal flow in DSC picture playback mode

ANALOG VIDEO I/O JCP8019
D/A
Y/V C DV_IF IN
Y C R-Y B-Y
A/D A/D
YC SEPA
DEC
FRAME TBC
DV_IF OUT
ENC
D/A D/A D/A
AV OUT & MONI/VF
OUT_Y(4) OUT_C(4)
NTSC :720x480 PAL :720x576
AD(10)
TBCO(12)
TBCI(12)
PS CCD
CDS AGC A/D
DV IN/OUT TAPE REC
Y/C
FMC/EIS
DVIO
DYI(4) DCI(4)
DECK DSP
HSE PBDATA
SRAM
DRAM 8Mb x 2
SRAM DSC PB out VGA :720x480 XGA :960x768 CA_DS_C(8) CA_DS_Y(8) DS_CA_C(8) DS_CA_Y(8)
AUTO
SSG
pass through
DSC_IF JCY0121-4 VERTICAL 576480 654768
HORIZONTAL 720 640 960 1024
LINE MEM
SDRAM CTL
S_DQ0-15
HORIZONTAL Pixels Convert VGA :640x480 XGA :1024x768
SIGNAL SELECTOR JPEG
SDRAM
JPEG Expansion
DMA CAMERA CPU

ADR0-15
CPU IF
IC inside configuration
M32DT_IN
SERIAL I/O_0
M32DT_OUT M32_CLK MMC_SO
CAMERA CPU
RXD
SERIAL I/O_1 UART_1
MMC_SI MMC_SCLK
MMC
PC/JLIP
TXD
PRN_RX PRN_TX
M32_RX M32_TX
Read a JPEG file from MMC
UART_2 BUS IF
A5-30 D0-15
FLASH ROM
PRINTER
SDI
PRINTER IF
M32Rx/D CPU
Fig. 3-3-2 Signal flow in DSC picture playback mode

3-9
In playing back a DSC picture, the M32Rx/D CPU reads a recorded file out of the MMC and saves it in the internal DRAM once. Then, the M32Rx/D CPU extracts image data from the file and transfers it to the SDRAM through the vertical line converter circuit, which passes the transferred image data without conversion. In DCS picture playback, vertical line conversion is carried out by the FMC of the CAM DSP. The image data transferred to the SDRAM is extended in the reverse manner for recording. After that, the image data undergoes horizontal image density conversion so that 640 pixels is converted into 720 pixels for the VGA size or 1024 pixels into 960 pixels for the XGA size, then the converted image data is sent to the CAM DSP. In the CAM DSP the image data is saved in the DRAM by the FMC through the DVIO. The image data saved in the DRAM is repeatedly read out to be output to the monitor. At that time, the FMC converts the image size so that it comprises 720 480 pixels for the NTSC or 720 576 pixels for the PAL. For index display, thumbnail image data for 6 frames that is read out of the MMC as a part of the JPEG file is inserted into the index display picture and it is output to the CAM DSP. The thumbnail image is a small-sized image of the original, namely, the original image is reduced into a small size and it is additionally saved in the same JPEG file in recording. Extension of the JPEG-compressed thumbnail image is processed by the software installed in the M32Rx/D CPU, because of its small data amount owing to the small size. Therefore, it is output directly to the CAM DSP without passing the SDRAM line. When a picture is selected from the index display and it is determined to output, the M32Rx/D CPU reads the original image out of the MMC and it outputs the image in full scale to the CAM DSP in the same manner as the general DSC picture playback. To output image data for printing, the M32Rx/D CPU reads out the extended image data remaining in the SDRAM and then saves it in the internal DRAM once. Since the image data read out of the SDRAM is composed of Y, Cr and Cb data for the VGA or XGA size, those color data are respectively converted into R, G and B data for printing. The image data moreover processed to meet the request of the printer, such as image size conversion properly to the print size or for adding the white frame. When the printer completes preparation for printing and it requests data output, the M32Rx/D CPU outputs the image data of 1280 pixels per 1 vertical line through the PRINTER IF to the printer. At that time, the image data is output by the dot sequential system that outputs R, G, B data in unit of 8 bits respectively. The M32Rx/D CPU also carries out data processing for making framed printout, calendar printout, 16-sectioned printout, etc. The printout can be framed by either of the frames built in the FLASH ROM of this model and creative frames prepared by use of a personal computer and saved in the MMC. Calendar pictures and 16-sectioned pictures are internally processed by the M32Rx/D CPU. For transferring data on DSC pictures and print frames to a personal computer by means of the Multimedia Navigator or Picture Navigator, the data is output from the PC terminal through the UART 1 in the form of the RS-232C standard. Image data transfer to a personal computer and image data write on the MMC are carried out by the M32Rx/D CPU. The CAMERA CPU (SYSCON) carries out internal system control so as to meet various kinds of external camera operation, and the SERIAL I/O 0 inside the DSC I/F plays the role of serial communication between the CAMERA CPU and M32Rx/D CPU. The 16-bit bus line of ADR0-15 is used to control internal setting of the DSC I/F.
3-10
3. Signal flow of analog input

AV IN
Y/V C ANALOG VIDEO I/O JCP8019
D/A
DV_IF IN
Y C R-Y B-Y
A/D A/D
YC SEPA
DEC
FRAME TBC
DV_IF OUT
ENC
D/A D/A D/A
MONI/VF
OUT_Y(4) OUT_C(4)
AD(10)
TBCO(12)
TBCI(12)
PS CCD
CDS AGC A/D
DV IN/OUT TAPE REC
Y/C
FMC/EIS
DVIO
DYI(4) DCI(4)
DECK DSP
HSE PBDATA
SRAM
DRAM 8Mb x 2
SRAM
AUTO
SSG
CA_DS_C(8) CA_DS_Y(8) DS_CA_C(8) DS_CA_Y(8)
Fig. 3-3-3 Signal flow of analog input In the analog video input mode, analog signal is input to the ANALOG VIDEO I/O as a composite or Y/C separate signal. First, the analog input signal is converted into digital with the sampling frequency of 13.5 MHz and then separated into two-dimensional Y and C signals. After the Y/C separation, the signals are converted into luminance signal (Y) and color difference signals (R, B) by the decoder, and then they are sent to the FRAME TBC. Since the internal DRAM of the CAP DSP is used as the memory for TBC, the signals are once output from the TBCI (12) and then input to the TBCO (12) from the DRAM. The DV IF OUT in the next stage outputs the signals to the DECK DSP through the TBC DYO (4) and TBC DCO (4) after converting to the 27 MHz data transfer rate. Since the AV terminal of this model is used for both input and output, it is incapable of AV signal output while analog signal is input, but it can output E-E signal to the monitor or viewfinder during analog input.
3-11
4. Signal flow of PC/JLIP and Printer terminals

IC1001
S_DT_OUT
IC1401
SYSCON CPU J604 PC

GND TX RX IC1302 IC1009 IC1301
S_DT_IN
DECK CPU
IC1403
PC_TX PC_RX
IF_TX
SRV_RX SRV_TX PWR_CTL
IF_RX
Q1405
J603 JLIP
EDIT RX TX GND Q1301
IC1301
D1002
JLIP_RX JLIP_TX D1303
IC1303
IC1008
M32_DT_IN
PWR_CTL
IC1303
M32_DT_OUT
IC8002
S_D(16)
RXD
TXD
IC1301
JLIP_L DREQ SRCLK XSDEN
16M SDRAM
S_A(12)
IC8001
32A(19)
IC8004
8M FLASH
PRN_RX
M32_RX
D1303
DSC_IF
32D(16)
J605 PRIN. OUT
SDI M32_TX
IC8003
M32_RX CPU
MMC_SCLK
PRN_TX
Q1301 IC1303
P_ON_L
MMC
Fig. 3-3-4 Signal flow of PC/JLIP and Printer terminals In transferring a digital still image captured from DVC playback to the personal computer with the JLIP Video Capture used together, the image data memorized in the DRAM of deck section is output from the PC terminal through the SRV-TX of the DECK CPU. In transferring a DSC picture stored in the MMC to the personal computer with the Picture Navigator used together, the image data is output from the PC terminal through the TXD of the DSC IF. The communication between personal computer and camcorder is in the UART (Universal Asynchronous Receiver Transmitter). The JLIP terminal is for program editing. The equipment having a JLIP terminal is connected with a JLIP cable (4pin-4pin), and the equipment having a Remote Pause terminal is connected with an Edit cable (2pin-2pin or 4pin-2pin). The printing data is output from the PRINTER terminal through the SDI of the DSC IF in serial with clock SRCLK during the data enable XSDEN is turned to "L". The communication for control to/from the printer is through the M32-TX and M32-RX in the UART.
3-12
MMC_CD
MMC_SO
MMC_CS
MMC_SI
32A(25)
REM_OUT
RXD
TXD
3.3.2 Camera section CPU functions 1. Analog video I/O IC (IC3801: JCP8019) function 1) Analog video I/O IC (IC3801: JCP8019) block diagram
CK135
SDOUT
SDIN SCLK CS
Micro Computer IF
Command Command CK135d Y
VBID Detect
RST TEST
SYSTEM RESET RAM TEST Y C 8 4 4 8
RSTW, WE MYOUT0 - 7 MCOUT0 - 3 MCIN0 - 3 MYIN0 - 7 CK135 RSTR, RE
FRAME TBC
Micro Vision Detect
C Y
Sync Sep
Write TG HD, VD, FIELD 3H Phase Comparison
Read TG HD, VD, FIELD Y Interpolate 3H Thinning RB
Jitter Detect Y Interpolate
RB Interpolate
Command
CK135d
DECODER
Y
DVIF OUT
TG Y RB Y 4 RB C DVC C 4
TBCCTL INH, INV YSI0 - 3 CSI0 - 3
VINY
A/D
1H
2DYCS
AGC
DECODE
DVHS
VINC
A/D
1H
ACC
DLY
2D YC SEPARATOR
CK135d Command CK135d Command CK135d Command CK27d
CK135 9
RB Separator
Sync Add
D/A
IOY
DVIF IN OUTH, OUTH YSO0 - 3

TG Y TG VBID Add Micro Vision Add R ENCODE B C Command CK27 D/A D/A
IOR IOB IOC
DVHS
YNR
D/A
DVC
RB
CSO0 - 3 ENCODER
CK27 Command CK27 CK27d CK135 CK135d CK27 CK135
Command
CLK GEN
CLK27
Fig. 3-3-5 Analog video I/O IC (IC3801: JCP8019) block diagram
3-13
2) Analog video I/O IC (IC3801: JCP8019) pin functions (1/4)

Pin No. 1 20 2 97 119 106 98 107 108 109 111 113 12 51 49 120 121 133 134 135 147 148 149 50 82 52 124 138 152 123 137 122 136 150 56 61 125 139 153 140 VDD NC VSS RVD RHD RODDH RE_1H WE_3H TEST0 TEST1 TEST2 TEST3 VDD NC VSS MYOUT0 MYOUT1 MYOUT2 MYOUT3 MYOUT4 MYOUT5 MYOUT6 MYOUT7 VDD NC VSS MCOUT0 MCOUT1 MCOUT2 MCOUT3 MCOUT4 MCOUT5 MCOUT6 MCOUT7 VDD VSS RSTW RSTR WE RE Out Out Out Out Power supply Ground Reset write output, (To CAMERA DSP: IC4301) Reset read output, (To CAMERA DSP: IC4301) Write enable output, (To CAMERA DSP: IC4301) Read enable output, (To CAMERA DSP: IC4301) Open (Not used) Out TBC memory color difference signal output, (To CAMERA DSP: IC4301) Power supply Not used Ground Out TBC memory luminance signal output, (To CAMERA DSP: IC4301) Pin Name In/Out Out Out Digital power supply Not used Ground OSD vertical reference pulse, (To OSD: IC1002) OSD horizontal reference pulse, (To OSD: IC1003) Open (Not used) Open (Not used) Open (Not used) L: Fixed L: Fixed L: Fixed L: Fixed Power supply Not used Ground Description
Table 3-3-1 Analog video I/O IC (IC3801: JCP8019) pin functions (1/4)
3-14
Analog video I/O IC (IC3801: JCP8019) pin functions (2/4)

Pin No. 80 91 77 155 141 127 156 142 128 143 129 86 99 92 158 132 146 160 131 145 159 130 144 104 93 103 118 115 117 85 102 101 115 53 89 70 39 37 38 126 VDD NC VSS MCIN0 MCIN1 MCIN2 MCIN3 MCIN4 MCIN5 MCIN6 MCIN7 VDD NC VSS SWRCK MYIN0 MYIN1 MYIN2 MYIN3 MYIN4 MYIN5 MYIN6 MYIN7 VDD VSS SDIN SDOUT SCLK CS SCCK1 SCCK2 SCCK3 SCCK4 SCCK5 SCCKSEL SCSEL TCK TMS TDI TDO Test terminal for scan, (L: Fixed) Test terminal for scan, (L: Fixed) Open (Not used) Open (Not used) Open (Not used) Open (Not used) Test terminal for scan, (L: Fixed) In Out In In Power supply Ground Serial data input, (From DECK CPU: IC1401) Serial data output, (To DECK CPU: IC1401) Serial clock input, (From DECK CPU: IC1401) Chip select input, (From DECK CPU: IC1401) In TBC memory luminance signal input, (From CAMERA DSP: IC4301) Power supply Not used Ground Open (Not used) L: Fixed (Not used) In TBC memory color difference signal input, (From CAMERA DSP: IC4301) Pin Name In/Out Power supply Not used Ground Description
3-15

Pin No. 36 105 100 88 94 95 96 78 79 86 87 71 72 151 110 55 62 63 64 40 41 42 54 27 28 154 112 14 13 11 10 9 25 26 24 23 22 8 157 114 VDD VSS YSI0 YSI1 YSI2 YSI3 CSI0 CSI1 CSI2 CSI3 INH INV VDD VSS YSO0 YSO1 YSO2 YSO3 CSO0 CSO1 CSO2 CSO3 OUTH OUTV VDD VSS CLK27 RST MUTEH VDIN TBCCTL HD VD ODDH NOINT CPGDH CLAMP VDD VSS In In In In In Out Out Out Horizontal reference pulse for Monitor/Analog output,(From CAMERA DSP: IC4301) Vertical reference pulse for Monitor/Analog output, (From CAMERA DSP: IC4301) Power supply Ground TBC reference clock (27.0MHz), (From CAMERA DSP: IC4301) System reset (L: reset), (From DECK CPU: IC1401) L: Fixed (Not used) L: Fixed (Not used) TBC memory control, (From CAMERA DSP: IC4301) Open (Not used) Analog input vertical reference signal, (To DECK CPU: IC1401) Open (Not used) Noninterlace detect effect output, (To DECK CPU: IC1401) Open (Not used) ADC clamp pulse output Power supply Ground In Color difference signal input for Monitor/Analog output, (From CAMERA DSP: IC4301) In Luminance signal input for Monitor/Analog output, (From CAMERA DSP: IC4301) Out Out Horizontal reference pulse output for DVC recording, (To DECK DSP: IC3001) Vertical reference pulse output for DVC recording, (To DECD DSP: IC3001) Power supply Ground Out DVC recording digital color difference signal output, (To DECK DSP: IC3001) Out DVC recording digital luminance signal output, (To DECK DSP: IC3001) Pin Name TRST In/Out In Power supply Ground Description Reset pulse input, (From SYSCON CPU: IC1001)
3-16

Pin No. 5 17 31 3 18 34 32 4 21 47 35 48 6 7 33 19 15 29 57 65 44 43 30 16 46 58 59 67 60 45 68 76 90 84 73 83 74 75 66 81 Pin Name AVDD VRTC VRBC AVSS VNC AVSS VINC AVSSG VINY AVSS VNY AVSS VRBY VRTY AVDD AVDDG AVDD AVDD AVDD AVDD COMPYRB RSETYRB VREFOYRB VREFIYRB AVSS IOY AVSS IOR AVSS IOB AVSS AVSS IOC AVSS COMPC RSETC VREFOC VREFIC ADVV ADVV In/Out In/Out In Out Out Out Out In/Out In/Out In Luminance, Cb, Cr signal DAC, (Compensation capacitor) Luminance, Cb, Cr signal DAC, (Full scale adjustment resistor) Open (Not used) Luminance, Cb, Cr signal DAC, (Voltage reference input) Analog ground Analog luminance signal output Analog ground Analog Cr signal output Analog ground Analog Cb signal output Analog ground Analog color signal output Analog ground Color signal DAC (Compensation capacitor) Color signal DAC (Full scale adjustment resistor) Open (Not used) Color signal DAC (Voltage reference input) Analog power supply Analog power supply In/Out In In In In In In In In Power supply Color signal ADC (Top level reference voltage) Color signal ADC (Bottom level reference voltage) Ground Color signal ADC, (comparison reference voltage) Ground Analog color signal input Ground Analog luminance signal input Ground Luminance signal ADC (comparison reference voltage) Analog color signal input Luminance signal ADC (Bottom level reference voltage) Luminance signal ADC (Top level reference voltage) Analog power supply Analog power supply Description
3-17
2. Camera DSP (IC4301: JCY0119) function 1) Camera DSP (IC4301: JCY0119) block diagram
MCLKSEL FCK CLK108IN TRST TDI TMS TCK
CLKGEN TAP_CTL PLL
MCK36A MCK36B OCLK27 OCLK27T OCLK18 OCLK135 OCLK45 TDO TCPOUT
ROM 10
SRAM
AIN0 - 9 ID1 ID2
PREYC 24 12
24
AUTO
AFBEND BEND PWM
12
TNW
BDIN0 - 11 WE RE WRST RRST
12 FMC1 C Y 24 DRAM SRAM FMC2 40 12 8 8
BDOUT0 - 11 CDOUT8 - 15 CDOUT0 - 7 TBCCTL
C Y
4 4 4 4
FCVO0 - 3 FCVO4 - 7 BENCOUT0 - 3 BENCOUT4 - 7 OMT FSET
SRAM
VTRFCIN0 - 3 VTRFCIN4 - 7 CDIN0_C - 7_C CDIN8_Y - 15_Y
C Y 8 DVIO EIS
4 4 8 8
C Y C Y SRAM 4 4 8
HACK CS CE0 CE1 CE2 OE
Y_DAC
Y+SYNC Y_COMP Y_VREF Y_IREF CR CR_COMP CR_VREF CR_IREF CB CB_COMP CB_VREF CB_IREF C C_COMP C_VREF C_IREF ADDATA0 - 15 KASYA_OUT
8 CR_DAC ENC
CLKSEL PTESTDRAM0 PTESTDRAM1 RESET NTDRAM IOCNT
8 CB_DAC
8 C_DAC 10
NRE NWE ALE KASRST
CPU I/F KASYA
K_DAC
VREFL VREFH
ROM
HD HDIN VD VDIN FLD FRVD VS HS INH INV CSYNC SVD SHD SFLD
OUTV OUTH DFLT TVMD STBY
SSG
Fig. 3-3-6 Camera DSP (IC4301: JCY0119) block diagram

3-18
2) Camera DSP (IC4301: JCY0119) pin functions (1/5)

Pin No. 137 186 201 187 15 171 234 233 20 7 176 128 160 209 144 193 177 192 161 224 145 236 178 194 162 223 222 221 136 168 237 235 103 69 86 83 39 53 71 54 55 11 38 24 36 23 68 70 Label GND VDD3 I/F VDD3 I/F SHD SVD SFLD OCLK18 OCLK135 GND VDD4_DRAM2.5 CDIN15_Y_MSB CDIN14 CDIN13 CDIN12 CDIN11 CDIN10 CDIN9 CDIN8 CDIN7 CDIN6 CDIN5 CDIN4 CDIN3 CDIN2 CDIN1 CDIN0_C_LSB GND GND VDD2 GND VDD4_DRAM2.5 GND CDOUT15_C_MSB CDOUT14 CDOUT13 CDOUT12 CDOUT11 CDOUT10 CDOUT9 CDOUT8_C_LSB CDOUT7_Y_MSB CDOUT6 CDOUT5 CDOUT4 CDOUT3 CDOUT2 CDOUT1 CDOUT0_Y_LSB In/Out Out Out Out Out Out Description Ground Power supply, for I/F DSC horizontal drive pulse, (To DSC_IF: IC8001) DSC vertical drive pulse, (To DSC_IF: IC8001) DSC reference pulse, (To DSC_IF: IC8001) Reference clock (18.0MHz), (To DSC_IF: IC8001) Reference clock (13.5MHz), (To DSC_IF: IC8001) Ground Power supply, for DRAM (Luminance: MSB)
In
DSC data input, (From DSC_IF: IC8001)
(Luminance: LSB) (Color: MSB)
In
DSC data input, (From DSC_IF: IC8001)
(Color: LSB) Ground Power supply, for internal circuit Ground Power supply, for DRAM Ground (Color: MSB)
Out
DSC data output, (To DSC_IF: IC8001)
(Color: LSB) (Luminance: MSB)
Out
DSC data output, (To DSC_IF: IC8001)
(Luminance: LSB)
Table 3-3-2 Camera DSP (IC4301) pin functions (1/5)

3-19
Camera DSP (IC4301: JCY0119) pin functions (2/5)

Pin No. 63 101 100 30 88 99 114 219 229 230 232 107 5 16 3 106 78 46 80 43 121 74 91 92 58 41 90 89 13 59 42 61 77 57 76 44 26 60 28 27 25 105 73 14 1 140 158 170 Label IOCNT SCANTEST TDO TRST TCK TMS TDI VDD2 VDD2 VDD2 GND GND GND VDD2 VDD2 DAC_GND PTESTDRAM1 PTESTDRAM0 NTDRAM GND KASYA_OUT AVDD VREFL VREFH AVDD C CB CR Y+SYNC CB_IREF CB_VREF CB_COMP CR_IREF CR_VREF CR_COMP C_IREF C_VREF C_COMP Y_IREF Y_VREF Y_COMP AVSS2 AVDD2 AVSS1 AVDD1 INH INV OUTH In/Out In In In In In In Description Test terminal (Normal: High) Test terminal (Normal: Low) Open (Not used) Reset pulse input for BST, (From SYSCON CPU: IC1001) Clock terminal for BST, (L: Fixed) Mode select terminal for BST, (H: Fixed) Data input terminal for BST, (H: Fixed) Power supply, for internal circuit
Ground
In Out Out Out In
Power supply, for internal circuit Ground Test terminal (Normal: Low) Ground Analog output, (Shutter sound) Power supply, for Analog circuit DAC reference voltage low level input terminal DAC reference voltage high level input terminal Power supply, for Analog circuit Open (Not used) Open (Not used) Open (Not used) Open (Not used) CbDAC reference voltage input terminal Resistor terminal for CbDAC bias current setting Capacitor connection terminal for CbDAC phase compensation CrDAC reference voltage input terminal Resistor terminal for CrDAC bias current setting Capacitor connection terminal for CrDAC phase compensation C reference voltage input terminal Resistor terminal for C bias current setting Capacitor connection terminal for C phase compensation YDAC reference voltage input terminal Resistor terminal for YDAC bias current setting Capacitor connection terminal for YDAC phase compensation Ground, for Analog circuit Power supply, for Analog circuit Ground, for Analog circuit Power supply, for Analog circuit Horizontal reference pulse for DVC recording, (To DECK DSP: IC3001) Vertical reference pulse output for DVC recording, (To DECK DSP: IC3001) Horizontal reference pulse for DVC playback, (From DECK DSP: IC3001)
Table 3-3-2 Camera DSP (IC4301: JCY0119) pin functions (2/5)

3-20

Pin No. 157 123 217 139 129 120 132 135 131 134 130 116 127 143 191 175 207 159 208 174 216 240 239 228 214 118 111 142 220 79 17 62 47 148 152 147 151 115 133 165 167 149 150 164 184 182 183 163 Label OUTV CSYNC OCLK27 OCLK45 FCV00_C_LSB FCV01 FCV02 FCV03_C_MSB FCV04 FCV05 FCV06 FCV07_Y_MSB VTRFCIN0_C_LSB VTRFCIN1 VTRFCIN2 VTRFCIN3_C_MSB VTRFCIN4_Y_LSB VTRFCIN5 VTRFCIN6 VTRFCIN7_Y_MSB GND VDD3 I/F VDD3 I/F VDD3 I/F VDD3 I/F TBCCTL VS HS OCLK27T RRST WRST RE WE BENCOUT0_C_LSB BENCOUT1 BENCOUT2 BENCOUT3_C_MSB BENCOUT4_Y_LSB BENCOUT5 BENCOUT6 BENCOUT7_Y_MSB BDOUT0_LSB BDOUT1 BDOUT2 BDOUT3 BDOUT4 BDOUT5 BDOUT6 In/Out In Out Out Out Description Vertical reference pulse for DVC playback, (From DECK DSP: IC3001) Not used Reference clock (27.0MHz) Reference clock (4.5MHz) (Color: LSB) DVC recording digital color difference signal output, (To DECK DSP: IC3001) (Color: MSB) (Luminance: LSB) Out DVC recording digital luminance signal output, (To DECK DSP: IC3001) (Luminance: MSB) (Color: LSB) In DVC playback digital color difference signal input, (From DECK DSP: IC3001) (Color: MSB) (Luminance: LSB) In DVC playback digital luminance signal input, (From DECK DSP: IC3001) (Luminance: MSB) Ground Power supply, for I/F
Out Out Out In
TBC memory control, (To ANALOG VIDEO I/O: IC3801) TBC-ENC reference pulse, (To ANALOG VIDEO I/O: IC3801) TBC reference clock (27.0MHz), (To ANALOG VIDEO I/O: IC3801) TBC memory control, (From ANALOG VIDEO I/O: IC3801)
Out
(Color: LSB) Color difference signal output for Monitor/Analog output, (To ANALOG VIDEO I/O: IC3801) (Color: MSB) (Luminance: LSB) Luminance signal output for Monitor/Analog output, (To ANALOG VIDEO I/O: IC3801) (Luminance: MSB) (Color: LSB)
Out
Out
TBC memory color difference signal output, (To ANALOG VIDEO I/O: IC3801) (Color: MSB) (Luminance: LSB)
Out
TBC memory luminance signal output, (To ANALOG VIDEO I/O: IC3801)

3-21

Pin No. 199 181 198 197 215 225 180 210 213 227 146 238 195 211 196 226 179 37 22 18 33 85 102 45 9 51 50 52 200 40 56 72 87 104 119 4 12 10 153 169 141 138 94 125 156 155 110 109 Label BDOUT7 BDOUT8 BDOUT9 BDOUT10 BDOUT11_MSB BDIN0_LSB BDIN1 BDIN2 BDIN3 BDIN4 BDIN5 BDIN6 BDIN7 BDIN8 BDIN9 BDIN10 BDIN11_MSB GND GND GND GND QCTEST MINTEST CLKSEL MTEST1 MTEST2 MTEST3 MTEST4 GND VDD3 I/F VDD3 I/F VDD3 I/F VDD3 I/F GND GND CLK108IN VDD3 I/F GND MCK36A MCK36B HD HDIN VD VDIN FLD FRVD ID1 ID2 In/Out Description
Out
TBC memory luminance signal output, (To ANALOG VIDEO I/O: IC3801)
In
(Luminance: MSB) (Color: LSB) TBC memory color difference signal input, (From ANALOG VIDEO I/O: IC3801) (Color: MSB) (Luminance: LSB)
In
TBC memory luminance signal input, (From ANALOG VIDEO I/O: IC3801)
(Luminance: MSB) Ground
In
Test terminal (Normal: High)
In
Test terminal (Normal: Low)
Ground Power supply, for I/F
In Out Out Out Out Out In In
Ground Master clock (108.0MHz), (From X4301) Power supply, for I/F Ground TG reference clock (36.0MHz), (To TG: IC5001) TG horizontal drive reference pulse, (To TG: IC5001) TG horizontal drive trigger reference pulse, (To TG: IC5001) TG vertical drive reference pulse, (To TG: IC5001) TG horizontal drive trigger reference pulse, (To TG: IC5001) Open (Not used) Open (Not used) Picture element array discriminate pulse 1, (From TG: IC5001) Picture element array discriminate pulse 2, (From TG: IC5001)

3-22

Pin No. 185 190 172 188 218 205 204 206 189 231 173 21 67 34 82 66 98 35 81 49 65 19 97 32 48 112 8 64 96 31 2 122 124 108 95 75 93 117 113 84 203 202 126 154 Label FCK AIN9 AIN8 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 ADDDATA15 ADDDATA14 ADDDATA13 ADDDATA12 ADDDATA11 ADDDATA10 ADDDATA9 ADDDATA8 ADDDATA7 ADDDATA6 ADDDATA5 ADDDATA4 ADDDATA3 ADDDATA2 ADDDATA1 ADDDATA0 ALE NEW NRE RESET DFLT TVMD STBY TCPOUT MCLKSEL TNW FSET OMT KASRST AFBEND BEND PWM GND In/Out In Description Reference input clock (36.0MHz), (From TG: IC5001) (MSB)
In
CCD input, (From CDS/AGC/AD: IC4201)
(LSB)
In/Out
Address/Data MPX bus 16bits, (From/To SYSCON CPU: IC1001)
In In In In In In In Out In Out In Out In Out Out Out -
Address latch enable, (From SYSCON CPU: IC1001) Write enable, (From SYSCON CPU: IC1001) Read enable, (From SYSCON CPU: IC1001) Reset signal, (From SYSCON CPU: IC1001) Micro computer setting (H: Default, L: Micro computer), (open: L) Mode select (H: PAL, L: NTSC) Micro computer standby control (H: STBY, L: NORMAL), (open: L) PLL test output, (open) Clock select (H: PLL, L: DLY), (H: Fixed) Micro computer write-in inhibit signal, (open) EIS reset signal, (From SYSCON CPU: IC1001) EIS data read timing, (To SYSCON CPU: IC1001) Shutter sound reset signal, (From SYSCON CPU: IC1001) AF block end signal, (open) Block end signal, (open) Iris control output, (To IC4805) Ground
3-23
3. TG IC (IC5001: MN5290) function 1) TG IC (IC5001: MN5290) pin functions (1/2)

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CS DCLK DATA CKSW VDD_3V GND CLK72IN CK36IN1 CK36IN2 VDD_3V GND CLR DRV1 DRV2 HD VD HDIN VDIN V1A V2A V3A V1B V2B V3B V2C VB CH1 CH2 ID1 ID2 TEST1 TEST2 Label In/Out In In In In In In In In In In In Out Out Out Out Out Out Out Out Out Out Out Out Discription Serial data latch input, (From SYSCON CPU: IC1001) Serial clock input Serial data input Clock input select (L or Open: CK72IN, H: CK36IN1/CK36IN2), (open) Power supply (3V) Ground 72MHz clock input, (From IC5402) 36MHz clock input, (From CAMERA DSP: IC4301) 36MHz clock input, (open) Power supply (3V) Ground Not used Open (Not used) Open (Not used) TG horizontal drive reference pulse, (From CAMERA DSP:IC4301) TG vertical drive reference pulse, (From CAMERA DSP:IC4301) TG horizontal drive trigger reference pulse, (From CAMERA DSP:IC4301) TG vertical drive trigger reference pulse, (From CAMERA DSP:IC4301) V1A transfer pulse output, (To V_DRIVER: IC4101) V2A transfer pulse output, (To V_DRIVER: IC4101) V3A transfer pulse output, (To V_DRIVER: IC4101) V1B transfer pulse output, (To V_DRIVER: IC4101) V2B transfer pulse output, (To V_DRIVER: IC4101) V3B transfer pulse output, (To V_DRIVER: IC4101) V2C transfer pulse output, (To V_DRIVER: IC4101) VB gate pulse output, (To V_DRIVER: IC4101) V1A charge pulse output, (To V_DRIVER: IC4101) V1B charge pulse output, (To V_DRIVER: IC4101) Picture element array discriminate pulse 1, (To CAMERA DSP: IC4301) Picture element array discriminate pulse 2, (To CAMERA DSP: IC4301) Open (Not used) Open (Not used)
Table 3-3-3 TG IC (IC5001: MN5290) pin functions (1/2)
3-24
TG IC (IC5001:MN5290) pin functions (2/2)

Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SUB CLPDM VDD5 H1 GND VDD5 H2 GND VDD5 RM NC VDD_5V NC FCK PNSW/NL/PH SPSEL DS1 DS2 ADCLK CLKO36M CSEL1 CSEL2 GND VDD_3V NC VMD1 VMD2 VMD3 HCLR CPOB PBLK STO Label In/Out Out Out Out Out Out In In Out Out Out In In In Out Out Discription Vertical draw out pulse output, (To V_DRIVER: IC4101) Digital clamp pulse, (To CDS/AGC/AD: IC4201) Power supply (3V), for H and R H1 pulse output, (To CCD) Ground Power supply (3V), for H and R H2 pulse output, (To CCD) Ground Power supply (3V), for H and R R pulse output, (To CCD) Not used Power supply (3V) Not used Open (Not used) TV system select (NTSC: L. PAL: H), (open: L) Serial/Parallel select (L: parallel input, H: Serial input), (H: Fixed) CDS pulse 1 output, (To CDS/AGC/AD: IC4201) CDS pulse 2 output, (To CDS/AGC/AD: IC4201) Digital clock output (36MHz), (To CDS/AGC/AD: IC4201) Open (Not used) Open (Not used) Open (Not used) Ground Power supply (3V) Not used Electrical shutter select input 1, H: Fixed Electrical shutter select input 2, H: Fixed Electrical shutter select input 3, H: Fixed Open (Not used) OB clamp pulse output, (To CDS/AGC/AD: IC4201) Pre-balnking output, (To CDS/AGC/AD: IC4201) Open (Not used)
Table 3-3-3 TG IC (IC5001: MN5290) pin functions (2/2)
3-25
4. DSC IF IC (IC8001: JCY0121-4) function 1) DSC IF IC (IC8001: JCY0121-4) block diagram
IREG
PC_TOP
VC_TOP
KJN2MOD
16
S_DQ0 - 15
C17 - 10 Y17 - 10
8 8 8 IO_TOP LM_TOP SD_TOP
12
S_A0 - 11 S_CLK S_CKE S_CS S_WE S_RAS S_CAS S_LDQM
C27 - 20 Y27 - 20
CLK541 (13.5MHz) CLK13
54MHz
PLL
VCLK
1/2
27MHz 13MHz or 18MHz
(18MHz) CLK18
PLSGEN
AHD1 AVD1 FLD1 AHD2 AVD2 FLD2
16
ADR0 - 15 HWE LWE RE ALE DSTB SRCLK XSDEN SDI
CP_TOP
TRN84
TRN48
MIRIS_CTL
M_IRIS
PR_TOP
M32_RST TEST_M32 MCLR (32MHz) XIN (16MHz) XOUT
CCD IF4 CLKDIV

NRST
DMACSJVC3
SCLK FLICKER INT1 INT2 INT3 CCD_VD_INT DREQ CCD_FLD_INT INT
CLKGEN ETIM UART1 ICU Y S IrDA-SIR10 Y S

RXD1 TXD1
TXD2
UART2
RXD2 BURST D00 - 15
16 26
ITIME1
CSIO0
SI_0 SO_0 SCLK_0 SI_1 SO_1 SCLK_1
A05 - 30 SID BS RW BCL BCH DC HREQ HACK CS CE0 CE1 CE2 OE WE BUSY_M32
ITIME2 TIME BIU CONFIG PORT_J 10

PORT0 - 9
CSIO1
Fig. 3-3-7 DSC IF IC (IC8001: JCY0121-4) block diagram

3-26
2) DSC IF IC (IC8001: JCY0121-4) pin functions (1/6)

Pin No. 10 61 83 221 222 27 88 250 148 93 63 234 198 44 43 241 207 167 21 114 57 94 145 95 146 147 190 226 37 35 25 84 138 60 59 58 115 118 117 116 33 34 189 143 Label VDD IREG/JPEG_END INT1/M32_WKUP PORT0/M32_CS SCLK_0/M32_CLK SI_0/M32_DT_OUT SO_0/M32_DT_IN PORT2/M32_STS BP T_PLL/PLL_TEST M_IRIS/IRIS_C CLK13 CLK18 VSS VDD [2.9V] PR_CLK/SRCLK PR_DEN/SDI PR_DEN/XSDEN PR_DREQ/DREQINT17 VSS VDD [2.9V] LP R0 AGS AGND T1 T2 LD DYB VAA PORT1 PORT8 PORT9 N.C. N.C. N.C. N.C. N.C. N.C. SELCLK54I VDD (PLL) VDD (PLL) TMODE SMODE In/Out In Out In Out In Out In In Out Out Out In Out Out In Power supply (2.9V) Not used M32R/D wake-up, L: Power on, H: After stable High Chip select, (To SYSCON CPU: IC1001) Serial clock input, (From SYSCON CPU: IC1001) Serial data output, (To SYSCON CPU: IC1001) Serial data input, (From SYSCON CPU: IC1001) Micro computer status. (L: sleep), (To SYSCON CPU: IC1001) L: Fixed L: Fixed Open (Not used) 13MHz clock (From CAMERA DSP IC4301) 18MHz clock (From CAMERA DSP IC4301) Ground Power supply (2.9V) Printer clock Printer data Printer enable Printer data request Ground Power supply (2.9V) 54M PLL Ground L: Fixed L: Fixed Open (Not used) H: Fixed Power supply Open (Not used) Open (Not used) Open (Not used) Not used Not used Not used Not used Not used Not used L: Fixed Power supply Power supply H: Fixed H: Fixed Description
Table 3-3-4 DSC IF IC (IC8001: JCY0121-4) pin functions (1/6)

3-27
DSC IF IC (IC8001: JCY0121-4) pin functions (2/6)

Pin No. 168 54 120 1 163 92 32 91 31 144 225 238 90 188 253 142 9 223 224 30 237 265 264 263 226 252 20 81 132 134 80 133 19 18 17 79 78 16 77 15 180 217 206 186 USEL0 USEL1 CS_CAM RWSEL DSTB BCLK ACLK TRST TMS TESTSL54 TESYCK54 CLK54I TDI TCK MTST TEST_M32 BUSY_M32R UART2_RX/RXD2 UART2_TX/TXD2 TD0 CLK27 N.C. N.C. N.C. VSS VDD [2.9V] D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 BURST (L) SID (L) In/Out In Burst cycle: L, (From/To M32_RX CPU: IC8003) Decision signal of user space and I/O space (L: User / H: I/O) In/Out M32R/D data I/O, (From/To M32_RX CPU: IC8003) Label In/Out In Out H: Fixed L: Fixed L: Fixed L: Fixed L: Fixed L: Fixed L: Fixed L: Fixed L: Fixed L: Fixed H: Fixed H: Fixed L: Fixed L: Fixed L: Fixed L: Fixed L: Fixed PC/JLIP communication RX PC/JLIP communication TX Open (Not used) Open (Not used) Not used Not used Not used Ground Power supply (2.9V) Description

3-28

Pin No. 76 29 86 248 23 105 178 131 247 14 137 22 181 26 244 72 127 71 126 7 172 211 242 6 125 171 124 69 5 170 123 4 68 122 67 66 121 3 2 65 208 209 62 194 SCLK XOUT M32_RST (L) INT (L) OE (L) WE (L) CE2 (L) CE1 (L) CE0 (L) CS (L) HACK (L) HREQ (L) DC (L) RW (L) BS (L) BCL / BC1 (L) BCH / BC0 (L) BC2 (L) / A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 VSS Ground 32_A05 - 32_A30 M32R/D CPU address output, (To M32_RX CPU: IC8003, 8M FLASH: IC8004) Label In/Out In Out Out Out Out Out Out Out In Out In/Out In/Out In In/Out In/Out Description M32R/D clock input (1/4 frequency divided of M32R/D clock) M32R/D clock output (1/4 frequency divided of M32R/D clock) M32R/D reset (Used for carriage return of stand-by mode) External interrupt demand (interrupt at stop of M32R/D etc.,) Output enable, (To Flash RAM: IC8004) Write enable, (To Flash RAM: IC8004) Not used Not used Chip enable, (To Flash RAM: IC8004) M32R/D chip select, (L: chip select to M32R/D) M32R/D Bus disengagement notice at conversion for hold status M32R/D hold conversion command (Low: Hold of M32R/D) M32R/D data complete (L: data bus cycle complete command) M32R/D DRAM read/write decision (L: Write / H: Read) M32R/D bus cycle complete command input (bus start) Effect data transfer position: LSB side (D8-D15) Low active M32R/D Effect data transfer position: MSB side (D0-D7) Low active M32R/D
Out

3-29

Pin No. 192 36 96 184 183 141 28 87 139 187 251 85 24 185 140 239 240 89 135 179 218 164 165 166 205 204 210 169 119 111 258 196 195 102 231 257 230 42 101 152 229 41 256 100 VDD [2.9V] VSS VSS MMC_CD/PORT5 MMC_CD/INT3 MMC_DATA/SI_1 MMC_CMD/SO_1 MMC_CLK/SCLK_1 MMC_CS/PORT4 TXD1/Ir_TXD RXD1/Ir_RXD Ir_DA_ENA/PORT3 VDD [2.9V] VSS MCLR/RESET(L) N.C. TESTJPG XIN VDD [2.9V] VSS VSS N.C. N.C. N.C. N.C. N.C. VDD [2.9V] VDD [2.9V] VSS VSS S_DQ15 S_DQ14 S_DQ13 S_DQ12 S_DQ11 S_DQ10 S_DQ9 S_DQ8 S_DQ7 S_DQ6 S_DQ5 S_DQ4 S_DQ3 S_DQ2 In/Out Data I/O (16bit), (From/To 16M SDRAM: IC8002) Label In/Out In In In Out Out Out Out In Out Out In Power supply (2.9V) Ground Ground MMC card detect input MMC data input MMC data output MMC clock MMC chip select Printer communication TX (To Printer terminal) Printer communication RX (From Printer terminal) Not used Power supply (2.9V) Ground Reset pulse, (To 8M FLASH: IC8004) Not used L: Fixed 32MHz clock input (From X8001) Power supply (2.9V) Ground Ground Not used Not used Not used Not used Not used Power supply (2.9V) Power supply (2.9V) Ground Ground Description

3-30

Pin No. 151 193 40 255 99 150 39 227 98 254 38 149 191 97 104 232 45 259 197 103 153 106 48 156 47 199 155 233 46 74 214 215 245 175 73 174 213 158 109 108 157 51 50 49 S_DQ1 S_DQ0 S_A11 S_A10 S_A9 S_A8 S_A7 S_A6 S_A5 S_A4 S_A3 S_A2 S_A1 S_A0 S_WE S_RAS L.DQM S_CAS S_CS S_CLK S_CKE Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 C10 C11 C12 C13 C14 C15 C16 C17 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Out DSC data output (To CAMERA DSP: IC4301) In DSC data input (From CAMERA DSP: IC4301) Out Out Out Out Out Out Out Write enable, (To 16M SDRAM: IC8002) Row address strobe, (To 16M SDRAM: IC8002) Data I/O mask, (To 16M SDRAM: IC8002) Column address strobe, (To 16M SDRAM: IC8002) Chip select,(To 16M SDRAM: IC8002) Clock, (To 16M SDRAM: IC8002) Clock enable,(To 16M SDRAM: IC8002) Out Address output (12bit), (To 16M SDRAM: IC8002) Label In/Out In/Out Description Data I/O (16bit), (From/To 16M SDRAM: IC8002)
In
DSC data input (From CAMERA DSP: IC4301)

3-31

Pin No. 107 177 129 12 75 246 176 128 11 243 212 8 173 82 136 220 249 219 13 218 182 56 236 262 203 113 162 55 202 261 112 54 161 201 160 53 260 200 159 52 110 154 70 130 Y27 C20 C21 C22 C23 C24 C25 C26 C27 AHD1 AHD2 AVD1 AVD2 FLD1 FLD2 PORT6/FLD1 PORT7/FLD2 VDDSC/INT2 CCD_VD_IN CCD_FLD_IN FLICKER RE/CRE HWE/CHWE LWE/CLWE ALE/CALE ADR15 ADR14 ADR13 ADR12 ADR11 ADR10 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 VSS VSS VSS Ground In/Out Address/Data MPX bus 16bits, (From/To SYSCON CPU: IC1001) In In DSC horizontal reference pulse input, (From CAMERA DSP: IC4301) DSC vertical reference pulse input, (From CAMERA DSP: IC4301) Out DSC data output (To CAMERA DSP: IC4301) Label In/Out Out DSC data output Description (To CAMERA DSP: IC4301)
In
DSC frame reference pulse input (vertical pulse), (From CAMERA DSP IC4301) Vertical synchronization (for DSC), (From CAMERA DSP: IC4301) Open (Not used) Open (Not used) Open (Not used) Read-out enable,(To SYSCON CPU: IC1001) Write-in enable,(From SYSCON CPU: IC1001) Write-in enable (Lower bit), (From SYSCON CPU: IC1001) Address latch enable,(From SYSCON CPU: IC1001)
In Out In In In

3-32
5. M32 RX CPU (IC8003: M3231D4WG) function 1) M32 RX CPU (IC8003: M3231D4WG) pin functions (1/3)
Pin No. 162 133 148 163 134 149 164 135 165 120 151 166 121 137 167 122 136 125 155 123 124 169 154 139 170 140 126 171 156 153 168 142 173 158 143 175 174 160 159 144 145 128 129 130 113 114 115 112 Label VCC (2.5V) D23 D22 D21 D20 VSS VCCX (3.0V) D19 D18 D17 D16 VSS VCC (2.5V) D15 D14 D13 D12 VSS VCCX (3.0V) D11 D10 D09 D08 VSS VCC (2.5V) D07 D06 D05 D04 VSS VCCX (3.0V) D03 D02 D01 D00 VSS VSS ST PP1 PP0 BS (L) VSS VCCX (3.0V) BURST (L) RDY (L) DC (L) EMSZ VSS In/Out Power supply (2.5V) Open (Not used) Description
Ground Power supply (3.0V) Open (Not used)
Ground Power supply (2.5V)
In/Out
16bit data bus, (From/To DSC_IF: IC8001, 8M_FLASH: IC8004)
In/Out
Ground Power supply (3.0V) 16bit data bus, (From/To DSC_IF: IC8001, 8M_FLASH: IC8004)
In/Out
In/Out
Ground
Out In/Out In In/Out In/Out -
Open (Not used) Bus start (bus cycle start, BS signal: L), (To DSC_IF: IC8001) Ground Power supply (3.0V) Burst (burst cycle, BURST signal: L), (From/To DSC_IF: IC8001) Bus ready (L: Fixed) Data complete (From/To DSC_IF: IC8001) External master bus (L: data bus width 16bit, H: data bus width 32bit), (L: Fixed) Ground
Table 3-3-5 M32 RX CPU (IC8003: M3231D4WG) pin functions (1/3)

3-33
M32 RX CPU (IC8003: M3231D4WG) pin functions (2/3)

Pin No. 106 104 98 96 88 91 83 89 80 157 82 81 75 73 67 56 59 14 29 44 43 28 57 58 13 42 27 12 41 26 40 25 10 55 39 22 54 23 53 52 7 21 37 6 36 50 5 20 Label VCC (2.5V) HREQ (L) HACK (L) CS (L) R/W (L) VSS VCCX (3.0V) INT (L) SBI (L) VCCX TCK TRST (L) VCCX PLLCNT2 PLLCNT1 VCCX CLKIN VCC (2.5V) VSS RST (L) WKUP (L) STBY (L) VSS VCC (2.5V) PLL VCC BC3 BC2 (L)/A30 BC1 (L) BC0 (L) PLL VSS VCCX (3.0V) A29 A28 A27 A26 VSS VCC A25 A24 A23 A22 VSS VCCX (3.0V) A21 A20 A19 A18 VSS In/Out In Out In In/Out In In In In In In In In In/Out In/Out In/Out Description Power supply (2.5V) Hold, (From DSC_IF: IC8001) Hold acknowledge, (To DSC_IF: IC8001) Chip select, (From DSC_IF: IC8001) Read/Write decision signal (H: read, L: write), (From/To DSC_IF: IC8001) Ground Power supply (3.0V) External interrupt request input, (From DSC_IF: IC8001) System break interrupt input (H: Fixed) Power supply Test clock Test reset Power supply PLL control (PLLCNT1="H", PLLCNT2="L": 5 times) Power supply Clock input, (From DSC_IF: IC8001) Power supply (2.5V) Ground Reset input, (From DSC_IF: IC8001) Wakeup signal input Open (Not used) Ground Power supply (2.5V) Power supply L: Fixed 16bit address bus, (From/To DSC_IF: IC8001, 4M_FLASH: IC8004) Byte control, (From/To DSC_IF: IC8001) Ground Power supply (3.0V) 16bit address bus, (From/To DSC_IF: IC8001, 4M_FLASH: IC8004)
In/Out
Ground Power supply 16bit address bus, (From/To DSC_IF: IC8001, 4M_FLASH: IC8004)
In/Out
Ground Power supply (3.0V) 16bit address bus, (From/To DSC_IF: IC8001, 4M_FLASH: IC8004)
Ground

3-34
M32 RX CPU (IC8003: M3231D4WG) pin functions (3/3)

Pin No. 35 49 4 34 48 3 18 33 2 17 32 15 1 16 31 30 47 46 45 61 60 70 69 71 78 77 76 86 84 87 100 92 93 94 103 95 101 102 111 108 109 110 116 117 118 131 132 147 Label VCC (2.5V) A17 A16 A15 A14 VSS VCCX (3.0V) A13 A12 A11 A10 VSS VSS DRAM 3.3V A09 A08 A07 A06 VSS VCCX (3.0V) A05 SID M/S (L) VCC (2.5V) VSS VSS VCC (2.5V) ROMSZ TDI TMS VSS DRAM 3.3V TDO VCCX VCCX VSS VCC (2.5V) D31 D30 D29 D28 VSS VCCX (3.0V) D27 D26 D25 D24 VCC (2.5V) In/Out In/Out Power supply (2.5V) 16bit address bus, (From/To DSC_IF: IC8001, 4M_FLASH: IC8004) Description
In/Out
In/Out
In/Out Out In In In In Out -
Ground Power supply (3.0V) 16bit address bus, (From/To DSC_IF: IC8001, 4M_FLASH: IC8004) Decision signal of user space and I/O space, (To DSC_IF: IC8001) Master slave setting input (H: Bus master, L: Bus slave), (H: Fixed) Power supply (2.5V) Ground Power supply (2.5V) ROM bus width set (L: Data bus width 16bit, H: Data bus width 32bit), (L: Fixed) Test data input Test mode select Ground Power supply (3.3V) Test data output Power supply Ground Power supply (2.5V) Open (Not used)
Ground Power supply (3.0V) Open (Not used)
Power supply (2.5V)

3-35
3.4 EXPLANATION OF DECK CIRCUIT

3.4.1 PLL operation 1. Explanation of PLL operation
X4301
IC4301 CAMERA DSP

CLK27 VCO405I
108MHz
81MHz A04 MAIN_VCO ADJ X3301
IC3001 FRP GEN

FRP
DVDSP
IC3101 1394 PHY

PHYCLK
27MHz
JIG CONN MAIN_VCO
81MHz
1394 LINK
FRP
IC3301
DVANA
REF
VCXO
PWM405 VCO405
FRP GEN
PC
VCO CLK OSC

X3001 MAIN CLK 40.5MHz REC CLK 41.85MHz Not used
Serial I/F
REF 12.288MHz 11.289MHz 8.192MHz PWMAUD
ANA_DATA From DECK_CPU
24.576MHz
PC
VCO
VCOAUD
DOMCK
A03 FS_PLLADJ VCOAUD
FS_PLL JIG CONN
ANA_PD
Fig. 3-4-1 PLL operation block diagram The main clock for the deck section operates at a frequency of 40.5 MHz, which is equivalent to 18 MHz for the previous models. Since two memories of the SHUFFLE memory and the ECC memory that are needed for the previous models are integrated into one DRAM, the clock frequency is raised in order to increase the processing speed. For setting the clock duty ratio exactly at 50 %, 40.5 MHz clock is produced from the 81 MHz clock. The PLL circuit of the main clock system produces 81 MHz clock by the X'TAL X3301 and VCXO, and sends the 81 MHz clock to the IC3001 DV DSP. Using the frame pulse produced from the 81 MHz pulse as the comparison signal of the PLL, the frame pulse (29.97 Hz in NTSC or 25 Hz in PAL) is produced from the 27 MHz pulse output from the camera and this frame pulse is used as the reference signal of the PLL in the general recording and playback modes. However, the frame pulse produced by decoding the input DV signal is used as the PLL reference signal for phase comparison in the 1394 input mode. A phase error is output as the PWM405 signal, which passes through the filter circuit and controls the VCXO. For PLL adjustment, the filter output voltage is set nearly at the center (1.2 V 0.1 V) of the tolerance in the condition that the PLL is locked. There are three audio sampling frequencies (32 kHz, 44.1 kHz and 48 kHz) provided, therefore, master clocks (8.192 MHz, 11.289 MHz and 12.288 MHz) are produced by t e VCO in the IC3301 for the h respective sampling frequencies, and those master clocks are output to the IC3001 DV DSP. For adjusting the FS-PLL, the respective frequencies are adjusted in the free-run status.
3-36
2. Explanation of PB equalizer and ATF operations

IC3301
PB_ENV
DV_ANA
PBO
IC3201
AINAD1
DV_EQ AUTO EQ
PB_DATA
LPF
AGC
AD1
1+D
VITERBI
PB_CLK
PLLE + REFV PLLO
VOA VOB
2CH DAC
PLL DET PWM
VCO
VCOC CLKO
IC3202
CLK 41.85MHz ADDT00:15
DTR SW CTL1
PB:H
CPU I/F
DISCR
SERVO CPU
DISCRI
41.85MHz
RECCTL REC:H
JIG CONN PB_VCO
BPF
GCA
ATFO
AINAD2
AD2
ATF
A02 ATF_GAIN
RECCLK
Fig. 3-4-2 PB equalizer and ATF operation block diagram In the playback mode the PB ENV signal output from the PB amp. is branched into two in the IC3301 DV ANA; one is the signal for playback data and the other is that for ATF. The PBO signal output through the LPF and AGC is sent to the IC3201 DV EQ as that for playback data, while the ATFO signal output through the BPF and GCA is also sent to the IC3201 DV EQ as that for ATF. In the IC3201 DV EQ, the playback signal undergoes digitalization (AD1), waveform equalization (AUTO EQ), SI-NRZI channel decoding (1+D), and Viterbi-decoding (VITERBI). The resultant signal processed as mentioned above is output from the IC3201 as the playback data signal. At the same time, the PLL circuit constructed in this circuitry controls phase correction in order to generate the PB clock synchronizing with the playback signal. The 41.85 MHz signal oscillated by the internal VCO of the IC3301 is output as the PB clock (PB CLK). Since the internal switch of the IC3301 varies the capacitance of the capacitor, the switch is turned off to minimize the capacitance of the capacitor when the level of the REC CTL is H, namely, in the Audio-Dubbing mode. As a result, the response time is shortened in that mode. The discriminator (DISCRI) compares the 41.85 MHz signal oscillated from the VCO with the other 41.85 MHz signal produced from the 81 MHz of the main clock in order to detect a difference between the two frequencies. In the general playback mode, the discriminator outputs a Low level signal when the frequency difference is +1 % or more or a High level signal when the difference is -1 % or more. In the other modes, a Low level signal is output when the frequency difference is +3 % or more or a High level signal is output when the difference is -3 % or more. When the frequency difference is within 1 % in the general playback mode or within 3 % in the other modes, the output signal has a high impedance. Therefore, a frequency difference, if there is, is roughly corrected. Regarding the signal for the ATF, the frequency component of the ATF pilot signal is extracted from the playback signal by the BPF and the ATF gain is adjusted by the GCA. Then, the ATF circuit in the IC3201 DV EQ detects a tracking difference using the pilot signals of F0, F1 and F2, and data on the detection result is transmitted to the servo CPU.
3-37
3.4.2 Deck section CPU functions 1. SYSCON CPU (IC1001: MN1021617JA) function 1) SYSCON CPU (IC1001: MN1021617JA) pin functions (1/4)
Pin No. 15 29 2 42 16 56 39 43 4 57 5 31 18 44 6 58 19 45 33 46 20 7 59 8 34 21 47 22 48 10 35 51 3 30 32 9 F/Z_CS VDD OSC_I OSC_O VSS VDD VSS VSS VSS Ground Label M32_STS BATT_SW BUS 0 BUS 1 BUS 2 BUS 3 VDD VSS BUS 4 BUS 5 BUS 6 BUS 7 BUS 8 BUS 9 BUS 10 PWR_CTL SRV_RDY BUS 11 BUS 12 BUS 13 BUS 14 BUS 15 MODE 0 MODE 1 MODE 2 SRV_CS IN IN IN OUT OUT In Out L: Fixed (0V) L: Fixed (0V) H: Fixed (3V : VDD) Servo reset L: Fixed (Not used) Focus/Zoom MDA (IC4851) chip select Power supply 24MHz OSC input 24MHz OSC output Ground Power supply In/Out Address/Data MPX bus 16bits, (From/To CAMERA DSP: IC4301) Out IN Regulator section power supply control Servo ready signal input, (From DECK CPU: IC1401) In/Out Address/Data MPX bus 16bits, (From/To CAMERA DSP: IC4301) Power supply Ground In/Out Address/Data MPX bus 16bits, (From/To CAMERA DSP: IC4301) In/Out In In Description Micro computer status input, L: Sleep, (From DSC_IF: IC8001) Battery/DC coupler discrimination (L: Battery)
Table 3-4-1 SYSCON CPU (IC1001: MN1021617JA) pin functions (1/4)

3-38
SYSCON CPU (IC1001: MN1021617JA) pin functions (2/4)

Pin No. 17 37 36 38 49 50 60 63 62 64 73 77 75 76 74 90 85 89 87 101 100 102 99 103 114 116 113 115 128 127 129 140 141 23 88 61 S_DT_IN S_DT_OUT S_CLK AFZ_DATA AFZ_CLK RXD TXD RESERVE4 VSS AVDD VDD RTC_INT M32_CS SCR_UD SCR_LR ODD_EVN EEPROM_CS VDD TIMER_OUT STROBE_CHG SDRAM_PWR DSC_PS VDD FLD_FMC RST GATEPULS STO_OFF JLIP_INT VD OMT VDIN Label In/Out In Out Out In In In In In In In Out Out In Out Out Out Out Out In Out Out Out Out In Out Power supply L: Fixed (0V) Field reference pulse, (From DSP: IC4301) System reset Strobe emission control (L to H: emission) Strobe emission stop signal JLIP interrupt Vertical reference pulse, (From CAMERA DSP: IC4301) EIS data read timing, (From CAMERA DSP: IC4301) TG V rate reference pulse, (From CAMERA DSP: IC4301) L: Fixed (Not used) L: Fixed (Not used) Clock 1 second interrupt Chip select, (From DSC_IF: IC8001) Monitor Up/Down control output, (To DECK CPU: IC1401) Monitor Left/Right control output, (To DECK CPU: IC1402) Field discrimination signal at PB mode, (From DECK CPU: IC1401) Chip select, (To EEPROM: IC1003) Power supply Not used Strobe charge control (H: Charge inhibition) Not used ( To DSC_IF: IC8001) Reset signal output, ( To DSC_IF: IC8001, 8M_FLASH: IC8004) L: Fixed (Not used) Serial data input, (From MSD, EEPROM, RTC) Serial data output, (To MSD, TG, CDS/AGC, EEPROM, DAC, RTC) Serial clock output L: Fixed Serial data output, (To AUDIO FZ_MDA: IC3401) Serial data clock, (To AUDIO FZ_MDA: IC3401) RS232C data input RS232C data output L: Fixed Ground Power supply Power supply Description
Table 3-4-1 SYSCON CPU (IC1001: MN1021617JA) pin functions (2/4)
3-39

Pin No. 165 136 125 152 153 139 155 126 142 112 151 138 154 111 163 137 150 124 152 110 149 123 135 122 148 109 159 160 134 147 121 146 133 155 132 145 TG_CS CDS_CS LEDCTL_R LEDCTL_B VRefH AVDD SENSPULS SRV_RST STO_OPEN RTC_CS DAC_CS CLWE CHWE CRE VDD AVSS AVSS VSS M32_DT_IN M32_DT_OUT M32_DT_CLK VDD VSS AVSS VRefL BATT_CHK HALL_AD Z_PTR_AD F_PTR_AD STRB_AD OP_SEPMO In Out In In In In In In In Out Out Out Out Out Out In Out Out Out Out In Ground Serial data input, (From DSC_IF: IC8001) Serial data output, (To DSC_IF: IC8001) Serial clock input, (From DSC_IF: IC8001) Power supply Ground Ground ADC ground Battery DC input Iris motor hall generator (A/D input) Zoom position sensor (A/D input) Focus position sensor (A/D input) Strobe charge status (A/D input ) OP temperature detect input L: Fixed (Not used) L: Fixed (Not used) TG chip select, (To TG: IC5001) CDS chip select, (To CDS/AGC/AD: IC4201) L: Fixed (Not used) L: Fixed (Not used) Mode illumination control RED Mode illumination control BLUE ADC reference voltage (REG3V) Power supply Strobe emission quantity detect sensor ON/OFF control Servo reset, (To DECK CPU: IC1401, IC1002) Open (Not used) Strobe open/close detect switch input Chip select, (To RTC: IC1004) Chip select, (To AUDIO FZ_MDA: IC3401) Write enable, (To DSC_IF: IC8001) Write enable, (To CAMERA DSP: IC4301, DSC_IF: IC8001) Read enable, (To CAMERA DSP: IC4301, DSC_IF: IC8001) Label In/Out Power supply Ground Description
Table 3-4-1 SYSCON CPU (IC1001:MN1021617JA) pin functions (3/4)
3-40

Pin No. 107 54 161 119 131 120 130 108 118 106 105 95 104 93 91 94 92 82 78 81 79 68 67 69 66 80 65 55 52 40 53 41 26 28 27 117 S_MUTE A_P_CTL L_MUTE MMC_L DSC_BFLS A_MUTE VDD Label VDD (VPP) VDD (VPP) AVDD CALE VDD VSS DIAL_DSCPB DIAL_MANU DIAL_AUTO DIAL_OFF DIAL_PLAY EJECT_SW CAS_SW MONITOR_SW VF_SW NR_DET DSP_RST_1 DSP_RST_2 DSP_RST_3 F/Z_RST CDS_RST CDS_STBY V_MUTE JLIP_ENABLE VDD (VPP) IRIS_O/C M32_WKUP Out Out Out Out Out Out Out Out Out Out In Out Driver reset, (FOCUS/ZOOM: IC4851) Reset signal out put, (To CDS/AGC/AD: IC4201) Standby signal output, (To CDS/AGC/AD: IC4201) Video mute Not used Power supply Iris Open/Close control DSC wakeup signal output, L: Power on, after stable to High, (To DSP_IF; IC8001) L: Fixed Shutter sound mute Not used Audio mute, (To AUDIO: IC2201) MMC detect L: Fixed Audio mute, (To AUDIO: IC2201) Power supply Out Reset signal out put, ( To DSC_IF: IC4301, DECK DSP:IC3001, DVEQ: IC3201, ANALOG VIDEO I/O: IC3801) In/Out Out In In In In In In In In In In Power supply Power supply Address latch enable, (To CAMERA DSP: IC4301, DSC_IF: IC8001) Power supply Ground Dial DSC PLAY mode L: Fixed Power dial MANUAL position detect Power dial AUTO position detect Power dial OFF position detect Power dial PLAY position detect Eject switch detect Cassette switch detect Monitor switch detect VF switch detect Noise reduction detect, (From AUDIO: IC2201) Description
Table 3-4-1 SYSCON CPU (IC1001:MN1021617JA) pin functions (4/4)
3-41
2. Deck CPU (IC1401: MN1030F04K) function 1) Deck CPU (IC1401: MN1030F04K) pin functions (1/5)
Pin No. 1 27 14 28 2 29 3 61 15 45 16 46 4 30 31 52 5 47 17 63 49 32 18 79 6 48 64 7 65 19 33 20 82 50 66 8 67 51 34 9 35 21 52 10 SCR_UD SCR_LR ODD_EVEN VDDB ADM15 ADM14 ADM13 ADM12 ADM11 ADM10 ADM9 ADM8 VSS ADM7 ADM6 ADM5 ADM4 ADM3 In/Out Ground In/Out Data (16 bits) /address (15 bits) (From/To DECK DSP: IC3001 (EDA, DIF BLOCK)) VSS In In Out Monitor UP/DOWN control input, (From SYSCON: IC1001) Monitor Left/Right control input, (From SYSCON: IC1001) Field discrimination signal at PB mode, (To SYSCON: IC1001) Power supply (3V) L: Fixed (Not used) Label CAP_BRK LD_ON TBC_RST EXT_IN_L VSS NOINT PHY_PD PHY_RST PHY_CNA S_OPEN S_CLOSE OPEN_SW CLOSE_SW VDDH V_MUTE EEPROM_CS RWSEL AS Ground In/Out Out Out Out Out In Out Out In Out Out In In In Out Out Out Capstan motor brake control Loading motor ON/OFF control System reset output (L: reset), (To ANALOG VIDEO I/O: IC3801) External input select output, (To IC3851, IC1402, Q3706) Ground Noninterlace detect effect input, (From ANALOG VIDEO I/O: IC3801) IEEE1394 power down, (To 1394PHY: IC3101) IEEE1394 power reset (L: active), (To 1394PHY: IC3101) IEEE1394 cable connection detect, (From 1394PHY: IC3101) Lens shutter open (H: In action), (SHUTTER MDA: IC1201) Lens shutter close (H: In action), (SHUTTER MDA: IC1201) Lens shutter open switch, (From LENS SHUTTER UNIT) Lens shutter close switch, (From LENS SHUTTER UNIT) Power supply (3V) Video mute input, (From SYSCON CPU: IC1001) Chip select, (To EEPROM: IC1003) Bus read/write select signal Bus address strobe signal L: Fixed (Not used) Description
Data (16 bits) /address (15 bits) (From/To DECK DSP: IC3001 (EDA, DIF BLOCK))
Table 3-4-2 Deck CPU (IC1401: MN1030F04K) pin functions (1/5)

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Deck CPU (IC1401: MN1030F04K) pin functions (2/5)

Pin No. 36 22 23 11 37 24 38 12 40 53 56 54 55 70 71 69 68 72 88 86 87 85 104 102 103 101 100 84 99 83 120 118 119 116 117 134 135 133 136 132 148 ADM2 ADM1 ADM0 VDDB DK (L) RE (L) WE1 (L) WE0 (L) PVDD PVSS MMOD1 MMOD0 RESET (L) FRQS VSS EXMOD1 EXMOD0 OSCI OSC0 VDDH SYSCLK EQ_CS DV_CS CS1 (L) CS0 (L) VDD V_PB_L D_GAIN DV_RST EQ_RST ANA_PD VSS HID3 REC_I PBH REEL_LED REC_SAFE VDDH CAM2 CAM1 CAM0 Label In/Out In/Out Out Out Out In In Out Out Out Out Out Out Out Out Out Out Out In Out Out Out Description Data (16 bits) /address (15 bits) (From/To DECK DSP: IC3001 (EDA, DIF BLOCK)) Power supply (3V) CPU standby signal (L: Deck mode) , (To DECK DSP: IC3001) Bus memory read enable signal, (To DECK DSP: IC3001, DVEQ: IC3201) Open Bus memory write enable signal, (To DECK DSP: IC3001, DVEQ: IC3201) Power supply (3V) Ground Bus memory mode setup signal Reset (L), (From SYSCON CPU: IC1001) Open Power supply (3V) H: Fixed L: Fixed OSC 27MHz Open Power supply (3V) Open Chip select output, (To DVEQ: IC3201) Chip select output, (To DECK DSP: IC3001) Open Power supply (3V) Power ON timing control for tape recording circuit (H: REC and REC pause) Drum servo gain control Reset pulse output, (To DECK DSP:IC3001) Reset pulse output, (To DVEQ: IC3201) Not used Ground Head switch 3, (To PRE/REC: IC3501) REC insert switch, (To PRE/REC: IC3501) PB: H control, (To PRE/REC: IC3501, DVEQ: IC3201, IC3202) Reel sensor LED control REC safety switch Power supply (3V) Rotary encoder input 2 Rotary encoder input 1 Rotary encoder input 3
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Pin No. 149 152 150 151 147 164 166 167 163 168 165 183 181 184 200 182 199 198 216 214 239 213 240 197 227 212 226 196 238 180 225 195 237 179 211 210 236 194 224 209 235 178 IR_DET ZOOM_SW KEY_D KEY_C KEY_B KEY_A S_DC_IN BCID3 BCID2 BCID1 DEW_SENS E_SENS S_SENS VREFH AVDD ADTRG NMI VSS DRUM_PG DRUM_FG MSELECT VDD TRG_OUT TALLY AGC_RST S_DET AV_DET HP_DET ADC_PWD1 ADC_PWD0 VSS ADC_DEM1 ADC_DEM0 In In In Out Out Out In In In Out Out Out Out Drum PG, (From MDA: IC1601) Drum FG, (From MDA: IC1601) Deck CPU chip select input (From SYSCON CPU: IC1001) Power supply (3V) Remote signal output Tally LED ON/OFF control Reset pulse output, (To VIDEO OUTPUT DRIVER: IC3701) S terminal connection detect input AV plug detect input HP plug detect input D/A power control (Power down: L), (to AUDIO AD/DA: IC2101) A/D power control (Power down: L), (to AUDIO AD/DA: IC2101) Ground Sampling frequency select ADC_DEM0/ADC_DEM1, (to AUDIO AD/DA: IC2101) :Frequency (L/L: 44.1k, L/H:48k, H/L: OFF, H/H: 32k) L: Fixed (Not used) In In In In Cassette tape ID board information Dew sensor detect End sensor detect Start sensor detect AVSS In In In In In In In L: Fixed White balance IR DC component detect input Zoom switch input Shooting mode dial switch input (XGA, VGA, DUAL, VIDEO, PS) Snapshot button switch input (SNAP SHOT, TRIGGER, MENU SET) Snapshot mode switch input (SLOW, SNAP MODE, PRINT FRAME, PRINT) Deck operation switch input (PLAY/PAUSE, FF, REW, STOP) Voltage detect from S2 terminal Label In/Out Ground Description
H: Fixed (3V)
Ground
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Pin No. 223 193 205 182 222 177 234 192 207 176 233 191 221 175 232 159 220 206 231 190 204 174 219 205 230 189 218 172 229 203 201 187 185 188 186 171 169 172 170 158 VDD BZ_ENV VD SPA VSS TSR FRP REMOTE TBC_VD HID_IN VDD S_REEL T_REEL STR CAP_FG DRUM_FG VSS DRUM_FG MENU_P_B VSS MENU_P_A TAPE_LED Out Power supply (3V) Buzzer envelope output VDDH HID DRUM_REF CAP_REF Label ASPECT1 ASPECT2 S_IN_L L: Fixed (Not used) In/Out Out Out Description S2 terminal output, (To VIDEO AMP: IC3701) External input select control (S-IN: L), (To VIDEO INPUT SW: IC3851)
In Out Out In In In In In In In In In In In In In In In Out -
Power supply (3V) Head switch pulse L: Fixed (Not used) Drum offset voltage output, (To MDA: IC1601) Capstan offset voltage output, (To MDA: IC1601) L: Fixed (Not used) L: Fixed (Not used) Camera vertical reference pulse input, (From CAMERA DSP: IC4301) ATF sampling pulse, (From DECK DSP: IC3001) Ground HID reference (Drum 150Hz) Frame reference pulse, (From DVIO: IC3202) IR remote input, (From IR: IC1801) Analog input vertical reference pulse, (From ANALOG VIDEO I/O: IC3801) Head switch pulse Power supply (3V) SUP reel pulse TU reel pulse HID reference (Drum 150Hz) Capstan FG Drum FG Ground Drum FG Menu dial pulse B input Power supply (3V) Menu dial pulse A input Tape LED control, (To SENSOR) L: Fixed (Not used)
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Pin No. 154 156 153 157 155 140 138 142 139 141 137 124 122 123 121 125 106 107 105 109 108 93 91 94 90 92 89 78 74 76 73 77 59 75 58 60 57 43 42 44 41 Label BZ_FREQ IR_WB M_RVS AUDIO_CS VSS ROM_CS VF_CS M_CS AU_LCD_CLK AU_LCD_IN AU_LCD_OUT VDDH TBC_CLK TBC_IN TBC_OUT TBC_CS VPP ANA_CS VSS ANA_CLK ANA_IN ANA_OUT MDA_CLK MDA_IN VDD MDA_OUT SYS_CLK SYS_IN SYS_OUT READY VSS TXD RXD OSD_CLK OSD_DATA OSD_CS MIC_SCL VDDH MIC_SDA MIC_CTL C.SD In/Out Out In In Out Out Out Out Out Out In Out Out In Out Out Out In Out Out Out In In Out In Out Out Out Out Out Out Out In Description Buzzer frequency output White balance IR AC component detect input LCD monitor inversion switch input Audio chip select output, (To AUDIO: IC2201) Ground EEPROM chip select, (To EEPROM; IC7210) VF IC chip select, (To VF: IC7400) Monitor IC chip select, (To MONITOR: IC7300) AUDIO/LCD serial clock AUDIO/LCD serial data output AUDIO/LCD serial data input Power supply (3V) ANALOG VIDEO I/O serial data clock, (To ANALOG VIDEO I/O: IC3801) ANALOG VIDEO I/O serial data output, (To ANALOG VIDEO I/O: IC3801) ANALOG VIDEO I/O serial data input, (From ANALOG VIDEO I/O: IC3801) ANALOG VIDEO I/O chip select, (To ANALOG VIDEO I/O: IC3801) Power supply (3V) DV analyzer chip select, (To DVANA: IC3301) Ground DV analyzer clock, (To DVANA: IC3301) DV analyzer data input, (From DVANA: IC3301) DV analyzer data output, (To DVANA: IC3301) MDA Serial clock output, (To MDA: IC1601) MDA Serial data output, (To MDA: IC1601) Power supply (3V) MDA Serial data input, (From MDA: IC1601) Serial clock, (To SYSCON CPU: IC1001) Serial data output, (To SYSCON CPU: IC1001) Serial data input, (From SYSCON CPU: IC1001) Servo ready signal output, (To SYSCON CPU: IC1001) Ground Not used Onscreen character generator clock, (To OSD: IC1002) Onscreen character generator data output, (To OSD: IC1002) Onscreen character generator chip select, (To OSD: IC1002) Microphone Serial clock Power supply (3V) Microphone Serial data output Microphone power supply control Short detect input for capstan section
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3. Deck DSP (IC3001: JCY0106-2) function 1) Deck DSP (IC3001: JCY0106-2) pin functions (1/6)
Pin No. 69 1 134 70 2 71 3 135 189 226 72 4 136 73 190 5 227 137 74 6 191 138 75 7 8 76 139 192 228 9 77 140 193 229 10 78 141 230 194 11 79 142 231 VDD GND PWMAUDO VDDS VDD VCOAUDI VCOAUDO GND VDD OSC32I OSC32O OSC44I OSC44O OSC48I OSC48O GND AUDIOTESTI AUDIOTESTO VDDS DILRCK DIBCK DIMCK DIDAT AILRCK AIBCK AIMCK PHYCLK GND AIDAT [0] AIDAT [1] DOLRCK DOBCK DOMCK DODAT VDD AOLRCK AOBCK AOMCK AODAT [0] AODAT [1] VDDS GND Out Power supply Open (Not used) Audio serial data output, (To ADC: IC2101) Open (Not used) Power supply Ground Label In/Out Out In Out In Out Power supply Ground Audio PLL control signal, (To DVANA: IC3301) Power supply PB audio b PLL input, (From DVANA: IC3301) PB audio b PLL adjustment voltage output Ground Power supply L: Fixed (Not used) Not used Open (Not used) L: Fixed (Not used) Open (Not used) 24.5MHz clock input 24.5MHz clock output Ground L: Fixed H: Fixed Power supply Description
L: Fixed (Not used)
Out Out Out Out In
Serial I/O interface channel clock for ADC, (To ADC: IC2101) Audio serial data clock, (To ADC: IC2101) Audio master clock, (To ADC: IC2101) IEEE 1394 crystal oscillator output (27MHz), (To 1394 PHY: IC3101) Ground Audio serial data input, (From ADC: IC2101)
Open (Not used)
Table 3-4-3 Deck DSP (IC3001: JCY0106-2) pin functions (1/6)

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Deck DSP (IC3001: JCY0106-2) pin functions (2/6)

Pin No. 195 12 80 143 232 13 81 196 144 14 233 82 197 145 15 83 16 146 84 17 147 85 18 148 86 19 87 20 149 196 234 88 21 150 89 199 22 235 151 90 23 200 152 Label YSO [0] YSO [1] YSO [2] YSO [3] BRSO [0] BRSO [1] BRSO [2] BRSO [3] NC VDDS YSI [0] YSI [1] YSI [2] YSI [3] BRSI [0] BRSI [1] BRSI [2] BRSI [3] VDD OUTH OUTV INH INV GND VDD OSC27I OSC27O GND VDD NC RAMADRS [0] RAMADRS [1] RAMADRS [2] RAMADRS [3] VDDS RAMADRS [4] RAMADRS [5] RAMADRS [6] RAMADRS [7] GND RAMADRS [8] RAMADRS [9] Out Ground DRAM address output, (To 16M_DRAM: IC3002) Power supply DVC record digital color difference signal input (From CAMERA_DSP: IC4301, ANALOG VIDEO I/O: IC3801) Power supply Horizontal reference pulse output for DVC PB, (To CAMERA DSP: IC4301) Vertical reference pulse output for DVC PB, (To CAMERA DSP: IC4301) Horizontal reference pulse input for DVC REC, (From CAMERA DSP: IC4301, ) Vertical reference pulse input for DVC REC, (From CAMERA DSP: IC4301) Ground Power supply 27MHz clock input, (From CAMERA DSP: IC4301) Open (Not used) Ground Power supply Not used Out DVC playback digital luminaunce signal output, (To CAMERA_DSP: IC4301) In/Out Not used Description
Out
DVC playback digital color difference signal output, (To CAMERA_DSP: IC4301)
Not used Power supply DVC record digital luminaunce signal input (From CAMERA_DSP: IC4301, ANALOG VIDEO I/O: IC3801)
In
In
Out Out In In In -
Out
DRAM address output, (To 16M_DRAM: IC3002)
Out
DRAM address output, (To 16M_DRAM: IC3002)

3-48

Pin No. 91 24 25 92 153 201 235 26 93 154 202 237 27 94 155 238 203 28 95 156 239 204 29 96 157 240 30 97 205 158 31 241 98 206 159 32 99 33 160 100 34 161 101 VDD RAMWE RAMRAS RAMCAS [0] RAMCAS [1] RAMOE VDDS RAMDATA [0] RAMDATA [1] RAMDATA [2] RAMDATA [3] RAMDATA [4] RAMDATA [5] RAMDATA [6] RAMDATA [7] VDD NC RAMDATA [8] RAMDATA [9] RAMDATA [10] RAMDATA [11] RAMDATA [12] RAMDATA [13] RAMDATA [14] RAMDATA [15] GND XRESET GND CPUALE XCPUDSTB [0] XCPUDSTB [1] XCPURW XCPUCS XINT CPUWAIT CPUAD [0] CPUAD [1] CPUAD [2] CPUAD [3] VDD CPUAD [4] In In In In In In In Ground Reset pulse input, (From DECK CPU: IC1401) Ground Bus address strobe signal input, (From DECK CPU: IC1401) Bus memory write enable signal input, (From DECK CPU: IC1401) Bus memory read enable signal input, (From DECK CPU: IC1401) Bus read/write select signal input, (From DECK CPU: IC1401) Chip select input, (From DECK CPU: IC1401) Not used Open (Not used) Wait command, (From DECK_CPU: IC1401) Power supply Not used Label In/Out Out Out Out Out Out Not used Power supply Write enable output, (To 16M_DRAM: IC3002) Lower address strobe, (To 16M_DRAM: IC3002) Address strobe (Lower bit), (To 16M_DRAM: IC3002) Address strobe (Upper bit), (To 16M_DRAM: IC3002) Output enable (L: active), (To 16M_DRAM: IC3002) Power supply Description
In/Out
Audio/Shuffle/ECC memory data I/O, (From/To 16M_DRAM: IC3002)
In/Out
Audio/Shuffle/ECC memory data I/O, (From/To 16M_DRAM: IC3002)
In/Out
Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)
In/Out
Power supply Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)

3-49

Pin No. 35 162 102 36 103 37 163 207 242 104 38 164 105 208 39 243 165 106 40 209 166 107 41 42 108 167 210 244 43 109 168 211 245 44 110 169 246 212 45 111 170 247 213 Label CPUAD [5] CPUAD [6] CPUAD [7] GND NC CPUAD [8] CPUAD [9] CPUAD [10] CPUAD [11] VDDS CPUAD [12] CPUAD [13] CPUAD [14] CPUAD [15] VDD CPUWAITH VDD TESTIO [0] TESTIO [1] TESTIO [2] TESTIO [3] TESTIO [4] TESTIO [5] TESTIO [6] TESTIO [7] VDDS TESTIO [8] TESTIO [9] TESTIO [10] TESTIO [11] TESTIO [12] TESTIO [13] TESTIO [14] TESTIO [15] GND GND TESTIO [16] TESTIO [17] TESTIO [18] TESTIO [19] TESTIO [20] TESTIO [21] Open (Not used) Ground Open (Not used) Not used Power supply Open (Not used) In/Out In/Out Description Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401) Ground Not used
In/Out
Power supply
In/Out
Power supply H: Fixed (Not used) Power supply

3-50

Pin No. 46 112 171 248 47 113 214 172 48 249 114 215 173 49 115 50 174 116 51 175 117 52 176 118 53 119 54 177 216 250 120 55 178 121 217 56 251 179 122 57 218 180 123 Label TESTIO [22] TESTIO [23] VDD SCANENABLE SCANMODE TRST TDI TCK TMS TDO TEST VDD PHYDATA [3] PHYDATA [2] PHYDATA [1] PHYDATA [0] VDDS SCLK LOCONT XPHYISO PHYCTL [0] PHYCTL [1] PHYLREQ GND VDD EXTCLKIN EXREQ EXRW EXREADEMPTY EXWRITEFULL VDDS EXTDATA [0] EXTDATA [1] EXTDATA [2] EXTDATA [3] EXTDATA [4] EXTDATA [5] EXTDATA [6] EXTDATA [7] VDD GND Power supply Ground In/Out In Open (Not used) Power supply Not used L: Fixed (Not used) Reset signal input for boundary scan H: Fixed (Not used) L: Fixed (Not used) H: Fixed (Not used) Open (Not used) L: Fixed (Not used) Power supply Description
In/Out
Link interface data input/output, (From/To 1394PHY: IC3101)
Out Out In/Out -
Power supply IEEE1394 system clock (49.152MHz), (To 1394PHY:IC3101) H: Fixed Link interface isolation status (H: Enable), (To 1394PHY: IC3101) Link interface control (H: output), (From/To 1394PHY: IC3101) IEEE1394 link request signal output, (To 1394PHY:IC3101) Ground Power supply L: Fixed (Not used) H: Fixed (Not used) Open (Not used) Power supply Not used
Open (Not used)

3-51

Pin No. 58 59 124 181 219 252 60 125 182 220 253 61 126 183 254 221 62 127 184 255 222 63 128 185 256 64 129 223 186 65 225 130 224 187 66 131 67 188 132 68 133 PF [0] PF [1] SBE HID HSP PBDATA PBCLK VDDS TPNO [0] TPNO [1] TPNO [2] RECDATA RECCTL SPA RECCLK GND VCCA VCO4185 GNDA GND OSC4185I OSC4185O VDD VDD GND Label PWM405O VDDS VDD VCO405I VCO405O GND VDD CLK81SEL FRRES FRREF SERVOFRREF TRKREF SERVOTRKREF GND In/Out Out In In In In Out Out In In Out Out Out Out Open (Not used) Sync block error (Error pulse output) Head switch pulse (CH1: H, CH2: L), (To DECK CPU: IC1401) VITERBI processing termination playback data input, (From DVEQ: IC3201) VITERBI processing termination playback clock input, (From DVEQ: IC3201) Power supply Open (Not used) HSE (record data) output, (To PRE/REC: IC3501) Recording current control (H: ON), (To DVANA: IC3301) Pulse output for ATF sample, (To DVEQ: IC3201) Recording reference clock 41.85MHz Ground Power supply Constant for 41.85MHz VCO Ground L: Fixed (Not used) Open (Not used) Power supply Ground Description 40.5MHz (PLL control output) 1/2 frequency of VCO405I, (To DVANA: IC3301) Power supply 81MHz VCO reference clock input, (From DVANA: IC3301) Open (Not used) Ground Power supply H: Fixed (Not used) L: Fixed Frame reference signal input, (From DECK CPU: IC1401) Open (Not used) Drum servo reference signal input (150Hz), (From DECK CPU: IC1401) Open (Not used) Ground -
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4. 1394PHY IC (IC3101: PDI1394P11ABD) function 1) 1394PHY IC (IC3101: PDI1394P11ABD) pin functions (1/2)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Label RESET LPS LREQ VDD5V DVDD DVDD PD DGND SYSCLK DGND CTL0 CTL1 D0 D1 D2 D3 DGND DGND DVDD DVDD TESTM2 TESTM1 CPS AVDD AVDD AGND C/LKON PC0 PC1 PC2 CAN AGND In In/Out In In In Out Ground, for Analog circuit Bus/Isochronous resource manager input, LINK-ON signal output Power class bit 0 input Power class bit 1 input Power class bit 2 input Cable power supply status Ground, for Analog circuit In Test mode control ("1","1"=1394-1995 mode, "1","0"=1394a mode, "0","0"/"0","1"= reserve) Cable power supply status Power supply (3V), for Analog circuit Power supply (3V), for Digital circuit Ground, for Digital circuit In/Out Link interface reversible data signal, (From/To DVMAIN: IC3001) In Out In/Out Device power down input, (From DECK_CPU: IC1401) Ground, Digital circuit 49.152MHz clock output, (To DVMAIN: IC3001) Ground, for Digital circuit Link interface reversible control signal, (From/To DVMAIN: IC3001) In/Out In In In Description PHY reset signal input (L: active), (From DECK_CPU: IC1401) Link layer controller (LLC) power supply status Link request, (From DVMAIN: IC3001) Power supply (3V) Power supply (3V), for Digital circuit
Table 3-4-4 1394PHY IC (IC3101: PDI1394P11ABD) pin functions (1/2)
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1394PHY IC (IC3101: PDI1394P11ABD) pin functions (2/2)

Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TPB3TPB3+ TPA3TPA3+ TPB2TPB2+ TPA2TPA2+ AGND TPB1TPB1+ TPA1TPA1+ TPBIAS1 TPBIAS2 TPBIAS3 AGND AGND AVDD PLLGND PLLGND FILTER AVDD XI XO PLLVDD R0 R1 AGND ISO DGND DGND In Ground, for Analog circuit Link interface isolation status input, (To DVMAIN: IC3001) Ground, for Digital circuit In/Out In Out PLL external filter, capacitor termination Power supply (3V), for Analog circuit OSC connection terminal OSC connection terminal Power supply (3V), for PLL circuit Resistor termination for external current setting Power supply (3V), for Analog circuit Ground, for PLL circuit Ground, for Analog circuit Out Cable load power supply In/Out In/Out In/Out In/Out Ground, Analog circuit Port 1 cable pair B, negative signal Port 1 cable pair B, positive signal Port 1 cable pair A, negative signal Port 1 cable pair A, positive signal In/Out In/Out Port 2 cable pair B, negative signal Port 2 cable pair B, positive signal Open (Not used) Label In/Out In/Out In/Out Port 3 cable pair B, negative signal Port 3 cable pair B, positive signal Open (Not used) Description
Table 3-4-4 1394PHY IC (IC3101: PDI1394P11ABD) pin functions (2/2)
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3.5 EXPLANATION OF POWER SUPPLY CIRCUIT

3.5.1 Power supply circuit block diagram
Z_UNREG
CN303 JIG 28 29 30 F6103
DRUM REG
DRUM_PWR
CAP. REG
CAP_PWR
4.8V REG
M_REG4.8
+
DET
UNREG
F6102
IC6101 8ch SW-REG CTL DRUM_ERR
R6002 18k
CAP_ERR Q6106 F6105 SW TR T6101 TRA NS. REG_15.5 CCD_-7V
IC6001 2 4.2V DET 1 Q6001 Q6002 L:ON L:ON H:ON R6005 220k Q6003 R6006 100k Q6004 Q6005
F6101
4.6V REG
REG_4.6V
3V REG
DSC_3V
1.8V REG
REG_1.8V
P.ON:H
PWR_CTL
2.9V REG
D_REG2.9V A_REG2.9V M_UNREG
CHKUNREG Q6007
BATTCHK
BATT_SW IC6003 3.0V REG AL_3V IC6004 RESET D6002 LIT_3V RESET SP_UNREG AL_3V
D6001 Q6006 IC6002 3.3V REG CN303 JIG 27 CHR_STOP BT6001
Fig. 3-5-1 Power supply circuit block diagram A battery or DC coupler is used to supply power to this set. When the jig connector is used for servicing, neither battery nor DC coupler can be used as the power supply but necessary power can be supplied to the set from CN303 of the jig connector. The IC6001 detects the UNREG voltage and it turns off the Q6001 to prevent the battery from over-discharging when the UNREG voltage drops under a certain level. Although the IC6001 detects the voltage at 4.2 V by itself, detection level of UNREG voltage is switched in three steps by the functions of the resistors R6002, R6005, R6006 and the switches of Q6003, Q6004. Immediately after the power supply is connected to the set, both the Q6003 and Q6004 are turned on and the resistance type potential divider turns on the switch Q6001 when the UNREG voltage is 5.3 V or more. The IC6003 generates AL-3V and supplies it to the SYSCON. As soon as AL-3V is generated, the Q6003 is turned off and the detection level of the UNREG voltage is accordingly switched down to 4.95 V to prevent hunting
3-55
phenomenon that the Q6001 is switched on and off repeatedly because of temporary voltage drop by load. When the set is turned on, the SYSCON outputs the PWR-CTL H signal to switch off the Q6004. Accordingly the detection level of the UNREG voltage is furthermore lowered to 4.2 V not to switch off the Q6001 by voltage fluctuation. Since the SYSCON monitors the UNREG voltage with the BATTCHK signal, it shuts off the set when the voltage drops to 5.8 V or lower that is the lower limit of the operating voltage. Voltage information of the BATTCHK signal is also used for indicating the remaining battery power. The switch of the battery holder discriminates the power supply from between the battery and DC coupler, and the BATT-SW signal is output not to indicate the remaining battery power when the DC coupler supplies the power to the set. The IC6004 generates the RESET signal for the SYSCON CPU. However, the SYSCON of this set is reset each time the power supply is connected to the set, because no reset switch is installed in this set. The LIT -3V is supplied only to the IC of the RTC (Real-Time Counter). When the power supply is connected to the set, the LIT -3V is supplied by the AL-3V and the button battery BT6001 is charged by 3.3 V supplied from the IC6002. The button battery supplies 3.3 V only when no power supply is connected to the set. IC6101 is the 8CH switching regulator controller. When the set is turned on, the PWR-CTL H signal from the SYSCON CPU turns the level at the pin 43 (STB) of the IC6101 into the H level to start the DC-DC converter so that it produces various voltages to be supplied to each part of the set.
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3.5.2 Power supply section IC function 1. Regulator IC (IC6101: BD9712KU) function 1) Regulator IC (IC6101: BD9712KU) block diagram
CSCP SOFT
STB2
VDD VREF VDD VREF SOFT
STB6
GND
STB
Vcc
TIMER
S LATCH R Q
U.V.L.O VIN1
VDD
FETDRV
INV1
DUTY SHIFT SYNCDRV
FB1 SCP1 VDD

FETDRV
VG1 PG1 VGL1 PGL1 SYNC1 VIN2 VG2 PG2 VGL2 PGL2 SYNC2
INV2 FB2 SCP2 VDD

FETDRV DUTY SHIFT SYNCDRV
VIN3 VG3 PG3 VGL3 PGL3 SYNC3 VIN4

FETDRV
INV3 FB3 SCP3
DUTY SHIFT
SYNCDRV
VG4 PG4 VIN5
INV4 FB4 SCP4

FETDRV
INV5 FB5 SCP5 INV6 FB6 SCP6 NON7 INV7 FB7 SCP7 NON8 INV8 FB8 SCP8 CT RT OSC BUFF
FETDRV FETDRV FETDRV
VG5 PG5 VIN6 VG6 PG6 VIN7 VG7 PG7 VIN8 VG8 PG8
DTC6 DTC5 DTC2
Fig. 3-5-2 Regulator IC (IC6101: BD9712KU) block diagram

3-57
2) Regulator IC (IC6101: BD9712KU) pin functions (1/2)

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC NC NC DTC5 FB5 INV5 SCP5 DTC6 FB6 INV6 SCP6 FB7 INV7 NON7 SCP7 NC FB6 INV8 NON8 SCP8 PG7 VG7 VIN7 PG8 VG8 VIN8 CT RT CSCP GND VREF Vcc VDD SOFT NC PGL1 VGL1 PG1 VG1 VIN1 Label In/Out In Out In In In Out In In Out In In In Out In In In Out Out Out Out Not used Dead time control (soft start setting) Error amp output terminal Error amp inversion input terminal Short protect operation detect input terminal Dead time control (soft start setting) Error amp output terminal Error amp inversion input terminal Short protect operation detect input terminal Error amp output terminal Error amp inversion input terminal Error amp noninversion input terminal Short protect operation detect input terminal Not used Error amp output terminal Error amp inversion input terminal Error amp noninversion input terminal Short protect operation detect input terminal FET driver ground terminal (Hi side) FET driver output (Hi side) FET driver power supply terminal FET driver ground terminal (Hi side) FET driver output (Hi side) FET driver power supply terminal Triangle waveform timing capacitor terminal Triangle waveform timing resistor terminal Short protect timer latch setting capacitor terminal Ground Reference voltage output Power supply terminal Internal power supply voltage monitor terminal Soft start setting terminal Not used Synchronized rectification FET driver connection terminal Synchronized rectification FET driver output terminal FET driver ground terminal (Hi side) FET driver output (Hi side) FET driver power supply terminal Description
Table 3-5-1 Regulator IC (IC6101: BD9712KU) pin functions (1/2)
3-58
Regulator IC (IC6101: BD9712KU) pin functions (2/2)

Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 STB6 STB2 STB SCP1 INV1 FB1 SCP2 INV2 FB2 SCP3 INV3 FB3 SCP4 SYNC1 INV4 FB4 SYNC2 DTC2 NC NC VIN2 VG2 PG2 VGL2 PGL2 VIN3 VG3 PG3 VGL3 PGL3 SYNC3 VIN4 VG4 PG4 VIN5 VG5 PG5 VIN6 VG6 PG6 Label In/Out In In In In In Out In In Out In In Out In In Out Out Out Out Out Out Out Out CH6, 2 ON/OFF switch CH6, 2 ON/OFF switch All channel ON/OFF switch Short protect operation detect input terminal Error amp inversion input terminal Error amp output terminal Short protect operation detect input terminal Error amp inversion input terminal Error amp output terminal Short protect operation detect input terminal Error amp inversion input terminal Error amp output terminal Short protect operation detect input terminal Synchronized rectification ON/OFF switch Error amp inversion input terminal Error amp output terminal Synchronized rectification ON/OFF switch Dead time control (Soft start setting) Not used FET driver power supply terminal FET driver output (Hi side) FET driver ground terminal (Hi side) Synchronized rectification FET driver output terminal Synchronized rectification FET driver connection terminal FET driver power supply terminal FET driver output (Hi side) FET driver ground terminal (Hi side) Synchronized rectification FET driver output terminal Synchronized rectification FET driver connection terminal Synchronized rectification ON/OFF switch FET driver power supply terminal FET driver output (Hi side) FET driver ground terminal (Hi side) FET driver power supply terminal FET driver output (Hi side) FET driver ground terminal (Hi side) FET driver power supply terminal FET driver output (Hi side) FET driver ground terminal (Hi side) Description
Table 3-5-1 Regulator IC (IC6101: BD9712KU) pin functions (2/2)
3-59
VICTOR COMPANY OF JAPAN, LIMITED
Printed in Japan 2000-03 (TM1)

JVC GR-DVL9800 Technical Guide

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What are some of the new technologies employed in the GR-DVL9800 camera?

What are some of the new technologies employed in the GR-DVL9800 camera?

What are the main sections covered in the technical guide?

What are the main sections covered in the technical guide?

VIDEO TECHNICAL GUIDE

DIGITAL VIDEO CAMERA

COPYRIGHT 2000 VICTOR COMPANY OF JAPAN, LTD.

SECTION 2 EXPLANATION OF NEW TECHNOLOGIES

SECTION 3 EXPLANATION OF ELECTRICAL CIRCUIT

SECTION 1 OUTLINE OF THE PRODUCTS

Table list differing points between models (GR-DVL9500/GR-DVX7/DVM70/GR-DVL9800) (2/3)

PS WIDE Shutter speed Fader Scene

Date/Time Auto Flash Snapshot

Audio dubbing Insert editing Dual Shooting

Snapshot in PB Snapshot search DSC Recording function

Yes (Excluding Nega-Posi) No No

Table list differing points between models (GR-DVL9500/GR-DVX7/DVM70/GR-DVL9800) (3/3)

Yes (shared with AV terminal)

NewSoft Presto! Mr.Photo Ver1.2 PhotoAlbum Ver1.5.7 ImageFolio Ver4.1.6

SECTION 2 EXPLANATION OF NEW TECHNOLOGIES

Fig. 2-1-1 VF/monitor screen

2.1.2 1/3"-type Progressive scan CCD having 680,000 (*800,000) pixels

962 654 (*774) Effective area PS-Wide / DSC-XGA 720

Effective area Video / DSC-VGA

Cutting out an effective area at the FMC(EIS)

Effective area EIS area Reducing the size of picture by FMC

200 X Digital Zoom

PS Wide Mode : Total 14 X

Fig. 2-1-3 PS wide mode

Normal 1/60 (*1/50)

Fig. 2-1-4 Signal charge of CCD in high-speed recording

Normal 1/60 (*1/50)

1/250 High shutter speed 1/250 Reset Read Out Timing

Additional functions of area selecting and 4X PS-CCD 2X Horizontal

4X mode Image area

High speed sweeping area

2X Vertical mode Image area

Fig. 2-1-6 Actual image area in high-speed recording

Images recorded on the TAPE

(PB by other DVC or DV OUTPUT)

VIDEO OUTPUT or LCD MONITOR of GR-DVL9800

Field image of 2X Horizontal mode recording

Arrenging images at FMC in Camera section

1/8 Slow-Motion Playback

Field image of 2X Vertical mode recording

Arrenging images at FMC in Camera section

1/8 Slow-Motion Playback

Field image of 4X mode recording

Arrenging images at FMC in Camera section

1/8 Slow-Motion Playback

2.2 EXPLANATION OF DCF

DVC00002.JPG DCF DIRECTORY DCF IMAGE DIRECTORY IMAGE FILE DVC00003.JPG

Fig. 2-2-1 Directory and file construction of MMC

DCIM - 100J V C G R - D V C 0 0001. J P G

Still picture index screen

Fig. 2-2-4 Screen of still picture playback by DSC

2.3 EXPLANATION OF DPOF

Table 2-3-1 Contents of DPOF file

Fig. 2-3-2 DPOF file

SECTION 3 EXPLANATION OF ELECTRICAL CIRCUIT

962 492 (584) 654 (774)

327 (387) HD 654 (774) Lines BVOB:2 FVOB:6