Multiple Timer Interrupt Example2
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zOubaida feMultiple Timer Interrupt Example2
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zOubaida feParadigm of Several Timer Interrupts
This chapter discusses a scenario where two tasks vie for execution
simultaneously. In a situation known as "preemption," allowing priority
interruption becomes essential to complete the first task (from Ready to Run
state) before enabling the second task to enter the "Run" mode. In this
experiment, two LEDs connected to GPIOC 6 and 7 pins flash to indicate the
update rates of the general-purpose timers used in this study.
1) General-purpose timers overview
The general-purpose timers (TIM2-TIM5) consist of a 16-bit auto-reload
counter driven by a programmable prescaler.
Measuring the pulse lengths of input signals (input capture)
Generating output waveforms (output compare, PWM)
Pulse lengths and waveform periods can be modulated from a few
microseconds to several milliseconds using the timer prescaler and the RCC
clock controller prescalers.
General-purpose (TIMx) timers are completely independent, and do not
share any resources.
They can still be synchronized together.
16-bit up, down, up/down auto-reload counter
16-bit programmable prescaler allowing dividing (also “on the fly”)
the counter clock frequency either by any factor between 1 and 65535.
Up to 4 independent channels for :
Input Capture
Output Compare
PWM generation (Edge and Center-aligned Mode)
One-pulse mode output
Synchronization circuit to control timer with external signals and to
interconnect several timers together.
Interrupt/DMA generation based on several events.
1
2
The main block of the programmable timer is a 16-bit counter
with its related auto-reload register
The counter can count up, down or both up and down
The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler
register can be written or read by software
This is true even when the counter is running
The time-base unit includes:
Counter register (TIMx_CNT)
Prescaler register (TIMx_PSC)
Auto-reload register (TIMx_ARR)
Auto-reload register is preloaded
Writing to or reading from the auto-reload register accesses the
preload register
Contents of preload register are transferred into the shadow register
permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register
Update event is sent when counter reaches overflow or underflow
and if the UDIS bit equals 0 in TIMx_CR1 register
Update event can also be generated by software
Counter is clocked by prescaler output CK_CNT, which is enabled
only when counter enable bit (CEN) in TIMx_CR1 register is set
actual counter enable signal CNT_EN is set 1 clock cycle after CEN
Prescaler can divide the counter clock frequency by any factor between 1 and
65536
Based on a 16-bit counter controlled through a 16-bit register (in the
TIMx_PSC register)
It can be changed on the fly as this control register is buffered
New prescaler ratio is taken into account at the next update event
Counter timing diagram with prescaler division change from 1 to 4
Counter counts from 0 to the auto-reload value (content of the TIMx_ARR
register), then restarts from 0 and generates a counter overflow event
An Update event can be generated at each counter overflow or by setting the
UG bit in the TIMx_EGR register
When an update event occurs, all the registers are updated and the update
flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):
3
The buffer of the prescaler is reloaded with the preload value (content
of the TIMx_PSC register)
The auto-reload shadow register is updated with the preload value
(TIMx_ARR)
2) Some essential timer registers
4
TIMx Slave Mode Control Register (TIMx_SMCR)
TIMx Event Generation Register (TIMx_EGR)
TIMx Counter (TIMx_CNT)
TIMx Prescaler (TIMx_PSC)
5
TIMx Auto-Reload Register (TIMx_ARR)
TIMx DMA/Interrupt Enable Register (TIMx_DIER)
TIMx Status Register (TIMx_SR)
3) Application:
As mentioned above, we focus our attention on the simultaneous flashing of two
LEDs with different frequencies using Timer3 and Timer5 with interruption to
understand this behavior in the task priority management system.
void setup();
void GPIO_init();
void Timer3_init();
void Timer5_init();
void TIM3_ISR() iv IVT_INT_TIM3 ics ICS_AUTO{
TIM3_SR.UIF = 0;
GPIOC_ODR.B7 ^= 1;
}
void TIM5_ISR()iv IVT_INT_TIM5 ics ICS_AUTO{
TIM5_SR.UIF = 0;
GPIOC_ODR.B6 ^= 1;
}
6
void main(){
setup();
while(1)
{
};
}
void setup(){
GPIO_init();
Timer3_init();
Timer5_init();
}
void GPIO_init(){
RCC_APB2ENR.IOPCEN=1;
GPIOC_CRL=0x22444444;
GPIOC_CRH=0x44444444;
GPIOC_ODR.B6 = 1;
GPIOC_ODR.B7 = 1;
}
void Timer3_init(){
RCC_APB1ENR.TIM3EN = 1;
TIM3_CR1.CEN=0; //enable_TIM3_counter(false);
TIM3_PSC = 575;
TIM3_ARR = 62499;
DIR_TIM3_CR1_bit=1; // TIM3_CR1 |=(1<<4); Downcounting
TIM3_EGR.UG=1; // Re-initialize the counter and generate an update
NVIC_IntEnable(IVT_INT_TIM3);
EnableInterrupts();
NVIC_SetIntPriority (IVT_INT_TIM3, _NVIC_INT_PRIORITY_LVL1); // Set Priority
TIM3_DIER.UIE = 1; // up-date interrupt enable
TIM3_CR1.CEN=1; // enable_TIM3_counter
}
void Timer5_init(){
RCC_APB1ENR.TIM5EN = 1;
TIM5_CR1.CEN = 0;
TIM5_PSC = 575;
TIM5_ARR = 12499;
DIR_TIM5_CR1_bit=0; // UP-Counting
TIM5_EGR.UG=1; // Re-initialize the counter and generate an update
NVIC_IntEnable(IVT_INT_TIM5);
EnableInterrupts();
NVIC_SetIntPriority (IVT_INT_TIM5, _NVIC_INT_PRIORITY_LVL2); // Set Priority
TIM5_DIER.UIE = 1;
TIM5_CR1.CEN = 1;
}