VLSI Design

Subject code:PCCEEE310G
Semester: VI
 Unit –I
Basic MOS Transistor
 Content

• MOSFET structure
• Enhancement mode
• Depletion mode
• Introduction of IC Technology
• IC Fabrication process
• NMOS Technology
• PMOS Technology
• CMOS Technology
• BICMOS Technology
 MOSFET
• Metal oxide semiconductor field transistors can be considered as
switch which operates with proper biasing.
• MOSFET is three terminal device source , drain and gate.
• Biasing means application of appropriate voltage at three terminal of
MOSET so that it can be moved from on to off state or vice versa.
 MOSFET
• Metal-Oxide-Semiconductor (MOS) structure is created by
superimposing several layers of conducting and insulating materials to
form a sandwich- like structure.
• These structures are manufactured using a series of chemical processing
steps involving oxidation of the silicon, selective introduction of dopants,
and deposition and etching of metal wires and contacts.
• Transistor operation is controlled by electric fields so the devices are also
called Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)
• Types of MOSFET
 Based on material properties
• N Mos- where electrons are charge carriers
• P Mos- where holes are charge carriers
 MOSFET
Based on electrical properties
• Enhancement mode MOSFET
• Depletion mode MOSFET
• So technically four types of MOSFET
• N channel Enhancement mode MOSFET
• P channel Enhancement mode MOSFET
• P channel Depletion mode MOSFET
• N channel Depletion mode MOSFET
•
 Introduction
• Each transistor consists of a stack of the conducting gate, an insulating layer of silicon
dioxide (SiO2), and the silicon wafer, also called the substrate, or body, or bulk.
• An nMOS transistor is built with a p-type body and has regions of n-type
• semiconductor adjacent to the gate called the source and drain
• A pMOS consists of p-type source and drain regions with an n-type body.
•
MOSFET :Cutoff Region mode

• When VGS < VT, there is no channel formed between the Drain
and Source and hence IDS=0 A
• This region is called the Cutoff Region
• This region of operation is when the Transistor is OFF
MOSFET : Cutoff Region mode
• When VGS > VT, a channel is formed. IDS is dependent on the VDS
voltage
• When VDS = 0v, no current flows.
 MOSFET: Linear Region mode
• If VGS > VT and VDS > 0, then a current will flow from the Drain to
Source (IDS).The MOSFET operates like a voltage controlled
resistor which yields a linear relationship between the applied
voltage (VDS) and the resulting current (IDS)
• For this reason, this mode of operation is called the Linear
Region. This region is also sometimes called the triode region
(we'll use the term "linear")
• VDS can increase up to a point where the current ceases to
increase linearly (saturation)
• We denote the highest voltage that VDS can reach and still yield
a linear increase in current as the saturation voltage or VDSAT
when a voltage is applied at VD, its positive charge pushes
the majority charge carriers (holes) that exist at the edge of the
depletion region further from the Drain.
• As the depletion region increases, it becomes more difficult for the
Gate voltage to induce an inversion layer. This results in the
inversion layer depth decreasing near the drain.
• As VD increases further, it eventually causes the inversion layer to
be pinched-off and prevents the current flow to increase any
further.
• This point is defined as the saturation voltage (VDSAT)
• From this, we can define the linear region as:
VGS>VT
0< V D S < V D S A T
 MOSFET : Saturation Region mode
• MOSFET is defined as being in saturation when: Saturation Region :
VGS > VT and VDS > (VGS-VT)
• An increase in VDS does not increase IDS because the channel is
pinched-off
• However, an increase in VGS DOES increase IDS by increasing the
channel depth and hence the amount of current that can be
conducted.
 MOSFET Regions of Operation
• Cut-Off Region
When VGS < VT, no conductive channel is present and IDS = 0, the cutoff region.
• Ohmic or Linear Region
Ohmic or linear region is a region where in the current IDS increases with an
increase in the value of VDS. When MOSFETs are made to operate in this region,
they can be used as amplifiers.
• Saturation Region
In saturation region, the MOSFETs have their IDS constant inspite of an increase in
VDS and occurs once VDS exceeds the value of pinch-off voltage VP. Under this
condition, the device will act like a closed switch through which a saturated value
of IDS flows. As a result, this operating region is chosen whenever MOSFETs are
required to perform switching operations.
Types of MOSFET
 Enhancement-mode MOSFET
• For the n-channel enhancement MOS transistor a drain current will only flow
when a gate voltage ( VGS ) is applied to the gate terminal greater than the
threshold voltage ( VTH ) level in which conductance takes place making it a
transconductance device.
• The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts
more electrons towards the oxide layer around the gate thereby increasing or
enhancing (hence its name) the thickness of the channel allowing more current to
flow. This is why this kind of transistor is called an enhancement mode device as
the application of a gate voltage enhances the channel.
• Increasing this positive gate voltage will cause the channel resistance to decrease
further causing an increase in the drain current, ID through the channel. In other
words, for an n-channel enhancement mode MOSFET: +VGS turns the transistor
“ON”, while a zero or -VGS turns the transistor “OFF”. Thus the enhancement-
mode MOSFET is equivalent to a “normally-open” switch.
 Enhancement-mode MOSFET
• The reverse is true for the p-channel enhancement MOS transistor.
When VGS = 0 the device is “OFF” and the channel is open. The
application of a negative (-ve) gate voltage to the p-type eMOSFET
enhances the channels conductivity turning it “ON”. Then for an p-
channel enhancement mode MOSFET: +VGS turns the transistor
“OFF”, while -VGS turns the transistor “ON”.
n-channel Enhancement-type MOSFET
 Transfer characteristics
• The transfer characteristics (drain-to-source current IDS versus gate-to-source voltage VGS) of n-
channel Enhancement-type MOSFETs. From this, it is evident that the current through the
device will be zero until the VGS exceeds the value of threshold voltage VT. This is because
under this state, the device will be void of channel which will be connecting the drain and the
source terminals. Under this condition, even an increase in VDS will result in no current flow as
indicated by the corresponding output characteristics (IDS versus VDS) shown by Figure 1b. As a
result this state represents nothing but the cut-off region of MOSFET’s operation.
• Next, once VGS crosses VT, the current through the device increases with an increase in IDS
initially (Ohmic region) and then saturates to a value as determined by the VGS (saturation
region of operation) i.e. as VGS increases, even the saturation current flowing through the
device also increases. This is evident by Figure 1b where IDSS2 is greater than IDSS1 as VGS2 >
VGS1, IDSS3 is greater than IDSS2 as VGS3 > VGS2, so on and so forth. Further, Figure 1b also
shows the locus of pinch-off voltage (black discontinuous curve), from which VP is seen to
increase with an increase in VGS.
p-channel Enhancement-type MOSFET
 Transfer characteristics
• Figure 2a shows the transfer characteristics of p-type enhancement MOSFETs from which it
is evident that IDS remains zero (cutoff state) until VGS becomes equal to -VT. This is
because, only then the channel will be formed to connect the drain terminal of the device
with its source terminal. After this, the IDS is seen to increase in reverse direction (meaning
an increase in ISD, signifying an increase in the device current which will flow from source
to drain) with the decrease in the value of VDS. This means that the device is functioning in
its ohmic region wherein the current through the device increases with an increase in the
applied voltage (which will be VSD).
• However as VDS becomes equal to –VP, the device enters into saturation during which a
saturated amount of current (IDSS) flows through the device, as decided by the value of
VGS. Further it is to be noted that the value of saturation current flowing through the device
is seen to increase as the VGS becomes more and more negative i.e. saturation current for
VGS3 is greater than that for VGS2 and that in the case of VGS4 is much greater than both of
them as VGS3 is more negative than VGS2 while VGS4 is much more negative when
compared to either of them (Figure 2b). In addition, from the locus of the pinch-off voltage it
is also clear that as VGS becomes more and more negative, even the negativity of VP also
increases.
 Depletion -mode MOSFET
The Depletion-mode MOSFET, which is less common than the enhancement mode
types is normally switched “ON” (conducting) without the application of a gate bias
voltage. That is the channel conducts when VGS = 0 making it a “normally-closed”
device. The circuit symbol shown above for a depletion MOS transistor uses a solid
channel line to signify a normally closed conductive channel.
For the n-channel depletion MOS transistor, a negative gate-source voltage, -VGS will
deplete (hence its name) the conductive channel of its free electrons switching the
transistor “OFF”. Likewise for a p-channel depletion MOS transistor a positive gate-
source voltage, +VGS will deplete the channel of its free holes turning it “OFF”.
In other words, for an n-channel depletion mode MOSFET: +VGS means more electrons
and more current. While a -VGS means less electrons and less current. The opposite is
also true for the p-channel types. Then the depletion mode MOSFET is equivalent to a
“normally-closed” switch.
 n-channel Depletion-type
MOSFET
• The transfer characteristics of n-channel depletion MOSFET shown by Figure 3a indicate that the device has a
current flowing through it even when VGS is 0V. This indicates that these devices conduct even when the gate terminal
is left unbiased, which is further emphasized by the VGS0 curve of Figure 3b. Under this condition, the current through
the MOSFET is seen to increase with an increase in the value of VDS (Ohmic region) untill VDS becomes equal to
pinch-off voltage VP. After this, IDS will get saturated to a particular level IDSS (saturation region of operation) which
increases with an increase in VGS i.e. IDSS3 > IDSS2 > IDSS1, as VGS3 > VGS2 > VGS1. Further, the locus of the pinch-off
voltage also shows that VP increases with an increase in VGS.
n-channel Depletion-type
MOSFET
 p-channel Depletion-type
MOSFET
• The transfer characteristics of p-channel depletion mode MOSFETs (Figure 4a) show that these devices will be
normally ON, and thus conduct even in the absence of VGS. This is because they are characterized by the
presence of a channel in their default state due to which they have non-zero IDS for VGS = 0V, as indicated by
the VGS0 curve of Figure 4b. Although the value of such a current increases with an increase in VDS initially
(ohmic region of operation), it is seen to saturate once the VDS exceeds VP (saturation region of operation).
The value of this saturation current is determined by the VGS, and is seen to increase in negative direction as
VGS becomes more and more negative. For example, the saturation current for VGS3 is greater than that for
VGS2 which is however greater when compared to that for VGS1. This is because VGS2 is more negative
when compared to VGS1, and VGS3 is much more negative when compared to either of them. Next, one can
also note from the locus of pinch-off point that even VP starts to become more and more negative as the
negativity associated with the VGS increases.
Lastly, it is evident from Figure 4a that inorder to switch these devices OFF, one needs to increase VGS such
that it becomes equal to or greater than that of the threshold voltage VT. This is because, when done so, these
devices will be deprived of their p-type channel, which further drives the MOSFETs into their cut-off region of
operation.
p-channel Depletion-type
MOSFET
CMOS structure
Basic structure
Basic structure
 CMOS Inverter
•
NOR gate
•
Basic structure
Guess this device?

5 MB Hard disk by IBM IN 1956

Advancement due to VLSI
Achieved through VLSI
Very Large Scale Integration
Why VLSI?
Application of ICs
IC Evolution
Moore’s Law
Moore’s Law (cont..)
Processing technologies of VLSI
Power dissipation & propagation delay
N MOS &PMOS transistors
IC fabrication process
IC Fabrication process-Video from Intel
Creating wafers
Silicon wafer manufacturing process
Oxidation
•
 NMOS FABRICATION PROCESS
1.Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity
into which the required p-impurities are introduced as the crystal is grown. Such wafers are
typically 75 to 150 mm in diameter and 0.4 mm thick and are doped with, say, boron to
impurity concentrations of 1015/cm3 to 1016/cm3 , giving resistivity in the approximate
range 25 ohm cm to 2 ohm cm.