X1021 Iot Application Processor: Data Sheet

X1021
IoT Application Processor

Data Sheet
Release Date: Apr. 28, 2020

X1021 IoT Application Processor
Data Sheet
Copyright © 2005-2020 Ingenic Semiconductor Co. Ltd. All rights reserved.
Disclaimer
This documentation is provided for use with Ingenic products. No license to Ingenic property rights is
granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to the
usage, or intellectual property right infringement except as provided for by Ingenic Terms and
Conditions of Sale.
Ingenic products are not designed for and should not be used in any medical or life sustaining or
supporting equipment.
All information in this document should be treated as preliminary. Ingenic may make changes to this
document without notice. Anyone relying on this documentation should contact Ingenic for the current
documentation and errata.
Ingenic Semiconductor Co., Ltd.
Ingenic Headquarters, Zhongguancun Software Park,

Dongbeiwang West Road, Haidian District, Beijing, China,
Tel: 86-10-56345000
Fax: 86-10-56345001
Http: //www.ingenic.com
CONTENTS
1 Overview ............................................................................................ 1
1.1 Block Diagram ......................................................................................................................... 1
1.2 Features .................................................................................................................................. 1
1.2.1 CPU ................................................................................................................................. 1
1.2.2 ISP ................................................................................................................................... 2
1.2.3 Image post processor(IPU) ............................................................................................. 2
1.2.4 Display(LCD) ................................................................................................................... 3
1.2.5 Video input....................................................................................................................... 3
1.2.6 Audio ............................................................................................................................... 3
1.2.7 Memory Interface ............................................................................................................ 4
1.2.8 System Functions ............................................................................................................ 4
1.2.9 Peripherals ...................................................................................................................... 6
1.2.10 Bootrom ........................................................................................................................... 9
1.3 Characteristic .......................................................................................................................... 9
2 Packaging and Pinout Information ................................................... 10

2.1 Overview ............................................................................................................................... 10
2.2 Solder Process ...................................................................................................................... 10
2.3 Moisture Sensitivity Level ..................................................................................................... 10
2.4 X1021 Package ..................................................................................................................... 10
2.5 Pin Description ....................................................................................................................... 11
2.5.1 Static Memory/DVP/I2C0................................................................................................ 11
2.5.2 SFC ............................................................................................................................... 13
2.5.3 MSC0/GMAC/PWMx/UARTx/I2C1/JTAG/SLCD ........................................................... 13
2.5.4 MSC1/SSI0/PWMx/I2C1/GMAC/UART2/CAMERA/SLCD ........................................... 15
2.5.5 GPIO.............................................................................................................................. 16
2.5.6 System........................................................................................................................... 17
2.5.7 Digital IO/core power/ground......................................................................................... 17
2.5.8 DDR power/ground........................................................................................................ 18
2.5.9 Analog - USB ................................................................................................................. 18
2.5.10 Analog - SARADC ......................................................................................................... 19
2.5.11 Analog - CODEC ........................................................................................................... 19
2.5.12 Analog - MAC-PHY ....................................................................................................... 19
2.5.13 Analog - EFUSE ............................................................................................................ 20
2.5.14 Analog - CLOCK/PLL .................................................................................................... 20
2.5.15 Analog - RTC ................................................................................................................. 20
3 Electrical Specifications ................................................................... 22

3.1 Absolute Maximum Ratings .................................................................................................. 22
3.2 Recommended operating conditions .................................................................................... 22
3.3 Audio codec .......................................................................................................................... 24
CONTENTS
3.3.1 Microphone input ........................................................................................................... 24

3.3.2 ALC ................................................................................................................................ 24
3.3.3 Headphone output ......................................................................................................... 25
3.3.4 Microphone bias ............................................................................................................ 25
3.4 MAC PHY .............................................................................................................................. 25
3.5 Power On, Reset and BOOT ................................................................................................. 26
3.5.1 Power-On Timing ........................................................................................................... 26
3.5.2 Reset procedure ............................................................................................................ 28
3.5.3 BOOT ............................................................................................................................. 28
ii
X1021 IoT Application Processor Data Sheet
Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
Overview
1 Overview
X1021 is a high performance and high integrated application processor, the application is focus on IoT
devices. And it can match the requirements of many other embedded products.
1.1 Block Diagram
Figure 1-1 X1021 Diagram
1.2 Features
1.2.1 CPU
 XBurst®-1 core
– XBurst® FPU instruction set supporting both single and double floating point format
which are IEEE754 compatible
– XBurst® 9-stage pipeline micro-architecture, the operating frequency is 800MHz
 MMU
– 32-entry joint-TLB
– 8 entry instruction TLB
– 8 entry data TLB
 L1 Cache
– 16kB instruction cache
1
Overview
– 16kB data cache

 Hardware debug support
 16kB tight coupled memory
 L2 Cache
– 64kB unify cache
1.2.2 ISP
 Dynamic/Static Defect Pixel Correction
 Green Equalization
 Black Level Correction
 Lens Shading Correction
 3A(Auto Exposure/Auto White Balance/Auto Focus)
 Support Statistical Information Output(3A)
 Adaptive Dynamic Range Compression
 Demosaic
 Sharpen
 Bayer Denoise
 2D/3D Denosie
 Color Noise Suppression
 Lens Distortion Correction
 2D Color Correction
 3D Color Correction
 Gamma Correction
 Defog
 3 Independent Image Scaler and Output
 Crop, Mirror and Flip
 Support Maximum Resolution:2048x2048
 Flash timer
1.2.3 Image post processor(IPU)

 AXI Bus for data transaction
 Input data format:
― NV12
 Output data format:
― ARGB, RGB
― NV12/NV21
― HSV
 Color conversion feature: input and output format can be chosen freely from input and output
data format.
 Minimum input image size (pixel): 4x4
 Maximum input image size (pixel): 2048x2048
 Minimum output image size (pixel): 4x4
2
Overview
 Maximum output image size (pixel): 2048x2048

 Background channel OSD function:
― Support 4 layers OSD
― Support whole background picture into OSD process and partial picture into OSD
process
― Support 12 port-duff OSD modes
― Support 1 input format in background channel: NV12
― Output picture format must be NV12
1.2.4 Display(LCD)
 Basic Features
― Display size up to 800x600@60Hz,24BPP
― SLCD interface 6800(type A) and 8080(type B)
 Colors Supports
― Support up to 16,777,216 (16M) colors
 Panel Supports
― transmit 565 by one cycle via SLCD 16bit data interface
― transmit 666 by two cycle via SLCD 9bit data interface
― transmit 565 by two cycle via SLCD 8bit data interface
― transmit 888 by three cycle via SLCD 8bit data interface
― Supports different size of display panel
― Supports internal DMA operation and direct write register operation
1.2.5 Video input

 Support 8/10/12 bit RGB Bayer input
 Support maximum：2688x2048 @20fps, 1080p @60fps,720p @120fps
 Support single-sensor input
 Support DVP/BT1120(serial mode)/BT656/BT601
1.2.6 Audio
 Integrated Audio codec.
– 24 bits DAC with 93dB SNR
– 24 bits ADC with 92dB SNR
– Support signal-ended and differential microphone input and line input
– Automatic Level Control (ALC) for smooth audio recording
– Pure logic process: no need for mixed signal layers and less mask cost
– Programmable input and output analog gains
– Digital interpolation and decimation filter integrated
– Sampling rate 8K/12K/16K/24K/32/44.1K/48K/96K
3
Overview
1.2.7 Memory Interface

 Integrated DDR on chip
 Static memory interface
– Support 6 external chip selection CS6~1#. Each bank can be configured separately
– The size and base address of static memory banks are programmable
– Direct interface to 8-bit bus width external memory interface devices or external static
memory to each bank. Read/Write strobe setup time and hold time periods can be
programmed and inserted in an access cycle to enable connection to low-speed memory
– Wait insertion by WAIT pin
– Automatic wait cycle insertion to prevent data bus collisions in case of consecutive
memory accesses to different banks, or a read access followed by a write access to the
same bank
1.2.8 System Functions

 Clock generation and power management
– On-chip 12/24/48MHZ oscillator circuit
– External 32.768KHZ input
– One three-chip phase-locked loops (PLL) with programmable multiplier
– CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK, frequency can be changed
separately for software by setting registers
– SSI clock supports 50M clock
– MSC clock supports 100M clock
– Functional-unit clock gating
– Shut down power supply for P0, ISP, IPU
 Timer and counter unit with PWM output and/or input edge counter
– Provide eight separate channels, six of them have input signal transition edge counter
– 16-bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generation when the A counter underflows
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB
Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
– Every channel has PWM output
 OS timer
– 64-bit counter and 32-bit compare register
– Support interrupt generation when the counter matches the compare register
– Two clock sources: RTCLK (real time clock), HCLK (system bus clock) selected with 1, 4,
16, 64, 256 and 1024 clock dividing selected
 Interrupt controller
– Total 64 interrupt sources
– Each interrupt source can be independently enabled
– Priority mechanism to indicate highest priority interrupt
– All the registers are accessed by CPU
– Unmasked interrupts can wake up the chip in sleep mode
4
Overview
– Another set of source, mask and pending registers to serve for PDMA
 Watchdog timer
– Generates WDT reset
– A 16-bit Data register and a 16-bit counter
– Counter clock uses the input clock selected by software
 PCLK, EXTAL and RTCCLK can be used as the clock for counter
 The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software
 Direct memory access controllers
– Support up to 32 independent DMA channels
– Descriptor or No-Descriptor Transfer mode compatible with previous JZ SoC
– Transfer data units: 1-byte, 2-byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte
– Transfer number of data unit: 1 ~ 224 - 1
– Independent source and destination port width: 8-bit, 16-bit, 32-bit
– Fixed three priorities of channel groups: 0~3, highest; 4~11: mid; 12~31: lowest
– An extra INTC IRQ can be bound to one programmable DMA channel
 SAR A/D Controller
– 2 Channels
– Resolution: 10-bit
– Integral nonlinearity: ±1 LSB
– Differential nonlinearity: ±0.5 LSB
– Resolution/speed: up to 2MSPS
– Max Frequency: 24MHz
– Low power dissipation: 1.5mW(worst)
– Support multi-touch detect
– Support write control command by software
– Single-end and Differential Conversion Mode
– Support external touch screen controller
– Pin Description
 RTC (Real Time Clock)
– Need external 32768Hz oscillator for 32k clock generation
– 32-bits second counter
– Programmable and adjustable counter to generate accurate 1 Hz clock
– Alarm interrupt, 1Hz interrupt
– Stand alone power supply, work in hibernating mode
– Power down controller
– Alarm wakeup
– External pin wakeup with up to 2s glitch filter
 OTP Slave Interface
– Total 2048 bits. Lower 192bits are read only, other higher bits are read-able and
write-able
5
Overview
1.2.9 Peripherals
 General-Purpose I/O ports
– Each port can be configured as an input, an output or an alternate function port
– Each port can be configured as an interrupt source of low/high level or rising/falling edge
triggering. Every interrupt source can be masked independently
– Each port has an internal pull-up or pull-down resistor connected. The pull-up/down
resistor can be disabled
– GPIO output 3 interrupts, each interrupt corresponds to the group, to INTC
 SMB Controller
– Two-wire SMB serial interface – consists of a serial data line (SDA) and a serial clock
(SCL)
– Two speeds
 Standard mode (100 Kb/s)
 Fast mode (400 Kb/s)
– Device clock is identical with pclk
– Programmable SCL generator
– Master or slave SMB operation
– 7-bit addressing/10-bit addressing
– 16-level transmit and receive FIFOs
– Interrupt operation
– The number of devices that you can connect to the same SMB-bus is limited only by the
maximum bus capacitance of 400pF
– APB interface
– 2 independent SMB channels (SMB0, SMB1)
 One High Speed Synchronous serial interfaces (SFC)

– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI
– transmit-only or receive-only operation
– MSB first for command and data transfer, and LSB first for address transfer
– 64 entries x 32 bits wide data FIFO
– one device select
– Configurable sampling point for reception
– Configurable timing parameters: tSLCH, tCHSH and tSHSL
– Configurable flash address wide are supported
– 7 transfer formats: Standard SPI, Dual-Output/Dual-Input SPI, Quad-Output/Quad-Input
SPI, Dual-I/O SPI, Quad-I/O SPI, Full Dual-I/O SPI, Full Quad-I/O SPI
– two data transfer mode: slave mode and DMA mode
– Configurable 6 phases for software flow
 Two Normal Speed Synchronous serial interfaces (SSI0, SSI1)

– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI
– Full-duplex or transmit-only or receive-only operation
6
Overview
– Programmable transfer order: MSB first or LSB first

– 128 entries deep x 32 bits wide transmit and receive data FIFOs
– Configurable normal transfer mode or Interval transfer mode
– Programmable clock phase and polarity for Motorola’s SSI format
– Two slave select signal (SSI_CE_ / SSI_CE2_) supporting up to 2 slave devices
– Back-to-back character transmission/reception mode
– Loop back mode for testing
 Three UARTs (UART0, UART1, UART2)

– Full-duplex operation
– 5-, 6-, 7- or 8-bit characters with optional no parity or even or odd parity and with 1, 1½,
or 2 stop bits
– 64x8 bit transmit FIFO and 64x11bit receive FIFO
– Independently controlled transmit, receive (data ready or timeout), line status interrupts
– Internal diagnostic capability Loopback control and break, parity, overrun and
framing-error is provided
– Separate DMA requests for transmit and receive data services in FIFO mode
– Supports modem flow control by software or hardware
– Slow infrared asynchronous interface that conforms to IrDA specification
 Two MMC/SD/SDIO controllers (MSC0, MSC1)

– Fully compatible with the MMC System Specification version 4.2
– Support SD Specification 3.0
– Support SD I/O Specification 1.0 with 1 command channel and 4 data channels
– Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1)
– Maximum data rate is 50MBps
– Support MMC data width 1bit ,4bit and 8bit
– Built-in programmable frequency divider for MMC/SD bus
– Built-in Special Descriptor DMA
– Maskable hardware interrupt for SDIO interrupt, internal status and FIFO status
– 128 x 32 built-in data FIFO
– Multi-SD function support including multiple I/O and combined I/O and memory
– IRQ supported enable card to interrupt MMC/SD controller
– Single or multi block access to the card including erase operation
– Stream access to the MMC card
– Supports SDIO read wait, interrupt detection during 1-bit or 4-bit access
– Supports CE-ATA digital protocol commands
– Support Command Completion Signal and interrupt to CPU
– Command Completion Signal disable feature
– The maximum block length is 4096bytes
 USB 2.0 OTG interface

– Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the
7
Overview
On-The-Go supplement to the USB 2.0 specification

– Operates either as the function controller of a high- /full-speed USB peripheral or as the
host/peripheral in point-to-point or multi-point communications with other USB functions
– Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
– UTMI+ Level 3 Transceiver Interface
– Soft connect/disconnect
– 16 Endpoints
– Dedicate FIFO
– Supports control, interrupt, ISO and bulk transfer
 Ethernet Media Access controller and interface

– 10, 100Mbps data transfer rates with the following PHY interfaces:
 RMII interface to communicate with an external Fast Ethernet PHY
 RMII PHY integrated
– Full-duplex operation:
 IEEE 802.3x flow control automatic transmission of zero-quanta Pause frame on
flow control input de-assertion
 forwarding of received Pause frames to the user application
– Half-duplex operation:
– CSMA/CD Protocol support
– Frame bursting and frame extension in 100 Mbps half-duplex operation
– Preamble and start of frame data (SFD) insertion in Transmit path
– Preamble and SFD deletion in the Receive path
– Automatic CRC and pad generation controllable on a per-frame basis
– Automatic Pad and CRC Stripping options for receive frames
– Flexible address filtering modes, such as:
 Up to 31 additional 48-bit perfect (DA) address filters with masks for each byte
 64-bit Hash filter for multicast and unicast (DA) addresses
 Option to pass all multicast addressed frames
 Promiscuous mode to pass all frames without any filtering for network monitoring
 Pass all incoming packets (as per filter) with a status report
– Support Standard or Jumbo Ethernet frames with up to 2 KB of size
– IEEE 802.1Q VLAN tag detection for reception frames
– MDIO master interface for PHY device configuration and management
– CRC replacement, Source Address field insertion or replacement, and VLAN insertion,
replacement, and deletion in transmitted frames with per-frame control
– Programmable watchdog timeout limit in the receive path
– Detect remote wake-up frames and AMD magic packets
 Digital True Random Number Generator（DTRNG）

– Pure digital logic circuits
– True random number
– Interrupt mode and no interrupt mode
8
Overview
1.2.10 Bootrom
32kB Boot ROM memory
1.3 Characteristic
Item Characteristic
Process Technology 28nm CMOS low power
Power supply voltage General purpose I/O: 1.5~3.6V
DDR I/O: DDR2 ± 0.1V
RTC I/O: 1.5V~3.6V
EFUSE programming: 1.5V ± 10%
Analog power supply 1: 1.8V ± 10%
Analog power supply 2: 3.3V ± 10%
Core: 1.0V ± 0.1V
Package BGA152 9mm x 9mm x 1.22mm, 0.65mm pitch
Operating frequency 800MHz
9
Packaging and Pinout Information
2 Packaging and Pinout Information

2.1 Overview
X1021 processor is offered in 152-pin BGA package, which is 9mm x 9mm x 1.22mm outline, 10 x 10
matrix ball grid array and 0.65mm ball pitch, show in Figure 2-1. The X1021 pin to ball assignment is
show in Figure 2-2. The detailed pin description is listed in Table 2-1 ~ Table 2-16.
2.2 Solder Process

X1021 package is lead-free. It’s reflow profile follows the IPC/JEDEC lead-free reflow profile as
contained in J-STD-020C.
2.3 Moisture Sensitivity Level

X1021 package moisture sensitivity is level 3.
2.4 X1021 Package
Figure 2-1 X1021 package outline drawing
10
X1021 Ball Assignment Ver1.4

BGA152, 9mm X 9mm X1.22mm, 0.65pitch, top view
0 1 2 3 4 5 6 7 8 9 10 11 12 13
SSI0_CE1_U MSC1_CLK_
SSI0_CE0_P MSC1_D3_M MSC1_D1_M
ART2_RXD_ MAC_LED_S
MSC0_D0_P UART0_RXD UART1_RXD SMB1_SDA_ DDR_PLLVC WM5_UART AC_LED_RX AC_LED_DU
A B00 _TDI_PB19 _TMS_PB24 PB25 CD 2_RXD_PC1
SMB1_SCK_
_SLCD_D5_
PEED100_S
PLEX_SLCD A
SLCD_CS_P LCD_D0_PC
4 PC07 _D3_PC05
C09 02
SSI0_GPC_
SSI0_CLK_P SSI0_DR_P MSC1_CMD
UART2_TXD
MSC0_D3_P MSC0_CLK_ MSC0_D1_P UART0_CTS UART1_TXD SMB1_SCK_ DDR_PLLVC WM4_UART WM2_UART _MAC_LED_ SFC_GPC_P SFC_CLK_P
B B03 PB04 B01 _PB20 _TCK_PB23 PB26 CA 2_TXD_PC1 2_CTS_PC1
_SMB1_SDA
TX_SLCD_D A25 A27 B
_SLCD_DC_
3 1 1_PC03
PC08
SSI0_DT_P MSC1_D2_M MSC1_D0_M

BOOT_SEL1 MSC0_D2_P MSC0_CMD UART0_TXD UART0_RTS WM3_UART AC_LED_LIN AC_LED_SP SFC_DT_PA SFC_CE1_P
C _PC01 B02 _PB05 _TDO_PB22 _PB21
VREF
2_RTS_PC1 K_SLCD_D4 EED10_SLC 23 A26 C
2 _PC06 D_D2_PC04
CLK32K_OU
PWM6_SLC
BOOT_SEL0 T_PWM7_SL SFC_DR_PA SFC_CE0_P
D PLL_VDDA
_PC00
TRST VDDMEM VDDMEM VDDMEM VDDMEM
CD_TE_PC1
D_WR_PC1
24 A28 D
5
6
PWM1_FLA PWM0_FLA
SH_OUT_UA SH_STORB
RD_SMB0_S
E EXCLK_XI EXCLK_XO RTC_VDD RST_DELAY DDRVDD DDRVDD DDRVDD DDRVDD RT2_RTS_S E_IN_UART WAIT_PA22 GPIO_PA18
CK_PA13 E
LCD_D7_PC 2_CTS_SLC
18 D_D6_PC17
CS2_SMB0_ DVP_VSYNC
F OSC32_XI OSC32_XO AVDEFUSE VSSMEM VSSMEM VSSMEM VSSMEM VSSMEM VDDIO2
SDA_PA12 _PA17 F
DVP_MCLK_ DVP_HSYN DVP_PCLK_

G RTC_VDDIO PPRST_ AUX0 TEST_TE DDRVSS DDRVSS DDRVSS DDRVSS DDRVSS VDDIO2
PA15 C_PA16 PA14 G
SADC_VREF SA2_DVP_D CS1_DVP_D

H AUX1
P
WKUP_PA30 VSS VSS VSS VSS VSS VDDIO0
10_PA10 11_PA11 H
SADC_AVD SD7_DVP_D SA0_DVP_D SA1_DVP_D

J D
USB0PN USB0PP VSS VSS VDD VDD VDD VDD VDDIO0
7_PA07 8_PA08 9_PA09 J
SD5_DVP_D SD6_DVP_D
K USB_VCC33 USB_VCC18 VSS VDD VDD VDD VDD VDDIO1 VDDIO1
5_PA05 6_PA06 K
GMAC_MDC GMAC_RXD
K_SSI1_CLK 0_MAC_LED SLCD_RDY_ SD3_DVP_D SD4_DVP_D
L USB_VCC10 MICN MICBIAS
_SLCD_D4_ _LINK_SLCD PB28
MAC_TXN MAC_RXN MAC_VDDA
3_PA03 4_PA04 L
PB10 _WR_PB15
GMAC_TXD
GMAC_PHY
GMAC_RXD GMAC_RXD 1_SSI1_CE1
_CLK_MAC_
DRV_VBUS_ V_SSI1_DR_ 1_MAC_LED _MAC_LED_ PWM0_SLC MAC_EXTR SD1_DVP_D SD2_DVP_D
M MICP VCM
PB27 SLCD_D3_P _RX_SLCD_
LED_TX_SL
DUPLEX_SL D_CS_PB17
MAC_TXP MAC_RXP
ES 1_PA01 2_PA02 M
CD_D1_PB0
B09 TE_PB16 CD_D7_PB1
7
GMAC_TXD 4
GMAC_TXC
GMAC_MDI 0_SSI1_GPC GMAC_TXE
LK_MAC_LE
CODEC_AV O_SSI1_CE0 _MAC_LED_ N_SSI1_DT_ PWM1_SLC MAC_TEST_ MAC_VDDH SD0_DVP_D
N HPOUT
DD _SLCD_D5_
D_SPEED10
SPEED10_S SLCD_D2_P D_DC_PB18
GPIO_PB31
ATP V 0_PA00 N
0_SLCD_D0
PB11 LCD_D6_PB B08
_PB06
13
1 2 3 4 5 6 7 8 9 10 11 12 13
Figure 2-2 X1021 pin to ball assignment
2.5 Pin Description
2.5.1 Static Memory/DVP/I2C0

Table 2-1 Static Memory/DVP/I2C0 Pins(19)
Pin Names IO Loc IO Cell Char. Pin Description Power

SD0 IO 8mA SD0: Static memory data bus bit 0
DVP_D0 I N13 DVP_D0:DVP data bit 0 VDDIO0
PA00 IO PA00: GPIO group A bit 00
11

DVP_D1 I M12 DVP_D1:DVP data bit 1 VDDIO0
DVP_D2 I M13 DVP_D2:DVP data bit 2 VDDIO0
DVP_D3 I L12 DVP_D3:DVP data bit 3 VDDIO0
DVP_D4 I L13 DVP_D4:DVP data bit 4 VDDIO0
DVP_D5 I K11 DVP_D5:DVP data bit 5 VDDIO0
DVP_D6 I K12 DVP_D6:DVP data bit 6 VDDIO0
DVP_D7 I J11 DVP_D7:DVP data bit 7 VDDIO0
SA0 O 8mA SA0: Static memory address bus bit 0
DVP_D8 I J12 DVP_D8:DVP data bit 8 VDDIO0
DVP_D9 I J13 DVP_D9: DVP data bit 9 VDDIO0
DVP_D10 I H12 DVP_D10: DVP data bit 10 VDDIO0
CS1 O 8mA CS1: Static memory chip 1 select
DVP_D11 I H13 Pullup-rst DVP_D11: DVP data bit 11 VDDIO0
CS2 O 8mA CS2: Static memory chip 2 select
SMB0_SDA IO F12 Pullup-rst SMB0_SDA: I2C 0 serial data VDDIO0
RD O 8mA RD: Static memory read signal
SMB0_SCK IO E13 Pullup-rst SMB0_SCK: I2C 0 serial clock VDDIO0
DVP_PCLK I 8mA DVP_PCLK: camera sensor pixel clock input
G13 VDDIO0
DVP_MCLK O 8mA DVP_MCLK: DVP main clock output
G11 VDDIO0
PA15 IO Slew-rate-rst PA15: GPIO group A bit 15
DVP_HSYNC I 8mA DVP_HSYNC: DVP horizontal sync
G12 VDDIO0
DVP_VSYNC I 8mA DVP_VSYNC: DVP vertical sync
F13 VDDIO0
WAIT O 8mA WAIT: Slow static memory/device wait signal
PA22 IO E11 Pullup-rst PA22: GPIO group A bit 22 VDDIO0
Schmitt-rst
12
2.5.2 SFC
Table 2-2 SFC Pins(6)

SFC_DT IO 8mA SFC_DT: high speed ssi transmit data
C12 VDDIO1
PA23 IO Pullup-rst PA23: GPIO group A bit 23
SFC_DR IO 8mA SFC_DR: high speed ssi receive data
D11 VDDIO1
SFC_GPC IO 8mA SFC_GPC: high speed ssi general-purpose control
B12 VDDIO1
SFC_CE1 IO 8mA SFC_CE1: high speed ssi chip 1 select
C13 VDDIO1
SFC_CLK O 8mA SFC_CLK: high speed ssi clock
B13 VDDIO1
SFC_CE0 O 8mA SFC_CE0: high speed ssi chip 0 select
D12 VDDIO1
2.5.3 MSC0/GMAC/PWMx/UARTx/I2C1/JTAG/SLCD
Table 2-3 MSC0/GMAC/PWMx/UARTx/I2C1/JTAG/SLCD (28)

MSC0_D0 IO 8mA MSC0_D0: MSC (MMC/SD) 0 data bit 0
A2 VDDIO1
PB00 IO PB00: GPIO group B bit 00
B3 VDDIO1
C2 VDDIO1
B1 VDDIO1
MSC0_CLK O 8mA MSC0_CLK: MSC (MMC/SD) 0 clock output
B2 VDDIO1
MSC0_CMD IO 8mA MSC0_CMD: MSC (MMC/SD) 0 command
C3 VDDIO1
GMAC_TXCLK I 8mA GMAC_TXCLK: gmac transmitting clock
MAC_LED_SPEE O MAC_LED_SPEED100: speed100 indication
D100 N5 SLCD_D0: smart lcd data output bit 0 VDDIO1
SLCD_D0 O PB06: GPIO group B bit 06
PB06 IO
GMAC_PHY_CLK O 8mA GMAC_PHY_CLK: gmac phy clock
MAC_LED_TX O MAC_LED_TX: TX activity indication
M6 VDDIO1
SLCD_D1 O SLCD_D1: smart lcd data output bit 1
GMAC_TXEN O 8mA GMAC_TXEN: gmac transmitting enable
SSI1_DT O SSI1_DT: normal speed ssi 1 transmit data
N7 VDDIO1
GMAC_RXDV I 8mA GMAC_RXDV: gmac receive data valid
M4 VDDIO1
SSI1_DR I SSI1_DR: normal speed ssi 1 receive data
13

PB09 IO PB09: GPIO group B bit 09.
GMAC_MDCK O 8mA GMAC_MDCK: gmac manage data clock
SSI1_CLK O Pulldown-rst SSI1_CLK: normal speed ssi 1 clock
L4 VDDIO1
GMAC_MDIO IO 8mA GMAC_MDIO: gmac MDIO which is clocked
SSI1_CE0 O Pullup-rst by MDC
SLCD_D5 O N3 SSI1_CE0: normal speed ssi 1 chip 0 select VDDIO1
PB11 IO SLCD_D5: smart lcd data output bit 5
PB11: GPIO group B bit 11.
GMAC_TXD0 O 8mA GMAC_TXD0: gmac transmit data bit 0
SSI1_GPC O SSI1_GPC: normal speed ssi 1
MAC_LED_SPEE O general-purpose control
D10 N6 MAC_LED_SPEED10: PHY speed10 VDDIO1
SLCD_D6 O indication
PB13 IO SLCD_D6: smart lcd data output bit 6
PB13: GPIO group B bit 13.
GMAC_TXD1 O 8mA GMAC_TXD1: gmac transmit data bit 1
SSI1_CE1 O Pullup-rst SSI1_CE1: normal speed ssi 1 chip 1 select
MAC_LED_DUPL O MAC_LED_DUPLEX: PHY duplex indication
M7 VDDIO1
EX SLCD_D7: smart lcd data output bit 7
SLCD_D7 O PB14: GPIO group B bit 14.
PB14 IO
GMAC_RXD0 I 8mA GMAC_RXD0: gmac receive data bit 0
MAC_LED_LINK O MAC_LED_LINK: PHY link ON indication
L5 VDDIO1
SLCD_WR O SLCD_WR: smart lcd write data control
GMAC_RXD1 I 8mA GMAC_RXD1: gmac receive data bit 1
MAC_LED_RX O MAC_LED_RX: PHY RX activity indication
M5 VDDIO1
SLCD_TE I SLCD_TE: smart lcd crack control
PWM0 O 8mA PWM0: PWM channel 0 output
SLCD_CS O M8 Pullup-rst SLCD_CS: smart lcd chip select VDDIO1
SLCD_DC O N8 Pulldown-rst SLCD_DC: smart lcd cmd/data identify VDDIO1
UART0_RXD I 8mA UART0_RXD: UART 0 receive data
TDI I A3 Pullup-rst TDI: JTAG data input VDDIO1
UART0_CTS I 8mA UART0_CTS: UART 0 clear-to-send
PB20 IO B4 handshaking VDDIO1
PB20: GPIO group B bit 20
UART0_RTS O 8mA UART0_RTS: UART 0 request-to-send
PB21 IO C5 handshaking VDDIO1
PB21: GPIO group B bit 21
UART0_TXD O 8mA UART0_TXD: UART 0 transmit data
TDO O C4 TDO: JTAG data output VDDIO1
UART1_TXD O B5 8mA UART1_TXD: UART 1 transmit data VDDIO1
14

TCK I TCK: JTAG clock input
UART1_RXD I 8mA UART1_RXD: UART 1 receive data
TMS I A5 Pullup-rst TMS: JTAG mode select VDDIO1
SMB1_SDA IO 8mA SMB1_SDA: I2C 1 serial data
A6 VDDIO1
PB25 IO Pullup-rst PB25: GPIO group B bit 25
SMB1_SCK IO 8mA SMB1_SCK: I2C 1 serial clock
B6 VDDIO1
PB26 IO Pullup-rst PB26: GPIO group B bit 26
DRV_VBUS O 8mA DRV_VBUS:USB-5V control
M3 VDDIO1
PB27 IO Schmitt-rst PB27: GPIO group B bit 27
SLCD_RDY I 8mA SLCD_RDY: smart lcd work status
L7 VDDIO1
PB28 IO Schmitt-rst PB28: GPIO group B bit 28
2.5.4 MSC1/SSI0/PWMx/I2C1/GMAC/UART2/CAMERA/SLCD
Table 2-4 MSC1/SSI0/PWMx/I2C1/GMAC/UART2/CAMERA/SLCD Pins (16)

MSC1_CLK O 8mA MSC1_CLK: MSC (MMC/SD) 1 clock output
MAC_LED_SPE O MAC_LED_SPEED100: speed100 indication
ED100 A12 SLCD_D0: smart lcd data output bit 0 VDDIO2
SLCD_D0 O PC02: GPIO group C bit 02
PC02 IO
MSC1_CMD IO 8mA MSC1_CMD: MSC (MMC/SD) 1 command
MAC_LED_TX O MAC_LED_TX: TX activity indication
B11 VDDIO2
PC03 IO PC03: GPIO group C bit 03
MAC_LED_SPE O MAC_LED_SPEED10: speed10 indication
ED10 C11 SLCD_D2: smart lcd data output bit 2 VDDIO2
PC04 IO
MAC_LED_DUP O MAC_LED_DUPLEX: duplex indication
LEX A13 SLCD_D3: smart lcd data output bit 3 VDDIO2
PC05 IO
MAC_LED_LIN O MAC_LED_LINK: link ON indication
K C10 SLCD_D4: smart lcd data output bit 4 VDDIO2
PC06 IO
MAC_LED_RX O MAC_LED_RX: RX activity indication
A11 VDDIO2
PC07 IO PC07: GPIO group C bit 07
15

SSI0_GPC O 8mA SSI0_GPC: ssi 0 general-purpose control
UART2_TXD I Pullup-rst UART2_TXD: UART 2 transmit data
SMB1_SDA IO B10 SMB1_SDA: I2C 1 serial data VDDIO2
SLCD_DC O SLCD_DC: smart lcd cmd/data identify
PC08 IO PC08: GPIO group C bit 08.
SSI0_CE1 O 8mA SSI0_CE1: ssi 0 chip 1 select
UART2_RXD I Pullup-rst UART2_RXD: UART 2 receive data
SMB1_SCK IO A9 SMB1_SCK: I2C 1 serial clock VDDIO2
SLCD_CS O SLCD_CS: smart lcd chip select
SSI0_DR I 8mA SSI0_DR: ssi 0 receive data
PWM2 O PWM2: PWM channel 2 output
UART2_CTS I B9 UART2_CTS: UART 2 Clear-to-Send VDDIO2
PC11 IO handshaking
PC11: GPIO group C bit 11.
SSI0_DT O 8mA SSI0_DT: ssi 0 transmit data
UART2_RTS O C9 UART2_RTS: UART 2 Request-to-Send VDDIO2
PC12 IO handshaking
SSI0_CLK O 8mA SSI0_CLK: ssi 0 clock
B8 VDDIO2
UART2_TXD O UART2_TXD: UART 2 transmit data
SSI0_CE0 O 8mA SSI0_CE0: ssi 0 chip 0 select
PWM5 O Pullup-rst PWM5: PWM channel 5 output
A8 VDDIO2
UART2_RXD I UART2_RXD: UART 2 receive data
SLCD_WR I D10 Pulldown-rst SLCD_WR: smart lcd write data control VDDIO2
PC15 IO Schmitt-rst PC15: GPIO group C bit 15.
CLK32K_OUT O 8mA CLK32K_OUT: 32.768K clock output
PWM7 O Pulldown-rst PWM7: PWM channel 7 output
D9 VDDIO2
SLCD_TE I Schmitt-rst SLCD_TE: smart lcd crack control
FLASH_STORB I Pulldown-rst FLASH_STORBE_IN: camera flash store input
E_IN Schmitt-rst UART2_CTS: UART 2 clear-to-send
E10 VDDIO2
UART2_CTS I handshaking
FLASH_OUT O Pulldown-rst FLASH_OUT: camera flash out
UART2_RTS O Schmitt-rst UART2_RTS: UART 2 request-to-send
E9 VDDIO2
SLCD_D7 O handshaking
PC18 IO SLCD_D7: smart lcd data output bit 7
2.5.5 GPIO
Table 2-5 GPIO Pins (2)
16
PA18 IO E12 8mA PA18: GPIO group A bit 18 VDDIO0

PB31 IO 8mA PB31: GPIO group B bit 31
N9 VDDIO1
Pulldown-rst
2.5.6 System
Table 2-6 System Control Pins(6)

TRST I 8mA TRST: JTAG reset VDDIO1
D4 Schmitt
pull-down
RST_DELAY I E4 8mA RST_DELAY: system reset delay time control VDDIO1
WKUP_PA30* I 8mA WKUP_PA30: Wakeup signal after main power RTC_VD
H4
Schmitt down DIO
PPRST_ I 8mA PPRST_: RTC power on reset and RTC_VD
G2
Schmitt RESET-KEY reset input DIO
TEST_TE I 8mA TEST_TE: Manufacture test enable, program
RTC_VD
G4 Schmitt readable
DIO
pull-down
Table 2-7 Boot Select Pins(2)

(BOOT_SEL0) I 8mA PC00: GPIO group C bit 00
PC00 IO D2 Pullup-rst It is taken as BOOT select bit 0 by Boot ROM VDDIO1
code
(BOOT_SEL1) I 8mA PC01: GPIO group C bit 01
PC01 IO D3 Pulldown-rst It is taken as BOOT select bit 1 by Boot ROM VDDIO1
code
2.5.7 Digital IO/core power/ground

Table 2-8 IO/Core power supplies Pins (22)

VDDIO0 P - VDDIO0: IO digital power for DVP
H10,J10 -
power domain, 1.8/3.3V
VDDIO1 P - VDDIO1: IO digital power for normal
K9,K10 -
function Pad power domain, 3.3V
VDDIO2 P - VDDIO2: IO digital power for low
F10,G10 -
leakage power domain, 1.8/3.3V
VDD P J6,J7,J8,J9,K5 VDD: CORE digital power, 1.0V
-
,K6,K7,K8 -
17

VSS P H5,H6,H7,H8, VSS: IO digital ground for none DRAM
-
H9,J4,J5,K4 - and CORE digital ground, 0V
2.5.8 DDR power/ground

Table 2-9 DDR power/ground supplies Pins (21)

VREF P - VREF: DDR reference voltage,
C7 -
(VREF = VDDMEM/2)
VDDMEM P VDDMEM: DDR IO supply(1.8V for
D5,D6,D7,D8 -
- DDR2)
VSSMEM P F5,F6,F7,F8,F VSSMEM: DDR IO ground
-
9 -
DDRVDD P DDRVDD: DDR PHY 1.8V supply
E5,D6,D7,D8
- -
DDRVSS P G5,G6,G7,G8, DDRVSS: DDR PHY ground
G9 - -
DDR_PLLVCCD P - DDR_PLLVCCD: DDR PLL power -
A7
supply for digital
DDR_PLLVCCA P - DDR_PLLVCCA: DDR PLL power -
B7
supply for analog
2.5.9 Analog - USB

Table 2-10 USB 2.0 OTG (5)

USB0PP AIO J3 - USB0PP: USB data-positive USB_VCC33
USB0PN AIO J2 - USB0PN: USB data-negative USB_VCC33
USB_VCC33 P - USB_VCC33: This is the analog supply that is
used to support 3.3V signaling. This supply
has both integrated IO pads and associated
ESD. The expectation is that this supply is
K2 unique to the USB PHY. The PHY provides -
two pins for this power supply, but they can
often be bonded out to a single package pin if
the parasitic are low enough to support the
current draw.
K3 used to support 1.8V signaling. This supply -
has both integrated IO pads.
used to support 1.0V circuits within the PHY.
This supply has both integrated IO pads and
L1 -
associated ESD. As this includes power
supplied to the PLL and HS driver, the supply
needs to be fairly quiet. The PHY provides
18

two pins for this power supply, but they can
often be bonded out to a single pin if the
parasitic are low enough to support the
current draw.
2.5.10 Analog - SARADC

Table 2-11 SARADC Pins (4)

AUX0 AI G3 - AUX0: SARADC channel 0 input SADC_AVDD
AUX1 AI H1 - AUX1: SARADC channel 1 input SADC_AVDD
SADC_AVDD P - SADC_AVDD: SARADC analog power,
J1 -
1.8 V
SADC_VREFP P - SADC_VREFP: Voltage reference input,
H2 -
0.5* SADC_AVDD~0.99* SADC_AVDD
2.5.11 Analog - CODEC

Table 2-12 CODEC Pins (6)

MICP AI M1 - MICP: differential microphone input CODEC_AVDD
MICN AI L2 - MICN: differential microphone input CODEC_AVDD
VCM AO M2 - VCM: Reference voltage output CODEC_AVDD
MICBIAS AO L3 - MICBIAS: Microphone bias output CODEC_AVDD
HPOUT AO N1 - HPOUT: headphone output CODEC_AVDD
CODEC_AVDD P N2 - CODEC_AVDD:1.8V analog supply -
2.5.12 Analog - MAC-PHY

Table 2-13 MAC-PHY Pins(8)

MAC_TXN AO L9 - MAC_TXN: PHY transmit data-negative MAC_VDDA
MAC_TXP AO M9 - MAC_TXP: PHY transmit data-positive MAC_VDDA
MAC_RXN AI L10 - MAC_RXN: PHY receive data-negative MAC_VDDA
MAC_RXP AI M10 - MAC_RXP: PHY receive data-positive MAC_VDDA
MAC_EXTRE AIO - MAC_EXTRES: PHY connection to
S reference resistor
M11 MAC_VDDA
NOTES: 6.5KΩ should be connected
externally on board.
MAC_TEST_A AIO - MAC_TEST_ATP: PHY analog test point
N11 -
TP NOTES: Resistance < 1Ω;inductance <
19

5nH
MAC_VDDHV P - MAC_VDDHV: PHY 1.8V analog power
N12 -
supply for central bias
MAC_VDDA P - MAC_VDDA: PHY 1.0V analog power
L11 -
supply for RX and TX
2.5.13 Analog - EFUSE

Table 2-14 EFUSE Pins (1)

AVDEFUSE P - AVDEFUSE: EFUSE programming power,
F4 -
0V/1.5V
2.5.14 Analog - CLOCK/PLL

Table 2-15 CLOCK/PLL Pins (6)

EXCLK_XI AI 2~30 MHz EXCLK_XI: external oscillator clock input or
E1 RTC_VDDIO
Oscillator, external 24MHz clock input
EXCLK_XO AO E2 OSC on/off EXCLK_XO: external oscillator clock output RTC_VDDIO
PLL_VDDA P D2 - PLL_VDDA: PLL analog power, 1.8V -
2.5.15 Analog - RTC

Table 2-16 RTC Pins (4)

OSC32_XI AI F1 32.768KHz osc32_XI: 32.768KHz clock input RTC_VDDIO
OSC32_XO AO F2 Oscillator osc32_XO: Reserved RTC_VDDIO
RTC_VDD P E3 - RTC_VDD: 1.0V power for RTC -
RTC_VDDIO P G1 - RTC_VDDIO: 3.3V power for RTC -
NOTES:
1 All GPIO are programmable with multi-voltage (1.8V, 2.5V, 2.8V. 3.0V, 3.3V) general purpose,
bi-directional I/O buffer with a selectable LVCMOS input or LVCMOS Schmitt trigger input and
programmable pull-up / pull-down. In the full-drive mode, this buffer can operate in excess of
100MHz frequency with 15pF external load and 125 MHz with 10pF load, but actual frequency is
load and system dependent. A maximum of 200 MHz can be achieved under small capacitive
loads.
2 The meaning of phases in IO cell characteristics are:
 8/16mA out: The IO cell’s output driving strength is about 8/16mA.
20
 Pull-up: The IO cell contains a pull-up resistor and fixed pull up.
 Pull-down: The IO cell contains a pull-down resistor and fixed pull down.
 Pullup-rst: The IO cell during reset and after the pull up function is enabled.
 Pulldown-rst: The IO cell during reset and after the pull down function is enabled.
 Schmitt: The IO cell is Schmitt trigger input and fixed.
 Schmitt-rst: The IO cell during reset and after the Schmitt trigger input function is enabled.
 Slew-rate-rst: The IO cell during reset and after the slew-rate function select fast mode.
3 *: This pin has GPIO function as group A bit 30, but only input/interrupt function.
21
Electrical Specifications
3 Electrical Specifications
3.1 Absolute Maximum Ratings
The absolute maximum ratings for the processors are listed in Table 3-1. Do not exceed these
parameters or the part may be damaged permanently. Operation at absolute maximum ratings is not
guaranteed.
Table 3-1 Absolute Maximum Ratings
Parameter Min Max Unit

Storage Temperature -65 150 C
Operation Temperature -20 70 C
VDDMEM power supplies voltage -0.1 1.98 V
DDRVDD power supplies voltage -0.1 1.98 V
DDR_PLLVCCD power supplies voltage -0.1 1.1 V
DDR_PLLVCCA power supplies voltage -0.1 1.98 V
VDDIO0 power supplies voltage -0.5 1.98 V
VDD power supplies voltage -0.2 1.1 V
PLL_VDDA power supplies voltage -0.1 1.98 V
AVDEFUSE power supplies voltage -0.1 1.65 V
RTC_VDD power supplies voltage -0.5 1.155 V
RTC_VDDIO power supplies voltage -0.5 3.63 V
USB_VCC33 power supplies voltage -0.1 3.63 V
SADC_AVDD power supplies voltage -0.1 1.98 V
CODEC_AVDD power supplies voltage -0.1 1.98 V
MAC_VDDA power supplies voltage -0.1 1.1 V
MAC_VDDHV power supplies voltage -0.1 1.98 V
Maximum ESD stress voltage, Human Body Model; Any pin to any
supply pin, either polarity, or Any pin to all non-supply pins - 2000 V
together, either polarity. Three stresses maximum.
3.2 Recommended operating conditions

Table 3-2 Recommended operating conditions for power supplies
Symbol Description Min Typical Max Unit

VDDMEM VDDMEM voltage for SSTL18 (DDR2) 1.62 1.8 1.98 V
22
DDRVDD DDR PHY power supplies voltage 1.62 1.8 1.98 V

DDR_PLLVCCD DDR PLL power supplies voltage 0.9 1.0 1.1 V
DDR_PLLVCCA DDR PLL power supplies voltage 1.62 1.8 1.98 V
VDDIO0 GPIO power domain 0 supplies voltage 1.62 1.8 1.98 V
VDD VDD core supplies voltage 0.9 1.0 1.1 V
PLL_VDDA APLL, MPLL and VPLL analog voltage 1.62 1.8 1.98 V
AVDEFUSE EFUSE program supplies voltage 1.35 1.5 1.65 V
RTC_VDD RTC core supplies voltage 0.72 1.0 1.155 V
RTC_VDDIO RTC IO supplies voltage 1.35 3.3 3.63 V
USB_VCC33 USB PHY VCCA3P3 analog voltage 3.0 3.3 3.6 V
USB_VCC18 USB PHY VCC18 analog voltage 1.62 1.8 1.98 V
USB_VCC10 USB PHY VCCCORE1P0 voltage 0.9 1.0 1.1 V
SADC_AVDD SAR-ADC analog voltage 1.62 1.8 1.98 V
CODEC_AVDD CODEC analog voltage 1.62 1.8 1.98 V
MAC_VDDA MAC PHY analog voltage 0.9 1.0 1.1 V
MAC_VDDHV MAC PHY analog voltage 1.62 1.8 1.98 V
Table 3-3 Recommended operating conditions for VDDIO/VDDIO_D/RTC_VDDIO supplied pins
Symbol Parameter Min Typical Max Unit

VIH18 Input high voltage for 1.8V I/O application *0.65 - +0.3 V
VIL18 Input low voltage for 1.8V I/O application -0.3 - *0.35 V
VIH25 Input high voltage for 2.5V I/O application 1.7 - +0.3 V
VIL25 Input low voltage for 2.5V I/O application -0.3 - 0.7 V
VIH33 Input high voltage for 3.3V I/O application 2 - +0.3 V
VIL33 Input low voltage for 3.3V I/O application -0.3 - 0.8 V
Table 3-4 Recommended operating conditions for others
Symbol Description Min Typical Max Unit

TA Ambient temperature -40 25 +125 C
23
3.3 Audio codec
3.3.1 Microphone input
MICP
VOUT
MICN
MIC
There are two microphone input channels, MICP and MICN. They can be configured as differential
inputs by the microphone PGA(MIC).
The signal of microphone output should be input to AUDIO CODEC through DC-blocking capacitor, as
shown in following figure. The capacitance and input resistance form a high pass filter. For example,
when the gain of the MIC module is 20dB, the input resistance is 45KΩ and 0.1uF DC-blocking
capacitor is used, the lower cut-off frequency is:
1 1
f    35.4 Hz
2RC 2  45  103  0.1 10 6
The capacitance of the DC-blocking capacitor should be determined by the minimum input impedance
and application requirements.
MICP
C0
AUDIO
CODEC
C1
MICN
If the output of microphone is single-ended, the AUDIO ADC input should be connected as following
figure.
MICP MICP
C0 C0
AUDIO AUDIO
CODEC CODEC
C1 C1
MICN MICN
Microphone PGA has four gains to amplify the input signal, that is, 0dB, 20dB, 30dB and 40dB.
3.3.2 ALC
Automatic Level Control (ALC) function is included to adjust the signal level, which is input into ADC.
ALC will measure the signal magnitude and compare it to defined threshold. Then it will adjust the ALC
24
controlled PAG (ALC) gain according to the comparison result.
The programmable gain range of ALC controlled PAG is from -18dB to +28.5dB. The tuning step is
1.5dB.
3.3.3 Headphone output

Audio codec DAC output can drive 16Ω or 32Ω headphone load through DC-blocking capacitor.
In the configuration using DC-blocking capacitor, shown in following figure, the headphone ground is
connected to the real ground. The capacitance and the load resistance determine the lower cut-off
frequency. For instance, if 16Ωheadphone and 100uF DC-blocking capacitor are used, the lower
cut-off frequency is
1 1
f    99.5Hz
2RC 2  16  100  10 6
The DC-blocking capacitor can be increased to lower the cut-off frequency for better bass response.
HPOUT
Audio
DAC
AGND
The headphone driver chooses DAC output as input. It has a gain rang from -39dB to +6dB with a
tuning step of 1.5dB.
3.3.4 Microphone bias

Microphone bias output is used to bias external microphones. The bias voltage can varies from
0.8*CODEC_AVDD to 0.975* CODEC_AVDD with a step of 0.025* CODEC_AVDD.
3.4 MAC PHY

The transmitter is implemented using a Class-A current steering architecture. The transmitter drives a
scrambled MLT3 data into the 100Ω impedance. The transmitter implements a 6b DAC.
For the 100BaseT receive function, the MLT-3 from the cable is fed into PHY through a low-pass-filter,
and a 6b AD samples the incoming data. A programmable gain is implemented in the ADC. Baseline
wander is corrected using a small DAC.
The receiver receives the encoded stream from the cable, and the analog signal is filtered and
checked using a squelch circuit. The receiver recovers the clock and data to recreate the NRZI stream
25
after confirming that the data is valid encoded data. Polarity is identified and corrected as necessary
(observable through register interface). Then stream is deserialized ascent to the MAC interface at
2.5MHz.
The recommendations board circuit design is as shown below.

VCC_18
TXD+
TXD-
MAC PHY Transformer

RXD+
RXD-
Figure 3-1 Typical Product board circuit Design
3.5 Power On, Reset and BOOT
3.5.1 Power-On Timing

The external voltage regulator and other power-on devices must provide the X1021 processor with a
specific sequence of power and resets to ensure proper operation. Figure 3-2 shows this sequence
and Table 3-5 gives the timing parameters. Following are the name of the power.
 VDDRTC: RTC_VDDIO, RTC_VDD
 AVDAUD: CODEC_AVDD
 VDD10: all 1.0V power supplies, include VDD
 VDD: all other digital IO, include DDR power supplies: VDDMEM, VDDIO0,
VDDIO1,VDDIO2
 AVD: all other analog power supplies: SADC_AVDD, USB_VCC33, USB_VCC18,
USB_VCC10, PLL_VDDA, MAC_VDDA, MAC_VDDHV
Table 3-5 Power-On Timing Parameters
Symbol Parameter Min Max Unit

[1]
tR_VDDRTC VDDRTC rise time 0 5 ms
26
tR_VDD VDD rise time[1] 0 5 ms

Delay between VDDRTC arriving 50% (or 90%) to VDD33
tD_VDD 0 – ms
arriving 50% (or 90%)
tR_VDD10 VDD10 rise time[1] 0 5 ms
Delay between VDD arriving 50% (or 90%) to VDD10
tD_VDD10 –1 1 ms
tR_AVDAUD AVDAUD rise time[1] 0 5 ms
Delay between VDD10 arriving 50% (or 90%) to AVDAUD
tD_AVDAUD 0.01 1 ms
tR_AVD AVD rise time[1] 0 5 ms
tD_AVDA Delay between VDD arriving 50% to AVD arriving 50% -1 1 ms
[3]
tD_PPRST_ Delay between VDDAUD stable and PPRST_ deasserted TBD – ms[2]
NOTES:
 The power rise time is defined as 10% to 90%.
 The PPRST_ must be kept at least 100us. After PPRST_ is deasserted, the corresponding
chip reset will be extended at least 40ms.
tR_VDDRTC
VDDRTC
tD_VDD
tD_VDD
tR_VDD
VDD
tD_VDD10
tD_VDD11
tR_VDD10
VDD10
tD_AVDAUD
tD_AVDAUD
tR_AVDAUD
AVDAUD
tD_AVD
tR_AVD
AVD
tD_PPRST_
PPRST_
Figure 3-2 Power-On Timing Diagram
27
3.5.2 Reset procedure

There are 3 reset sources: 1. PPRST_ pin reset; 2. WDT timeout reset; and 3. hibernating reset when
exiting hibernating mode. After reset, program start from boot.
 PPRST_ pin reset.

This reset is trigged when PPRST_ pin is put to logic 0. It happens in power on RTC power
and RESET-KEY pressed to reset the chip from unknown dead state. The reset end time is
about 1M EXCLK cycles after rising edge of PPRST_.
 WDT reset.
This reset happens in case of WDT timeout. The reset keeps for about a few RTCLK cycles.
 Hibernating reset.
This reset happens in case of wakeup the main power from power down. The reset keeps for
about 1ms ~ 125ms programable, plus 1M EXCLK cycles, start after WKUP_ signal is
recognized.
After reset, all GPIO shared pins are put to GPIO input function and most of their internal pull-up/down
resistor are set to on, see “2.5Pin Description” for details. The PWRON is output 1. The oscillators are
on. The USB 2.0 OTG PHY and USB 1.1 PHY, the audio CODEC DAC/ADC, the SAR-ADCs is put in
suspend mode.
3.5.3 BOOT
The boot sequence of the X1021 is controlled by boot_sel[1:0]. The configuration is shown as follow:
Table 3-6 Boot Configuration of X1021
boot_sel[1:0] Boot method

MMC/SD boot @ MSC0 (MMC/SD use GPIO Port B.
00
MSC1 use GPIO Port C)
01 SFC boot @ CS4 (SPI boot)
10 NOR boot @ CS2 (just for FPGA testing)
11 USB boot @ USB 2.0 device, EXTCLK=24MHz
The boot procedure is showed in the following flow chart:

As shown in Figure 3-3, boot sequence Block Diagram. After reset, the boot program on the internal
boot ROM executes as follows:
1 Disable all interrupts and read boot_sel[1:0] to determine the boot method.
2 There 26KB backup reading failed, the 26KB backup at 128th, 256 th , …, and finally 1024th
page will be tried in consecutive order.
3 If it is boot from MMC/SD card at MSC0, its function pins MSC0_D0, MSC0_CLK,
MSC0_CMD are initialized, the boot program loads the 26KB code from MMC/SD card to
cache and jump to it. Only one data bus which is MSC0_D0 is used.
28
4 If it is boot from USB, a block of code will be received through USB cable connected with host
PC and be stored in cache. Then branch to this area in cache.
5 If it is boot from SPI nor/nand at SFC, its function pins SFC_CLK,SFC_CE, SFC_DR,SFC_DT,
SFC_WP,SFC_HOLD are initialized,the boot program loads the 12kB code from SPI
NAND/NOR flash to cache and jump to it.
6 If it is boot from NOR Flash, the boot program jump to nor and run directory.
When SFC boot start failure, the program in bootrom will go into MSC0 boot.
When MSC0 boot start failure, the program in bootrom will go into MSC1 boot，If it is boot from
MMC/SD card at MSC1, its function pins MSC1_D0, MSC1_CLK, MSC1_CMD are initialized, the boot
program loads the 26KB code from MMC/SD card to cache and jump to it. Only one data bus which is
MSC1_D0 is used.If MSC1 boot start failure, jump to USB boot.
Reset
N = 0
N = N +1
Enter
Y
Hibernate N> 3
mode
N
Check bootsel
01 00 10 11
MSC 0 NOR
SFC BOOT USB BOOT
BOOT BOOT
Y &&(N<5) Y &&(N < 1) Y

Y
FAIL? FAIL? FAIL? Time out?
N
Y &&(N ==1)
Y &&(N ==5)
MSC1 BOOT
Y &&(N < 1) Y &&(N ==1)
FAIL?
N N N N
Finish boot
Figure 3-3 Boot sequence diagram of X1021
29

X1021 Iot Application Processor: Data Sheet

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X1021 Iot Application Processor: Data Sheet

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X1021

IoT Application Processor

Release Date: Apr. 28, 2020

Copyright © 2005-2020 Ingenic Semiconductor Co. Ltd. All rights reserved.

Ingenic Semiconductor Co., Ltd.

Ingenic Headquarters, Zhongguancun Software Park,

2 Packaging and Pinout Information ................................................... 10

3 Electrical Specifications ................................................................... 22

3.3.1 Microphone input ........................................................................................................... 24

1.1 Block Diagram

Figure 1-1 X1021 Diagram

– 16kB data cache

1.2.3 Image post processor(IPU)

 Maximum output image size (pixel): 2048x2048

1.2.5 Video input

1.2.7 Memory Interface

1.2.8 System Functions

 One High Speed Synchronous serial interfaces (SFC)

 Two Normal Speed Synchronous serial interfaces (SSI0, SSI1)

– Programmable transfer order: MSB first or LSB first

 Three UARTs (UART0, UART1, UART2)

 Two MMC/SD/SDIO controllers (MSC0, MSC1)

 USB 2.0 OTG interface

On-The-Go supplement to the USB 2.0 specification

 Ethernet Media Access controller and interface

 Digital True Random Number Generator（DTRNG）

2 Packaging and Pinout Information

2.2 Solder Process

2.3 Moisture Sensitivity Level

2.4 X1021 Package

Figure 2-1 X1021 package outline drawing

X1021 Ball Assignment Ver1.4

SSI0_DT_P MSC1_D2_M MSC1_D0_M

DVP_MCLK_ DVP_HSYN DVP_PCLK_

SADC_VREF SA2_DVP_D CS1_DVP_D

SADC_AVD SD7_DVP_D SA0_DVP_D SA1_DVP_D

Figure 2-2 X1021 pin to ball assignment

2.5 Pin Description

2.5.1 Static Memory/DVP/I2C0

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

PA18 IO E12 8mA PA18: GPIO group A bit 18 VDDIO0

Pin Names IO Loc IO Cell Char. Pin Description Power

Table 2-7 Boot Select Pins(2)

Pin Names IO Loc IO Cell Char. Pin Description Power

2.5.7 Digital IO/core power/ground

Pin Names IO Loc IO Cell Char. Pin Description Power

Pin Names IO Loc IO Cell Char. Pin Description Power

2.5.8 DDR power/ground

Pin Names IO Loc IO Cell Char. Pin Description Power

2.5.9 Analog - USB

Pin Names IO Loc IO Cell Char. Pin Description Power