UNIT-4 COMBINATIONAL LOGIC DESIGN

DECODERS:
A decoder is a multiple-input, multiple-output logic circuit
that converts coded inputs into coded outputs, where the input
and output codes are different. The input code generally has
fewer bits than the output code, and there is a one-to one
mapping from input code words into output code words. In a
one-to-one mapping, each input code word produces a different
output code word.
The general structure of a decoder circuit is shown in
Figure 1. The enable inputs, if present, must be asserted for
the decoder to perform its normal mapping function.
Otherwise, the decoder maps all input code words into a single,
―disabled,‖ output code word.
The most commonly used output code is a 1-out-of-m code, which contains m bits, where one bit is asserted at
any time. Thus, in a 1-out-of-4 code with active-high outputs, the code words are 0001, 0010, 0100, and 1000.
With active-low outputs, the code words are 1110, 1101, 1011, and 0111.
BINARY DECODERS
The most common decoder circuit is an n-to-2n decoder or
binary decoder. Such a decoder has an n-bit binary input code
and a 1-out-of-2n output code. A binary decoder is used when
you need to activate exactly one of 2n outputs based on an n-
bit input value.
Table 1 is the truth table of a 2-to-4 decoder. The input code
word I1,I0 represents an integer in the range 0–3. The output
code word Y3,Y2,Y1,Y0 has Yi equal to 1 if and only if the
input code word is the binary representation of i and the
enable input EN is 1. If EN is 0, then all of the outputs are 0.
A gate-level circuit for the 2-to-4 decoder is shown in Figure 2
Each AND gate decodes one combination of the input code
word I1,I0.
74x138 3-to-8 Decoder
The 74x138 is a commercially
available MSI 3-to-8 decoder
whose gate-level circuit diagram
and symbol are shown in Figure
7; its truth table is given in Table.
Like the 74x139, the 74x138 has
active-low outputs, and it has
three enable inputs (G1, /G2A,
/G2B), all of which must be
asserted for the selected output to
be asserted.
The logic function of the
74X138 is straightforward—an
output is asserted if and only if the
decoder is enabled and the output
is selected.

Thus, we can easily write logic equations for an internal output

signal such as Y5 in terms of the internal input signals:

However, because of the inversion bubbles, we have the following relations between internal and external
signals:

Therefore, if we’re interested, we can write the following equation for the external output signal Y5_L in terms of
external input signals:

On the surface, this equation doesn’t resemble what you might expect for a decoder, since it is a logical sum
rather than a product. However, if you practice bubble-to-bubble logic design, you don’t have to worry
about this; you just give the output signal an active-low name and remember that it’s active low when you
connect it to other inputs.
The 74x139 Dual 2-to-4 Decoder:
Two independent and identical 2-to-4 decoders are contained in a single MSI part, the 74x139. The
gate-level circuit diagram for this IC is shown in Figure 5.
1. The outputs and the enable input of the ’139 are active-low.
2. Most MSI decoders were originally designed with active-low outputs, since TTL inverting gates are
generally faster than non inverting ones.
3. ’139 has extra inverters on its select inputs. Without these inverters, each select input would present three AC
or DC loads instead of one, consuming much more of the fanout budget of the device that drives it.

In this case, the assignment of the generic function to one half or the other of a particular ’139 package can be
deferred until the schematic is completed Table 5-6 is the truth table for a 74x139-type decoder.
CASCADING BINARY DECODERS
Multiple binary decoders can be used to decode larger code words. Figure 5-38 shows how two 3-to-8 decoders
can be combined to make a 4-to-16 decoder. The availability of both active-high and active-low enable inputs on
the 74x138 makes it possible to enable one or the other directly based on the state of the most significant input bit.
The top decoder (U1) is enabled when N3 is 0, and the bottom one (U2) is enabled when N3 is 1.
EXAMPLE 1: DESIGN 5 TO 32 DECODER USING 74X138
EXAMPLE VHDL PROGRAM FOR DECODER USING DIFFERENT MODELLING STYLE
SEVEN-SEGMENT DECODERS
Look at your wrist and you’ll probably see a seven-segment display. This type of display, which normally uses
light-emitting diodes (LEDs) or liquid-crystal display (LCD) elements, is used in watches, calculators, and
instruments to display decimal data.
A seven-segment decoder has 4-bit BCD as its input code and the
"sevenencoder 2n-to-n encoder binary encoder segment code," which is . graphically
depicted in Figure 6-44(b ), as its output code. Table 6-26 is a Verilog program for a
seven-segment decoder with 4-bit BCD input A-D (D being the MSB), active-high
enable input EN, and segment outputs SEGA-SEGG. Note the use of concatenation
and an auxiliary variable SEGS to make the program more readable. The program can
be easily modified for different encodings and features, for example, to add "tails" to
digits 6 and 9 (Exercise 6.47) or to display hexadecimal digits A-F instead of treating
these input combinations as "don't cares"
ENCODERS
A decoder’s output code normally has more bits than its input code. If the device’s output code has fewer bits than
the input code, the device is usually called an encoder. Probably the simplest encoder to build is a 2n-to-n or binary
encoder. As shown in Figure 6-45(a), it has just the opposite function as a binary decoder— its input code is the 1-
out-of-2n code and its output code is n-bit binary.
The corresponding logic circuit is shown in (b). In general, a 2n-to-n encoder can be built from n 2n 1-input OR
gates. Bit i of the input code is connected to OR gate j if bit j in the binary representation of i is 1.

PRIORITY ENCODERS
The 1-out-of-2n coded outputs of an n-bit binary decoder are generally
used to control a set of 2n devices, where at most one device is supposed to be
active at any time. Conversely, consider a system with 2n inputs, each of
which indicates a request for service. This structure is often found in
microprocessor input/output subsystems, where the inputs might be interrupt
requests.
the encoding device produces the number of the highest-priority requestor. Such a device is called a
priority encoder. Input I7 has the highest priority. Outputs A2–A0 contain the number of the highest-priority
asserted input, if any. The IDLE output is asserted if no inputs are asserted.
In order to write logic equations for the priority encoder’s outputs, we
first define eight intermediate variables H0–H7, such that Hi is 1 if and only
if Ii is the highest priority 1 input: Using these signals, the equations for the A2–
A0 outputs are similar to the ones for a simple binary encoder:

THE 74X148 PRIORITY ENCODER

The 74x148 is a commercially available, MSI 8-input priority encoder it has an
enable input, EI_L, that must be asserted for any of its outputs to be asserted. The
complete truth table is given in Table 5-22. Instead of an IDLE output, the ’148
has a GS_L output that is asserted when the device is enabled and one or more
of the request inputs is asserted. The manufacturer calls this “Group Select”
but it’s easier to remember as “Got Something” The EO_L signal is an enable
output designed to be connected to the EI_L input of another ’148 that handles
lower-priority requests. /EO is asserted if EI_L is asserted but no request input is
asserted; thus, a lower-priority ’148 may be enabled.

Figure 6-49 shows how four 74x148s can be connected in this way to accept 32
request inputs and produce a 5-bit output, RA4-RAO, indicating the highest-
priority requestor. Since the A2-AO outputs of at most one' 148 will be enabled at
any time, the outputs of
the individual' 148s can
be ORed to produce
RA2-RAO. Likewise,
the individual GS_L
outputs can be combined
in a 4-to-2 encoder to
produce RA4 and RA3.
The RGS output is
asserted if any GS output
is asserted.
PROGRAM FOR ENCODER

THREE-STATE DEVICES
Three-State Buffers
The most basic three-state device is a three-state buffer, often called a three-state driver.
The logic symbols for four physically different three-state buffers are shown in Figure
The basic symbol is that of a noninverting buffer (a, b) or an inverter (c, d). The extra signal at the top of the symbol
is a three-state enable input, which may be active high (a, c) or active low (b, d). When the enable input is asserted,
the device behaves like an ordinary buffer or inverter.
When the enable input is negated, the device output
―floats‖; that is, it goes to a high impedance (Hi-Z),
disconnected state and functionally behaves as if it
weren’t even there.
Both enable inputs, G1_L and G2_L, must be
asserted to enable the device’s three-state outputs.
The little rectangular symbols inside the buffer symbols
indicate hysteresis, an electrical characteristic of the
inputs that improves noise immunity. The 74x541
inputs typically have 0.4 volts of hysteresis.

Following figure shows the logic diagram and symbol

for a 74x245 octal three-state transceiver. The DIR
input determines the direction 74x245 of transfer, from
A to B (DIR= 1) or from B to A (DIR= 0). The three-
state buffer for the selected direction is enabled only if
G_L is asserted.
MULTIPLEXERS
A multiplexer is a digital switch—it connects data from one of n sources to
its output. Figure 5-61(a) shows the inputs and outputs of an n-input, b-bit
multiplexer. There are n sources of data, each of which is b bits wide. A
multiplexer is often called a mux for short. A multiplexer can use addressing
bits to select one of several input bits to be the output. A selector chooses a
single data input and passes it to the mux output.it has one output
selected at a time.
Figure shows a switch circuit that is roughly equivalent to the multiplexer.
However, unlike a mechanical switch, a multiplexer is a unidirectional
device: information flows only from inputs (on the left) to outputs (on the
right. Multiplexers are obviously useful devices in any application in which data must be switched from
multiple sources to a destination. A common application in computers is the multiplexer between the
processor’s registers and its arithmetic logic unit (ALU). For example, consider a 16-bit processor in which
each instruction has a 3-bit field that specifies one of eight registers to use. This 3-bit field is connected
to the select inputs of an 8-input, 16-bit multiplexer. The multiplexer’s data inputs are connected to the eight
registers, and its data outputs are connected to the ALU to execute the instruction using the selected register.
STANDARD MSI MULTIPLEXERS
The sizes of commercially available MSI multiplexers are limited by the number of pins available in an
inexpensive IC package. Commonly used muxes come in 16-pin packages. Shown in fig which selects
among eight 1-bit inputs. The select inputs are named C, B, and A, where C is most significant numerically.
The enable input EN_L is active low; both active-high (Y) and active-low (Y_L) versions of the output are
provided.
At the other extreme of muxes in 16-pin packages, we have the 74x157, shown in Figure, which selects between
two 4-bit inputs. Just to confuse things, the manufacturer has named the select input S and the active-low enable
input G_L. Also note that the data sources are named A and B
EXPANDING MULTIPLEXERS
Seldom does the size of an MSI multiplexer match the characteristics of the problem at hand. For example,
we suggested earlier that an 8-input, 16-bit multiplexer might be used in the design of a computer processor. This
function could be performed by 16 74x151 8-input, 1-bit multiplexers or equivalent ASIC cells, each handling one
bit of all the inputs and the output. The processor’s 3-bit register-select field would be connected to the A,
B, and C inputs of all 16 muxes, so they would all select the same register source at any given time.
COMPARATORS
A circuit that compares comparator two binary words and indicates whether they are equal is called a
comparator. Some comparators interpret their input words as signed or unsigned numbers and also indicate an
arithmetic relationship (greater or less than) between the words. These devices are often called magnitude
comparators.
STANDARD MSI MAGNITUDE COMPARATORS

Comparator applications are common enough that magnitude

comparators have been developed commercially as MSI parts. The 74x85 is a
4-bit comparator with the logic symbol shown in Figure 6-78. It provides a
greater-than output (AGTBOUT) and a less-than output (AL TBOUT) as well
as an equal output (AEQBOUT). The '85 also has cascading inputs (AGTBIN,
ALTBIN, AEQBIN) for combining multiple '85s to create comparators for
more than four bits. Both the cascading inputs and the outputs are arranged in a
l-out-of-3 code, since in normal operation exactly one input and one output
should be asserted.

Several 8-bit MSI comparators are also available. The simplest of these is the 74x682,
whose logic symbol is shown in Figure 6-80 and whose internal logic diagram is shown in Figure
6-82 on the next page. The top half of the circuit checks the two 8-bit input words for equality.
Each XNOR-gate output is asserted if its inputs are equal, and the PEQQ_L output is asserted if
all eight input-bit pairs are equal. The bottom half of the circuit compares the input words
arithmetically and asserts PGTQ_L if P[7--0] >
ITERATIVE COMPARATOR CIRCUITS
1. Set EQ0 to 1 and set i to 0.
2. If EQi is 1 and Xi and Yi are equal, set EQi +1 to 1. Else set EQi+1 to 0.
3. Increment i.
4. If i < n, go to step 2.
24 BIT GROUP RIPPLE ADDER USING 74X283
The 181 's M input selects between arithmetic and logical operations. When M = 1, logical operations are selected, and each
output Fi is a function only of the corresponding data inputs, Ai and Bi. The S3-SO inputs select a particular logical operation;
any of the 16 different combinational logic functions on two variables may be selected.
When M = 0, arithmetic operations are selected, carries propagate between the stages, and CIN is used as a carry input to the
least significant stage.
 Two other MSI ALUs, the 74x381 and 74x382 shown in Figure 6-91, encode their select inputs more compactly, and
provide only eight different but useful functions, as detailed in Table 6-71. The only difference between the '381 and '382 is
that one provides group-carry-lookahead outputs (which we explain next), while the other provides ripple carry and
overflow outputs.

PARITY CIRCUITS:
This is called an odd-parity circuit, because its output is 1 if an odd number of its inputs are 1. The circuit in (b) is also an
oddparity circuit, but it's faster because its gates are arranged in a treelike structure. If the output of either circuit is
inverted, we get an even-parity circuit, whose output is 1 if an even number of its inputs are 1.

74X280 9-BIT PARITY GENERATOR

To detect errors in the transmission and storage of data. In an evenparity code, the parity bit is chosen so that the total
number of 1 bits in a code word is even. Parity circuits like the 74x280 are used both to generate the correct value of the
parity bit when a code word is stored or transmitted and to check the parity bit when a code word is retrieved or received.
APPLICATION: ERROR DETECTOR
XOR GATE
Exclusive-OR and Exclusive-NOR Gates An Exclusive-OR (XOR) gate is a 2-input gate whose output is I if exactly one of
its inputs is 1. Stated another way, an XOR gate produces a I output if its inputs are different. An Exclusive NOR (XNOR)
or Equivalence gate is just the opposite-it produces a 1 output if its inputs are the same. A truth table for these functions is
shown in Table 6-54.
GROUP-CARRY LOOKAHEAD
The' 181 and '381 provide group-carry-lookahead outputs that allow multiple ALUs to be cascaded without rippling carries
between 4-bit groups. Like the 74x283, the ALUs use carry lookahead to produce carries internally.
Gray to Binary Conversion VHDL source code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gray2binary is
Port ( g : in STD_LOGIC_VECTOR (3 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0));
end gray2binary;

architecture Behavioral of gray2binary is

begin
b(3)<= g(3);
b(2)<= g(3) xor g(2);
b(1)<= g(3) xor g(2) xor g(1);
b(0)<= g(3) xor g(2) xor g(1) xor g(0);
end behavioral;
Binary to Gray Conversion VHDL source code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BinarytoGray is
port( b: in std_logic_vector(3 downto 0); --binary
g: out std_logic_vector(3 downto 0)); --gray
end BinarytoGray;

architecture behavioral of BinarytoGray is

begin
b(3)<= g(3);
b(2)<= g(3) xor g(2);
b(1)<= g(2) xor g(1);
b(0)<= g(1) xor g(0);
end behavioral;