Hi3716M V430

Hi3716M V430 Cable HD Chip Brief Data Sheet

Key Specifications
CPU Graphics and Display Processing (Imprex 2.0
 High-performance ARM Cortex-A7 processor Processing Engine)
 Built-in I-cache, D-cache, and L2 cache
 Hardware TDE
 Hardware Java acceleration
 3-layer OSD
 Floating-point coprocessor
 Two video layers
Memory Control Interfaces  16-bit and 32-bit color depth
 DDR3/DDR3L interface  Full-hardware anti-aliasing and anti-flicker
− Maximum capacity of 512 MB for an external DDR  IE, NR, and CCS
SDRAM or of 128 MB/256 MB for a built-in DDR  DEI
SDRAM Audio and Video Interfaces
− 16-bit data width
 PAL, NTSC, and SECAM standard outputs, and forcible
 A SPI NOR flash/SPI NAND flash, a parallel SLC NAND
standard conversion
flash, or a SPI NOR flash+a parallel SLC NAND flash
 Aspect ratio of 4:3 or 16:9, forcible aspect ratio
Video Decoding (HiVXE 2.0 Processing Engine) conversion, and free scaling
 H.265 Main/Main 10@Level 4.1 high-tier  1080p50(60)/1080i/720p/576p/576i/480p/480i outputs
 H.264 BP/MP/HP@Level 4.2; MVC  HD and SD output for the same source
 MPEG-1  Color gamut compliant with the xvYCC (IEC 61966-2-4)
 MPEG-2 SP@ML and MP@HL standard
 MPEG-4 SP@Levels 0–3, ASP@Levels 0–5, GMC, and  HDMI 1.4b with HDCP1.4
MPEG-4 short header format (H.263 baseline)  Analog video interfaces
 AVS baseline@Level 6.0 and AVS+ − One CVBS interface
− One built-in VDAC
 VC-1 SP@ML, MP@HL, and AP@Levels 0–3
− VBI
 VP6/VP8
 Audio interface
 1-channel 1080p@60 fps decoding
− Audio-left and audio-right channels
Image Decoding − S/PDIF interface
 JPEG decoding, supporting at most 64 MP − One built-in ADAC
− Output voltage swing up to 2 Vrms
Audio Decoding
 MPEG L1/L2 Peripheral Interfaces
 Dolby Digital/Dolby Digital Plus decoder-converter  Two USB 2.0 host interfaces (integrated with the PHY)
 AAC-LC and HE-AAC V1/V2 decoding  One 10/100 Mbit/s adaptive Ethernet interface with an
integrated FE PHY
 Downmixing, resampling, and automatic volume control
 One UART interface
TS Demultiplexing/PVR
 Two SCIs that support T0/T1/T14 protocols, with one SCI
 One built-in DVB-C QAM demodulator, compliant with
supporting 5 V and 3 V cards
J.83 A/B/C
 One IR receiver
 Up to 4-channel TS input, or 3-channel TS+1-channel
 One LED and keypad control interface
tuner input
 Three I2C interfaces
 Up to 1-channel TS output
 Multiple groups of GPIO interfaces
 Up to 96 hardware PID channels
 Recording of scrambled and non-scrambled streams Others
 Faster bootup time
Security Processing
 Integrated dedicated standby processor, with the chip
 Advanced CA feature
standby power consumption less than 30 mW
 OTP
 TFBGA package
 AES, DES, and 3DES data encryption and decryption
 2-layer or 4-layer PCB routing

Copyright © HiSilicon (Shanghai) Technologies Co., Ltd. 2018. All rights reserved.
New R&D Center, 49 Wuhe Road, Bantian, Longgang District, Shenzhen 518129 P. R. China www.hisilicon.com
Issue: 00B03 1 Date: 2018-10-18
 Hi3716M V430
Hi3716M V430 Cable HD Chip Brief Data Sheet
Functional Block Diagram

Tuner+Demod D VDAC x 1 CVBS

E Imprex2.0
M Engine
Cortex-A7 Video and
U HDMI TX HDMI output
Tuner Demod L1 cache Display processor
X
L2 cache

TDE Audio DAC Audio output

IR

BootROM/OTP S/PDIF x 1 S/PDIF

I2C x 3 HiVXE2.0 Engine BootRAM
Video decoder
(1x1080p60,10-bit) SCI x 2 SCI
UART AVS+/HEVC/H.264
SEC SUBSYS
USB 2.0 x 2 USB 2.0 device
SPI NOR/SPI NAND/SPI/SPI
NAND Flash NAND DDRC DDR3/3L Low-power
16-bit (optional) processor FEPHY RJ45
PLL

OSC DDR3/3L
(optional)

Hi3716M V430 is an FHD HEVC cost-effective STB chip solution launched by HiSilicon. It integrates the high-performance
Cortex-A7 processor and TDE, and supports HD video decoding in various formats such as H.265, H.264, AVS+, MPEG-2,
MPEG-4, VC-1, VP6, and VP8, and Dolby audio processing. Hi3716M V430 also provides flexible connection schemes with various
peripheral interfaces such as one Ethernet interface and two USB 2.0 interfaces. It delivers the industry's best user experience in
stream compatibility, smoothness and picture quality of live video playback, and STB performance.

NOTE
Dolby, mentioned in this document, is a registered trademark of Dolby Laboratories, Inc. Any parties intending to
use the Dolby trademark must obtain permission from Dolby Laboratories, Inc.

Acronyms and Abbreviations

3DES Triple Data Encryption Algorithm
AAC-LC advanced audio coding low complexity
ADAC audio digital-to-analog converter
AES Advanced Encryption Standard
AMR-NB adaptive multi-rate narrowband
AMR-WB adaptive multi-rate wideband
APE Monkey's Audio
AVS Audio Video Standard/adaptive voltage scaling
CA conditional access
CCS cross-color suppression
CVBS composite video broadcast signal
DD Dolby Digital
DDR double data rate
DEI de-interlacing
DES Data Encryption Standard
DVB Digital Video Broadcasting
DVB-T Digital Video Broadcasting-Terrestrial

Copyright © HiSilicon (Shanghai) Technologies Co., Ltd. 2018. All rights reserved.
New R&D Center, 49 Wuhe Road, Bantian, Longgang District, Shenzhen 518129 P. R. China www.hisilicon.com
Issue: 00B03 2 Date: 2018-10-18
 Hi3716M V430
Hi3716M V430 Cable HD Chip Brief Data Sheet
eMMC embedded multimedia card
FE fast Ethernet
FHD full high definition
FLAC free lossless audio codec
GMC global motion compensation
GPIO general-purpose input/output
HD high definition
HDCP High-bandwidth Digital Content Protection
HDMI high definition multimedia interface
HE-AAC high-efficiency advanced audio coding
HEVC high efficiency video coding
IE image enhancement
IF intermediate frequency
I2C inter-integrated circuit
I2S inter-IC sound
IR infrared
JPEG Joint Photographic Experts Group
LED light emitting diode
MP megapixel
MPEG Moving Picture Experts Group
MVC multiview video coding
NR noise reduction
NTSC National Television System Committee
OSD on-screen display
OTP one-time programmable
PAL phase alternating line
PCB printed circuit board
PHY Port Physical Layer
PID packet identifier
QAM quadrature amplitude modulation
SCI smart card interface
SD standard definition
SDIO secure digital input/output
SDRAM synchronous dynamic random access memory
SECAM sequential color with memory
SLC single-level cell
S/PDIF Sony/Philips Digital Interface Format
SPI serial peripheral interface
STB set-top box
TDE two-dimensional engine
TFBGA thin & fine ball grid array
TS transport stream
UART universal asynchronous receiver transmitter
VBI vertical blanking interval
VDAC video digital-to-analog converter

Copyright © HiSilicon (Shanghai) Technologies Co., Ltd. 2018. All rights reserved.
New R&D Center, 49 Wuhe Road, Bantian, Longgang District, Shenzhen 518129 P. R. China www.hisilicon.com
Issue: 00B03 3 Date: 2018-10-18