IRF6644
IRF6644
IRF6644
Applicable DirectFET® Outline and Substrate Outline (see pg. 13, 14 for details)
SH SJ SP MZ MN
Description
The IRF6644PbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET® packaging to achieve the
lowest on-state resistance in a package that has a footprint of a SO-8 and only 0.7 mm profile. The DirectFET® package is compatible with
existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering tech-
niques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET® package allows
dual sided cooling to maximize thermal transfer in power systems improving previous best thermal resistance by 80%.
The IRF6644PbF is optimized for primary side bridge topologies in isolated DC-DC applications, for wide range universal input Telecom
applications (36V-75V), and for secondary side synchronous rectification in regulated DC-DC topologies. The reduced total losses in the
device coupled with the high level of thermal performance enables high efficiency and low temperatures, which are key for system reliabil-
ity improvements, and makes the device ideal for high performance isolated DC-DC converters.
60 80
RDS (on), Drain-to -Source On Resistance (m)
RDS(on) , Drain-to -Source On Resistance (m)
55 ID = 34A
70 VGS = 7.0V
50 VGS = 8.0V
45 60 VGS = 10V
VGS = 12V
40
50
35
30 40
25 TJ = 125°C
30
20
15 TJ = 25°C 20
10
10
5
0 0
2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100 120 140 160
VGS, Gate -to -Source Voltage (V) ID , Drain Current (A)
Figure 1 Typical On-Resistance vs. Gate Voltage Figure 2 Typical On-Resistance vs. Drain Current
Final Datasheet Please read the important Notice and Warnings at the end of this document V2.0
www.infineon.com 2017-03-28
IR MOSFET
IRF6644PbF
Table of Contents
Table of Contents
Applications …..………………………………………………………………………...……………..……………1
Description ….……………………………………………………………………………………………………1
Table of Contents ….………………………………………………………………………………………………...2
1 Parameters ………………………………………………………………………………………………3
2 Maximum ratings, Thermal, and Avalanche characteristics ………………………………………4
3 Electrical characteristics ………………………………………………………………………………5
4 Electrical characteristic diagrams ……………………………………………………………………6
Package Information ………………………………………………………………………………………………13
Qualification Information ……………………………………………………………………………………………16
Revision History …………………………………………………………………………………………..…………17
1 Parameters
Notes:
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET™ Website.
Surface mounted on 1 in. square Cu board, steady state.
TC measured with thermocouple mounted to top (Drain) of part.
Repetitive rating; pulse width limited by max. junction temperature.
(Starting TJ = 25°C, L = 0.15mH, RG = 50, IAS = 34A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Used double sided cooling, mounting pad with large heat sink.
Mounted on minimum footprint full size board with metalized back and with small clip heat sink.
R is measured at TJ of approximately 90°C.
3 Electrical characteristics
Table 5 Static characteristics
Values
Parameter Symbol Conditions Unit
Min. Typ. Max.
Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = 250µA 100 - - V
Breakdown Voltage Temp. Coefficient V(BR)DSS/TJ Reference to 25°C, ID = 1mA - 0.1 - V/°C
Static Drain-to-Source On-Resistance RDS(on) VGS = 10V, ID = 34A - 10.3 13 m
Gate Threshold Voltage VGS(th) 2.8 3.7 4.8 V
VDS = VGS, ID = 150µA
Gate Threshold Voltage Temp. Coefficient VGS(th)/TJ - -11 - mV°/C
VDS = 100V, VGS = 0V - - 20
Drain-to-Source Leakage Current IDSS µA
VDS = 80V, VGS = 0V, TJ = 125°C 250
IGSS VGS = 20V - - 100
Gate-to-Source Forward Leakage nA
IGSS VGS = -20V - - -100
Gate Resistance RG - - 1.6 -
IS - - 57
(Body Diode) showing the
G A
Pulsed Source Current integral reverse
ISM - - 228
(Body Diode) p-n junction diode.
S
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
10
5.0V
5.0V 10
1
1000 2.4
ID = 34A
RDS(on) , Drain-to-Source On Resistance
VGS = 10V
2.0
ID , Drain-to-Source Current (A)
100
1.6
(Normalized)
TJ = 150°C
TJ = 25°C
1.2
10
0.8
VDS = 50V
60µs PULSE WIDTH
1 0.4
2 3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V) T J , Junction Temperature (°C)
100000 14
VGS = 0V, f = 1 MHZ
ID = 34A
Ciss = Cgs + Cgd, Cds SHORTED
12 VDS = 80V
Crss = Cgd
Ciss 8
1000 Coss
6
4
100 Crss
10 0
0.1 1 10 100 0 5 10 15 20 25 30 35 40
VDS , Drain-to-Source Voltage (V) QG , Total Gate Charge (nC)
Figure 7 Typical Capacitance vs. Drain-to-Source Figure 8 Typical Gate Charge vs. Gate-to-Source
Voltage Voltage
1000
100
ID , Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
100 100µsec
1msec
T J = 150°C T J = 25°C
10
10 OPERATION IN THIS AREA
LIMITED BY R DS(on)
1 1
10msec
Tc = 25°C
VGS = 0V Tj = 150°C DC
Single Pulse
0.1 0.1
0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 100
VSD , Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Figure 9 Typical Source-Drain Diode Forward Figure 10 Maximum Safe Operating Area
Voltage
60 5.0
50 4.5
40
3.5
30
3.0
20 ID = 150µA
2.5
ID = 250µA
10 ID = 1.0mA
2.0
ID = 1.0A
0 1.5
25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150
TC , Case Temperature (°C) T J , Temperature ( °C )
Figure 11 Maximum Drain Current vs. Case Figure 12 Typical Threshold Voltage vs. Junction
Temperature Temperature
400
ID
E AS , Single Pulse Avalanche Energy (mJ)
350
TOP 4.2A
8.9A
300 BOTTOM 34A
250
200
150
100
50
0
25 50 75 100 125 150
Starting T J , Junction Temperature (°C)
100
Single Pulse Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming DTj = 125°C and
Tstart =25°C (Single Pulse)
0.01
Avalanche Current (A)
10
0.05
0.10
10
Thermal Response ( Z thJC ) °C/W
1 D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE Notes:
( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t 1 , Rectangular Pulse Duration (sec)
Figure 16 Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET™ Power MOSFETs
Figure 17a Gate Charge Test Circuit Figure 17b Gate Charge Waveform
Figure 18a Unclamped Inductive Test Circuit Figure 18b Unclamped Inductive Waveforms
Figure 19a Switching Time Test Circuit Figure 19b Switching Time Waveforms
5 Package Information
DirectFET™ Board Footprint, MN Outline
Please see DirectFET™ application note AN-1035 for all details regarding the assembly of DirectFET™.
This includes all recommendations for stencil and substrate designs.
Note: For the most current drawing please refer to website at : www.irf.com/package/
Please see DirectFET™ application note AN-1035 for all details regarding the assembly of DirectFET™.
This includes all recommendations for stencil and substrate designs.
Note: For the most current drawing please refer to website at : www.irf.com/package/
Note: For the most current drawing please refer to website at : www.irf.com/package/
6 Qualification Information
Qualification Information
Revision History
Major changes since the last revision
All page 2.0 2017-03-28 This is Unique datasheet Project with Id Ratings based on RthJC.
The datasheet is converted in New Infineon Template.
Other Trademarks
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Edition 2015-05-06 The information given in this document shall in no delivery terms and conditions and prices please
Published by event be regarded as a guarantee of conditions or contact your nearest Infineon Technologies office
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