Computer Network 17-21
Computer Network 17-21
Computer Network 17-21
Computer Network
Presented By
Dr. S.Kanungo
Asynchronous and Synchronous Transmission
• Timing problems require a mechanism to synchronize
the transmitter and receiver
• Two solutions
➢ Asynchronous
➢ Synchronous
• Data transmission and modes
Asynchronous
• Data transmitted one character at a time
• Also called start and stop transmission
• Synchronize without utilizing a clock
• Data flows in a Half Duplex mode
• We send 1 start bit (0) at the beginning and 1 or more stop bits
(1s) at the end of each byte. There may be a gap between each
byte.
• Asynchronous at the byte level; but the bits are still
synchronized; their durations are the same
• Synchronous
➢Used for sending huge amount of data
➢Allows connected devices to interact in real time
➢High data transfer speed
➢ Full Duplex transmission using frames or blocks
➢ More efficient (lower overhead) than asynchronous
➢ We send bits one after another without start or stop bits
or gaps. It is the responsibility of the receiver to group the
bits.
• Burst errors
– Length B
– Contiguous sequence of B bits in which first, last and
any number of intermediate bits in error
– Impulse noise
– Fading in wireless
– Effect greater at higher data rates
Error Detection Process (Figure 6.2)
Error Detection
• Additional bits added by transmitter for error
detection code
• Parity check
– Value of parity bit is such that character has even (even
parity – used for synchronous transmission) or odd
(odd parity – used for asynchronous transmission)
number of ones
– Even number of bit errors goes undetected
1The least significant bit of a character is transmitted first, and that the
parity bit is the most significant
• Two-dimensional Parity Check
- The string of data bits to be checked is arranged in a 2-D array
- It is more robust than the single parity bit
- Any odd number of bit errors detected
- The error can be determined to be at the intersection of
that row and column
- It is possible to not only detect the error but also correct the bit
error
• Example: A string of 20 data bits arranged in a 4×5 array
Fig. 6.3 2D Even Parity Scheme
➢ Define:
T = n-bit frame to be transmitted; D = k-bit block of data, or message, the first k bits of T
F = (n - k)-bit FCS, the last (n - k) bits of T; P = pattern of n - k + 1 bits; this is the
predetermined divisor; We would like T/P to have no remainder:
Coding for detection and correction of content errors
• Coding is the process of adding check bits
• The block of data bits to which check bits are added is
called a Data Word
• Code Word: The bigger block containing check bits
• Hamming Distance: Distance between two code words
is the number of disagreement between them.
• If data word has length l, and r number of check bits
are added to each data word to generate code
words of length n=l+r, we have 2l combinations of
data words to be mapped to code words from 2l+r
possible combinations.
• If we want to detect up to E errors, then all the
valid code words should be at least E+1 distance
apart.
• Error Correction Approaches
➢ Reverse Error Correction (REC)
- The receiver requests for retransmission of the
code word whenever it detects an error. If there
is no error, the receiver returns an ACK for the
correctly received code words
➢ Forward Error Correction (FEC)
- The code is so designed that it is possible for
the receiver to detect and correct the error
- The FEC decoder has 4 possible outcomes:
▪ No errors: If there are no bit errors, the input to the
FEC decoder is identical to the original codeword, and
the decoder produces the original data block as output.
• Detectable, correctable errors: For certain error
patterns, it is possible for the decoder to detect and
correct those errors. Thus, even though the incoming
data block differs from the transmitted codeword, the
FEC decoder is able to map this block into the original
data block.
• Detectable, not correctable errors: For certain error
patterns, the decoder can detect but not correct the
errors. In this case, the decoder simply reports an
uncorrectable error.
• Undetectable errors: For certain, typically rare, error
patterns, the decoder does not detect the error and
maps the incoming n-bit data block into a k-bit block
that differs from the original k-bit block.
• Block Code Principles
➢ The Hamming distance d(v1, v2) between two n-bit binary
sequences v1 and v2 is the number of bits in which v1 and v2
disagree. For example, if
v1 = 011011, v2 = 110001
then
d (v1, v2) = 3
➢ Suppose we wish to transmit blocks of data of length k bits.
Instead of transmitting each block as k bits, we map each k-
bit sequence into a unique n-bit codeword.
• Perfect Error Correcting Code
- No. of check bits required (r) to correct error for data word
length (l) ?
- For single bit errors
- we need to address this problem from two angles
(i) The no. of check bits should be sufficient to ensure
that single-bit errors do not generate another valid code
word.
(ii) The no. of check bits should be sufficient to point to
location of the bit in error if there is an error.
- A perfect error correcting code is the one in which no. of
check bits is equal to the minimum integer value of r that
satisfies the inequality 2r ≥ n +1. (for e.g., if n = 7, the
perfect code will require 3 check bits for coding 4-bit data
word.)
• Forward Error Correction Methods
- Block Parity
- Hamming Code
- Interleaved Code
- Convolutional Code
• Block Parity
- The data block is arranged in a rectangular matrix form
and two sets of parity bits are generated namely:
- Longitudinal Redundancy Check (LRC)
- Vertical Redundancy Check (VRC)
- VRC is the parity bit associated with the character code
and LRC is generated over the rows of the bits.
- Single bit errors in the block result in failure of LRC in
one of the rows and VRC in one of the columns.
- The bit which is at intersection of the row and the column is in
error.
• Hamming Code
- It consists of code words of length n each having r parity bits,
where r is the smallest integer satisfying the condition 2r ≥ n +1.
- The check bits are generated using even or odd parity for a
defined set of data bits.
- The location of error is pointed out by error syndrome, which is
calculated based on the parity checks. (for e.g., if the 6th bit is in
error, error syndrome will take binary value 110.)
- For correction of single bit errors in data word (4 bit), 3 check
bits are required.
- For a 7-bit hamming code, syndrome can take values from 001
to 111.
- LSB of the syndrome is 1 for the bit positions 1,3, 5 and 7 (first
parity). These positions are grouped together. The error in these
positions is detected by keeping a parity bit at any one of these 4
positions. Whenever any of these bit positions is in error, the LSB
of the syndrome is made 1.
• Middle bit of syndrome is 1 for bit positions 2,3,6 and 7(second
parity). Third parity bit is kept at any one of the positions 4,5,6
or 7
• Bit positions 1,2,4,8 … of the code word are reserved for the
parity bits. The other bit positions are for the data bits.
P1 P2 D P4 D D D P8 D D D