3D MODELING AND SIMULATION

OF GAAFETs

Monsoon 2024

Submitted
by

Swetabh Krishna Singh (2110110539)

and
Lakshmi gayatri Kasinadhuni(2110110770)

Under Supervision
of

Dr Venkatnarayan Hariharan
Department of Electrical Engineering

Department of Electrical Engineering,

School of Engineering,
Shiv Nadar Institution of Eminence Deemed to be University,
Delhi-NCR
 Abstract

The scaling of semiconductor devices in accordance with Moore’s Law has led to significant
challenges for traditional transistor architectures, particularly as technology nodes shrink
below 10nm. To address the limitations of planar MOSFETs, which suffer from short-
channel effects, leakage currents, and reduced gate control at smaller dimensions, more
advanced transistor designs have been introduced. FinFETs, with their tri-gate structure,
initially provided better electrostatic control and performance improvements. However,
as technology demands continue to push for smaller, faster, and more efficient devices,
Gate-All-Around Field-Effect Transistors (GAAFETs) have emerged as a critical solution
for sub-7nm nodes.

GAAFETs fully surround the conducting channel with the gate, offering superior
electrostatic control, reduced leakage, and improved scalability compared to both planar
MOSFETs and FinFETs. This report documents the 3D modelling and simulation of
GAAFETs using the Sentaurus TCAD tool suite, including Sentaurus Device Editor,
Sentaurus Mesh, and Sentaurus Device, which together enable precise modelling, meshing,
and electrical simulation of semiconductor devices.

The initial phase of our project has focused on gaining familiarity with Sentaurus
TCAD tools and Scheme scripting, which are essential for automating the design and
simulation process. Although the project is ongoing and we have not yet completed a full
GAAFET simulation, we have laid the foundation by developing basic device structures
and learning how to generate high-quality simulation meshes. Moving forward, our objec-
tives include refining the GAAFET models, optimizing device parameters, and completing
detailed simulations to analyze their electrical behavior.

This report highlights the importance of transitioning from planar MOSFETs to Fin-
FETs and ultimately to GAAFETs as technology scales down, detailing the challenges and
advantages of each architecture. It also outlines our work with Sentaurus TCAD so far,
while setting the stage for future modelling and performance optimization of GAAFET
devices, which are key to the continued evolution of semiconductor technology.

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 Contents

1 Introduction 6
1.1 Transition from Planar MOSFETs to FinFETs and GAAFETs . . . . . . . 6
1.1.1 Planar MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.2 FinFET Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 GAAFET Technology . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Literature Survey 9
2.1 Device Structure and Performance: . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Modeling and Simulation: . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Applications in Memory Technologies: . . . . . . . . . . . . . . . . . . . . 9
2.4 Challenges in Fabrication: . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Future Directions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Work Done 11
3.1 Generating Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.1 Defining Geometric Regions . . . . . . . . . . . . . . . . . . . . . . 11
3.1.2 Defining Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Doping Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Constant Profile Placement . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2 Analytical Profile Placement . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Meshing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1 Mesh Generation Process . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2 Mesh Visualization . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Sentaurus Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.1 MOSFET Output and Transfer Characteristics . . . . . . . . . . . 13
3.5 Carrier Quantization Effects . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Without Carrier Quantization . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 With Carrier Quantization . . . . . . . . . . . . . . . . . . . . . . . 14

4 Future Work 15
4.1 Completion of Device Modelling . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Performance Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Experimental Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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 List of Figures

1.1 Structure Comparison of Planar MOSFET, FINFET AND GAAFET . . . 7

3.1 2D and 3D Geometry of MOSFET . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Doping porfile of 2D and 3D MOSFET . . . . . . . . . . . . . . . . . . . . 12
3.3 Mesh Profile of 2D and 3D MOSFET . . . . . . . . . . . . . . . . . . . . . 13
3.4 Transfer characteristics of MOSFET . . . . . . . . . . . . . . . . . . . . . 13
3.5 Output characteristics of MOSFET . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4
 List of Tables

4.1 Key Device Parameter for 7nm node GAAFET . . . . . . . . . . . . . . . 16

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 Chapter 1

Introduction

The relentless pursuit of Moore’s Law, which predicts the doubling of transistors in in-
tegrated circuits approximately every two years, has led to continuous advancements in
transistor technology. This progression has been essential for the growth of modern elec-
tronics, enabling devices to become smaller, faster, and more energy-efficient. However,
as traditional transistor architectures have reached their physical limits, new designs have
emerged to maintain this trend.
One of the most promising alternatives is the Gate-All-Around Field-Effect Transistor
(GAAFET). This structure represents the latest advancement in metal-oxide-semiconductor
field-effect transistor (MOSFET) technology, with the gate completely surrounding the
conducting channel. By fully enveloping the channel, GAAFETs offer superior electro-
static control, reduced leakage currents, and enhanced scalability compared to earlier
designs. The GAAFET architecture is particularly important for sub-7nm process nodes,
which are pushing the boundaries of what conventional transistors can achieve.

1.1 Transition from Planar MOSFETs to FinFETs

and GAAFETs
Transistor technology has evolved from planar Metal-Oxide-Semiconductor Field-Effect
Transistors (MOSFETs) to advanced structures like Fin Field-Effect Transistors (Fin-
FETs) and Gate-All-Around Field-Effect Transistors (GAAFETs).
Planar MOSFETs face challenges such as short-channel effects and increased leak-
age currents as device dimensions shrink. FinFETs address these issues with a three-
dimensional structure that enhances electrostatic control and reduces leakage, making
them suitable for nodes below 20nm.
However, FinFETs encounter limitations with further scaling, leading to the devel-
opment of GAAFETs. GAAFETs feature a gate that surrounds the channel, providing
superior control and allowing for aggressive scaling down to sub-7nm nodes.

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 Figure 1.1: Structure Comparison of Planar MOSFET, FINFET AND GAAFET

1.1.1 Planar MOSFET

Planar MOSFETs, a cornerstone of early transistor technology, consist of a source, drain,
and channel placed on a flat silicon substrate, with a gate electrode positioned above the
channel. While effective at larger scales, planar MOSFETs faced significant limitations
as device sizes shrank to sub-32nm technology nodes:
• Short-Channel Effects: As the channel length decreases, the control that the gate
exerts over the channel diminishes, leading to increased leakage currents.
• Increased Leakage Currents: The planar structure struggles to prevent leakage when
the device is turned off, resulting in higher power consumption.
• Diminished Drive Current: The ability to increase drive current is limited by the
two-dimensional nature of the device.

1.1.2 FinFET Technology

To address these limitations, FinFETs were introduced. FinFETs are 3D structures where
the channel is shaped like a fin that rises above the substrate, and the gate wraps around
three sides of the fin (hence the term ”tri-gate”). This design improves gate control by
increasing the surface area through which the gate influences the channel, thus mitigating
short-channel effects and enhancing performance at smaller dimensions.
• Improved Electrostatic Control: The three-dimensional gate structure provides bet-
ter control over the channel, significantly reducing short-channel effects.
• Higher Drive Currents: FinFETs can achieve higher drive currents due to increased
surface area for gate control.

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 • Reduced Leakage Currents: The wrap-around gate minimizes leakage when the
device is off.

Despite these improvements, FinFET technology faces its own challenges as dimensions
continue to shrink:

• Scaling Limitations: As FinFET dimensions approach 5nm and below, further scal-
ing becomes difficult without compromising performance.

• Increased Complexity: The need for multiple fins increases manufacturing complex-
ity and cost.

1.1.3 GAAFET Technology

The Gate-All-Around Field-Effect Transistor (GAAFET) represents the next step in tran-
sistor design. Unlike FinFETs, where the gate surrounds the channel on three sides,
GAAFETs feature a gate that fully encircles the channel. This design provides even bet-
ter electrostatic control, further reducing short-channel effects and allowing for effective
scaling beyond 7nm

• Complete Gate Control: With gates surrounding the channel entirely, GAAFETs
provide enhanced electrostatic control and significantly reduce leakage currents.

• Scalability below 7nm: GAAFETs are more suited to smaller technology nodes,
where effective gate control is crucial for performance.

• Lower power consumption: Better control over the channel enables more efficient
switching, allowing for lower operating voltages and reduced power consumption.

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 Chapter 2

Literature Survey

Gate-All-Around FETs (GAAFETs) are emerging as a crucial technology in semiconduc-

tor design, particularly as the industry transitions from FinFETs to address challenges
associated with scaling at advanced nodes (3nm and below). The literature highlights
various aspects of GAAFET technology, including its design, fabrication processes, per-
formance characteristics, and applications.

2.1 Device Structure and Performance:

• GAAFETs utilize a nanosheet or nanowire structure that allows for better elec-
trostatic control compared to traditional FinFETs. This structure wraps the gate
around the channel on all sides, significantly improving current control and reducing
leakage currents.

• Research has demonstrated that GAAFETs can be constructed with varying materi-
als, including silicon, silicon-germanium (SiGe), and III-V compounds like InGaAs,
which enhance mobility and performance at scaled dimensions.

2.2 Modeling and Simulation:

• A compact modeling approach for n-type NS-GAAFETs has been developed to cor-
relate single-device parameters with digital circuit performance. This includes sim-
ulations of digital inverters and ring oscillators to evaluate the impact of GAAFET
designs on circuit efficiency.

• The use of Look-up table-based Verilog A approaches for device circuit co-design
has been explored, allowing for better integration of GAAFETs into existing design
frameworks.

2.3 Applications in Memory Technologies:

• Studies have focused on the application of GAAFETs in SRAM cells, demonstrating
how low DIBL (Drain Induced Barrier Lowering) designs can enhance stability and

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 reduce power consumption. The proposed 6T and 7T SRAM cells leverage GAAFET
technology for improved voltage transfer characteristics.

2.4 Challenges in Fabrication:

• Transitioning from FinFET to GAAFET technology presents several challenges, in-
cluding increased complexity in manufacturing processes and the need for advanced
lithography techniques such as high-numerical aperture EUV lithography to meet
the demands of sub-3nm nodes.

• The introduction of new materials also complicates processing requirements, neces-

sitating precise environmental controls during fabrication

2.5 Future Directions:

• Research indicates a trend towards developing complementary FET (CFET) archi-
tectures that integrate NMOS and PMOS GAAFETs vertically, which could further
increase transistor density and performance while maintaining low power consump-
tion15.

• Innovations in power distribution methods are being explored to address IR-drop

issues associated with high-density GAAFET designs, which is critical for future
high-performance computing applications.

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 Chapter 3

Work Done

This report provides a comprehensive overview of the design process we undertook using
Sentaurus TCAD, specifically focusing on the Sentaurus Structure Editor (SDE). The
training material guided us through a structured approach to creating both 2D and 3D
MOSFETs, emphasizing key functionalities such as boundary generation, doping pro-
files, mesh building, scripting, and process emulation. This detailed exploration not only
enhanced our understanding of semiconductor device design but also equipped us with
practical skills for modelling and simulation of GAAFETS

3.1 Generating Boundaries

3.1.1 Defining Geometric Regions
We focused on accurately defining the geometric boundaries that represent different mate-
rials in the device such as Silicon Substrate, Gate Oxide, PolySilicon Gate, Buried Oxide
and Nitric Spacer.

3.1.2 Defining Contacts

In addition to defining these geometric regions, setting up contacts is essential for es-
tablishing electrical connections between different parts of the MOSFET and external
circuits. We have defined the contacts for the source, drain, gate and body tie.

Figure 3.1: 2D and 3D Geometry of MOSFET

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3.2 Doping Profile
In semiconductor device design using Sentaurus TCAD, defining doping profiles is crucial
for determining the electrical characteristics of devices. Two primary methods for doping
profile placement are Constant Profile Placement and Analytical Profile Placement. Below
is a brief overview of each method.

3.2.1 Constant Profile Placement

• This method involves uniformly doping a specified region with a constant concen-
tration throughout that area.

• Ideal for bulk regions where uniform doping is sufficient, such as the substrate in a
MOSFET.

3.2.2 Analytical Profile Placement

• This method allows for more complex doping profiles, where the concentration varies
with depth or position according to predefined mathematical functions (e.g., Gaus-
sian or exponential).

• Particularly useful for source and drain regions in MOSFETs, where precise control
over doping depth and concentration is required.

Figure 3.2: Doping porfile of 2D and 3D MOSFET

3.3 Meshing
Meshing is a crucial step in the simulation of semiconductor devices using Sentaurus
TCAD. It involves creating a finite element mesh that discretizes the device geometry
into smaller elements, allowing for accurate numerical analysis. Below is an overview of
the meshing process, including the types of meshes generated and their applications.

3.3.1 Mesh Generation Process

• The mesh generation engine reads the boundary and command files to create a
spatial discretization of the device.

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 • Local mesh refinement can be applied based on doping concentrations and other
specified parameters.

3.3.2 Mesh Visualization

• After generating the mesh, it can be visualized using Sentaurus Visual to ensure
that it accurately represents the device geometry.

Figure 3.3: Mesh Profile of 2D and 3D MOSFET

3.4 Sentaurus Device

Sentaurus Device is a powerful semiconductor device simulator developed by Synopsys,
capable of simulating the electrical, thermal, and optical characteristics of various semi-
conductor devices.

3.4.1 MOSFET Output and Transfer Characteristics

Figure 3.4: Transfer characteristics of MOSFET

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 Figure 3.5: Output characteristics of MOSFET

3.5 Carrier Quantization Effects

3.5.1 Without Carrier Quantization
• The device behavior is described using classical drift-diffusion equations.

• Current flow is treated as continuous without considering the discrete energy levels
that carriers can occupy.

• This approach works well for larger devices but may not accurately predict behavior
at smaller scales (e.g., below 10nm).

3.5.2 With Carrier Quantization

• The Schrödinger equation is solved alongside Poisson’s equation to account for quan-
tum mechanical effects.

• The energy levels become quantized due to confinement in small dimensions, espe-
cially in short-channel devices like FinFETs.

• This results in more accurate predictions of electrical characteristics such as thresh-

old voltage shifts and subthreshold slope degradation.

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 Chapter 4

Future Work

4.1 Completion of Device Modelling

In the next phase of the project, we will refine our GAAFET models by incorporating more
realistic material properties, doping profiles, and device dimensions. This will involve
optimizing the geometry to achieve the desired electrical performance and scaling the
device to match current industry trends.

4.2 Performance Optimization

Once the device modelling is complete, we will focus on optimizing the performance of the
GAAFETs. This will include analyzing the trade-offs between different design parameters
such as gate length, oxide thickness, and nanowire dimensions. Our goal is to minimize
leakage currents while maximizing drive current and ensuring that the device operates
efficiently at smaller technology nodes.

4.3 Experimental Validation

To validate our simulation results, we plan to compare them with experimental data from
similar GAAFET structures. This will allow us to assess the accuracy of our models and
make adjustments as needed to improve the fidelity of the simulations.

Figure 4.1: Caption

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 Parameters Value
Contact gate pitch (CPP) 1 58 nm
Gate Length (Lg) 18 nm
Spacer length 5 nm
Contact length 14nm
S/D Doping 2x1020 cm−3
Channel Doping 1x1015 cm−3
Punch through Stop Doping 2x1018 cm−3
Number of Nanosheets 3
Nanosheet Width 36 nm
Nanosheet Thickness 6 nm
Nanosheet Spacing 12 nm

Table 4.1: Key Device Parameter for 7nm node GAAFET

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Bibliography

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