lOMoARcPSD|43410809

ANNAI VAILANKANNI COLLEGE OF ENGINEERING

(Approved by AICTE, New Delhi. Affiliated to Anna University,
Chennai) AZHAGAPPAPURAM, KANYAKUMARI-629401

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

2021 REGULATION

CS3351 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION

LABORATORY MANUAL

II YEAR/ III SEMESTER

COMPUTER SCIENCE ENGINEERING

Prepared by

LIGIVINO

ASSISTANT PROFESSOR OF ECE

 LIST OF EXPERIMENTS
Page Marks Signature
Sl. No. Date Name of the Experiment
No.
Verification of Boolean theorems using logic
1 gates.
Design and implementation of
2 combinational circuits using gates for
arbitrary functions.
Implementation of binary adder/subtractor
3 circuits.
Implementation of code converters.
4
Implementation of BCD adder, encoder and
5 decoder circuits
Implementation of functions using
6 Multiplexers.

7 Implementation of the synchronous counters

8 Implementation of a Universal Shift register.

Simulator based study of Computer

9 Architecture
BEYOND THE SYLLABUS

10 Study of logic gates

Design and implement combinational

11
circuits using Magnitude Comparator
 lOMoARcPSD|43410809

Ex.No.-1 VERIFICATION OF BOOLEAN THEOREMS USING LOGIC GATES

AIM:

To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED:

SL. NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
As per
5. CONNECTING WIRES - required

THEORY:

BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

3. Distributive Law
The binary operator OR, AND is said to be distributive
if, 1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law
1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

1. A = A

6. Idempotent Law
1. A+A = A
2. A.A = A

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7. Complementary Law
1. A+A' = 1
2. A.A' = 0

8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B

ASSOCIATIVE LAW

A+(B+C) = (A+B)+C A * (B * C) = (A * B) * C

TRUTH TABLE:

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DISTRIBUTIVE LAW

A.(B+C) = (A.B)+(A.C)

TRUTH TABLE

DEMORGAN’S THEOREM

De-Morgan's First Theorem:

According to the first theorem, the complement result of the AND operation is equal to the
OR operation of the complement of that variable. Thus, it is equivalent to the NAND function
and is a negative-OR function proving that (A.B)' = A'+B' and we can show this using the
following table.

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De-Morgan's Second Theorem

According to the second theorem, the complement result of the OR operation is equal to
the AND operation of the complement of that variable. Thus, it is the equivalent of the NOR
function and is a negative-AND function proving that (A+B)' = A'.B' and we can show this using
the following truth table.

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 lOMoARcPSD|43410809

COMMUTATIVE LAW

A.B=B.A

A+B = B+A

PROCEDURE:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

RESULT:

Thus the above stated Boolean laws are verified.

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Ex.No.-2 DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING GATES FO

AIM:
To design and implementation of combinational circuits using gates for arbitrary
functions.

APPARATUS REQUIRED

SL.NO. COMPONENT SPECIFICATION QTY

1 DC Power Supply 5V 1
Digital Trainer (Logic
2 - 1
Probe)
3 Breadboard - 1
4 DIP Switch - 1
5 NAND gate IC7400 1
6 NOR gate IC7402 1
7 Inverter IC7404 1
8 AND gate IC7408 1
9 OR gate IC7432 1

THEORY

Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates
that are “combined” or connected together to produce more complicated switching circuits.
These logic gates are the building blocks of combinational logic circuits. An example of a
combinational circuit is a decoder, which converts the binary code data present at its input into a
number of different output lines, one at a time producing an equivalent decimal code at its
output. PROCEDUE

Procedure:

1) Determine required number of inputs and outputs from the specifications.

2) Derive the truth table for each of the outputs based on their relationships to the input.
3) Simplify the Boolean expression for each output. ...
4) Draw a logic diagram that represents the simplified Boolean expression.

.
NAND Gate
Let's look at the outputs of a NAND gate. This means A NOT-AND B, or A.B (A dot B).
Graphically this is represented by a line over the A.B in the diagram.

Logic Gate Circuit Diagram

NOR Gate
The NOR, or NOT-OR gate means that if ANY of the inputs are ON, then the gate is
OFF. In other words, if both are off, then the output is ON. This is indicated by an A + B
notation, with the line above (as in the NAND gate). Let's look at the diagram first.
Logic Diagram
Converting From One to the Other
Let's put it all together and look at our full circuit as shown in Figure 4. We still have the
NAND gate and the NOR gate, but now we have the input C.

But, based on the diagram, we know that we have a NAND and a NOR. Look at input C: there is
no gate, so if C is ON, and none of the other switches are on, then Q is ON.
Given the diagram, we can build a Boolean Expression as seen in Figure 5. Each dot (.) means an
AND condition. It's a NAND gate AND a NOR gate AND gate C.

RESULT:

Thus the combinational circuits for arbitrary functions designed and implemented using
logic gates.
Ex.No.-3 IMPLEMENTATION OF BINARY ADDER/SUBTRACTOR CIRCUITS.

AIM:

To design and implementation of binary adder/subtractor circuits

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 23

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as
a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry
out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of
three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow output of the half subtractor
and the second term is the inverted difference outputof first X-OR.

HALF ADDER

LOGIC DIAGRAM TRUTH TABLE

K-Map for SUM: K-Map for CARRY:

1
1

SUM = A’B + AB’ CARRY = AB

FULL ADDER
LOGIC DIAGRAM:
TRUTH TABLE:

K-Map for SUM

1 1

1 1

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY

 CARRY = AB + BC + AC

HALF SUBTRACTOR
LOGIC DIAGRAM TRUTH TABLE

K-Map for DIFFERENCE K-Map for BORROW

1 1

DIFFERENCE = A’B + AB’ BORROW = A’B

 FULL SUBTRACTOR

LOGIC DIAGRAM

TRUTH TABLE

K-Map for Difference

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for
Borrow

Borrow = A’B + BC + A’C

PROCEEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the half adder, full adder, half subtractor and full subtractor circuits are designed,
constructed and verified the truth table using logic gates.
EX.No:4 IMPLEMENTATION OF CODE CONVERTERS

AI
M To design and implement 4-bit

(i) Binary to gray code converter

(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED

Sl. Component Specification Qty.

No.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be inserted
between the two systems if each uses different codes for same information. Thus, code converter
is a circuit that makes the two systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four bits
to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted
code.
 The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines generate
the corresponding bit combination of code. Each one of the four maps represents one of the four
outputs of the circuit as a function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each of
three outputs.

BINARY TO GRAY CODE CONVERTOR

Logic Diagram
K-Map for G3 K-Map for G2

G3 = B3

K-Map for G1 K-Map for G0

Truth Table

Binary input | Gray code output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
 GRAY CODE TO BINARY CONVERTOR

Logic Diagram

K-Map for B3 K-Map for B2

B3 = G3
 K-Map for B1 K-Map for B0

Truth Table
 BCD TO EXCESS-3 CONVERTOR

Logic Diagram

K-Map for E3 K-Map for E2

E3 = B3 + B2 (B0 + B1)
 K-Map for E1 K-Map for E0

Truth Table
 EXCESS-3 TO BCD CONVERTOR

Logic Diagram

K-Map for A K-Map for B

A = X1 X2 + X3 X4 X1
K-Map for C K-Map for D

Truth Table
PROCEDURE

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

Result
Thus, binary to gray code converter, Gray to binary code converter, BCD to excess-3 code
converter, Excess-3 to BCD code converter was implemented.
EX.No:5 IMPLEMENTATION OF BCD ADDER, ENCODER AND DECODER CIRCUI

AIM

To design and implement of BCD adder, encoder and decoder circuits

Apparatus Required

Sl. No. Component Specification Qty.

1. IC IC 7483 1
2. EX-OR Gate IC 7486 1
3. OR Gate IC 7432 3
4. NOT Gate IC 7404 1
5. 3 I/P NAND Gate IC 7410 2
6. IC Trainer Kit - 1
7. Patch Cords - 40

BCD ADDER

THEORY

Consider the arithmetic addition of two decimal digits in BCD, together withan input
carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be
greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be
represented in BCD and should appear in the form listed in the columns.

ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4 bit adder to produce the binary
sum.
Pin Diagram for IC 7483

LOGIC DIAGRAM
K- MAP

Y = S4 (S3 + S2)

TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0
 1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

ENCODER AND DECODER

THEORY

ENCODER:

An encoder is a digital circuit that perform inverse operation of a decoder.

An encoder has 2n input lines and n output lines. In encoder the output lines generates the binary
code corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generate the corresponding binary code. In encoder it is assumed
that only one input has a value of one at any given time otherwise the circuit is meaningless. It
has an ambiguila that when all inputs are zero the outputs are zero. The zero outputs can also be

generated when D0 = 1.

DECODER:

A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word i.e
there is one to one mapping can be expressed in truth table. In the block diagram of decoder
circuit the encoded information is present as n input producing 2 n possible outputs. 2n output
values arefrom 0 through out 2n– 1.
LOGIC DIAGRAM FOR ENCODER

TRUTH TABLE
 Logic Diagram for Decoder

TRUTH TABLE

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0
Procedure

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

Result

Thus, the BCD Adder, Encoder and Decoder were designed using logic gates and implemented
EX.No:6 IMPLEMENTATION OF FUNCTIONS USING MULTIPLEXERS.

AIM

To Implementation of functions using Multiplexers.

APPARATUS REQUIRED

Sl. No. Component Specification Qty.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY

MULTIPLEXER

Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2 n input line andn
selection lines whose bit combination determine which input is selected.

Block Diagram for 4:1 Multiplexer

Circuit Diagram For Multiplexer

Truth Table

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Procedure

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

Result
Thus, the multiplexer was designed using logic gates and implement.
EX. No: 7 IMPLEMENTATION OF THE SYNCHRONOUS COUNTERS

AIM:

To design and Implementation of the synchronous counters.

APPARATUS REQUIRED:

S.NO. NAME OF THE APPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1
2. D Flip Flop IC 7474 4
3. NAND gate IC 7400 1
4. Connecting wires As required

THEORY

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states appears as
counter output. This is the main difference between a register and a counter. There are two types of
counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and
in asynchronous first flip flop is clocked by external pulse and then each successive flip flop is
clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by
output of first stage. Because of inherent propagation delay time all flip flops are not activated at
same time which results in asynchronous operation.

TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the synchronous counters are designed, implemented and verified its truth
table.
EX.No:8 IMPLEMENTATION OF A UNIVERSAL SHIFT REGISTER

AIM

To design and Implementation of a Universal Shift register

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one
that uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of
the register. Each clock pulse shifts the contentof register one bit position to right.

PIN DIAGRAM OF IC 7474:

 SERIAL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

CLK Serial In Serial Out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

SERIAL IN PARALLEL OUT

LOGIC DIAGRAM:
TRUTH TABLE:

OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

PARALLEL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1
 PARALLEL IN PARALLEL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK
DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

The Serial in serial out, Serial in parallel out, Parallel in serial out and Parallel in parallel
out shift registers are designed and implemented.
EX.No: 9 SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE

AIM

To Simulator based study of Computer Architecture

THEORY

Computer architecture simulators are used for the following purposes:

 Lowering cost by evaluating hardware designs without building physical hardware systems.
 Enabling access to unobtainable hardware.
 Increasing the precision and volume of computer performance data.
 Introducing abilities that are not normally possible on real hardware such as running code
backwards when an error is detected or running in faster-than-real time

FULL-SYSTEM SIMULATORS

A full-system simulator is execution-driven architecture simulation at such a level of

detail that complete software stacks from real systems can run on the simulator without any
modification. A full system simulator provides virtual hardware that is independent of the nature of
the host computer. The full-system model typically includes processor cores, peripheral
devices, memories, interconnection buses, and network connections. Emulators are full system
simulators that imitate obsolete hardware instead of under development hardware.
The defining property of full-system simulation compared to an instruction set simulator is that the
model allows real device drivers and operating systems to be run, not just single programs. Thus,
full-system simulation makes it possible to simulate individual computers and networked computer
nodes with all their software, from network device drivers to operating systems, network
stacks, middleware, servers, and application programs.
Full system simulation can speed the system development process by making it easier to detect,
recreate and repair flaws. The use of multi-core processors is driving the need for full system
simulation, because it can be extremely difficult and time-consuming to recreate and debug errors
without the controlled environment provided by virtual hardware. This also allows the software
development to take place before the hardware is ready, thus helping to validate design decisions.

CYCLE-ACCURATE SIMULATOR
A cycle-accurate simulator is a computer program that simulates a micro architecture on a
cycle-by-cycle basis. In contrast an instruction set simulator simulates an instruction set
architecture usually faster but not cycle-accurate to a specific implementation of this architecture;
they are often used when emulating older hardware, where time precision is important for legacy
reasons. Often, a cycle-accurate simulator is used when designing new microprocessors – they can
be tested, and benchmarked accurately (including running full operating system, or compilers)
without actually building a physical chip, and easily change design many times to meet expected
plan.
Cycle-accurate simulators must ensure that all operations are executed in the proper virtual
(or real if it is possible) time – branch prediction, cache misses, fetches, pipeline stalls, thread
context switching, and many other subtle aspects of microprocessors.

INSTRUCTION SET SIMULATOR (ISS).

An instruction set simulator (ISS) is a simulation model, usually coded in a high-level
programming language, which mimics the behavior of a mainframe or microprocessor by
"reading" instructions and maintaining internal variables which represent the processor's registers.
Instruction simulation is a methodology employed for one of several possible reasons:

 To simulate the machine code of another hardware device or entire computer for
upward compatibility—a full system simulator typically includes an instruction set
simulator.
For example, the IBM 1401 was simulated on the later IBM/360 through use
of microcode emulation.

 To monitor and execute the machine code instructions (but treated as an input stream) on
the same hardware for test and debugging purposes, e.g. with memory protection (which
protects against accidental or deliberate buffer overflow).
 To improve the speed performance—compared to a slower cycle-accurate simulator—of
simulations involving a processor core where the processor itself is not one of the
elements being verified; in hardware description language design using Verilog where
simulation with tools like ISS[citation needed] can be run faster by means of "PLI" (not to be
confused with PL/1, which is a programming language).

SIMULATION TYPES

 Discrete Event Simulation. Modeling a system as it progresses through time,

for example; ...
 Dynamic Simulation. Modeling a system as it progresses through space, for example; ...
 Process Simulation.

SIMULATION SOFTWARES

1. 20-SIM - Bond Graph-Based Multi-Domain Simulation Software

2. MATLAB - a programming, modeling and simulation tool developed by Math Works
3. SIMUL8 - software for discrete event or process based simulation
 4. SIMULINK - a tool for block diagrams, electrical mechanical systems and machines
from Math Works.
5. ADVANCED SIMULATION LIBRARY - open-source hardware accelerated metaphysics
simulation software
6. GNU Octave - an open-source mathematical modeling and simulation software very similar
to using the same language as MATLAB and Free mat
7. VSim - a multiphysics simulation software tool designed to run computationally intensive
electromagnetic, electrostatic, and plasma simulations

COMPUTER ARCHITECTURE

SIMULATION MODELS
RESULT

Thus the studied simulator based computer architecture.

BEYOND THE SYLLABUS
EX.No:10 STUDY OF LOGIC GATES

AIM

To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:

Circuit that takes the logical decision and the process are called logic gates.Each gate
has one or more input and only one output.OR, AND and NOT are basic gates. NAND, NOR
and X-OR are known as universal gates. Basic gates form these gates.

AND GATE

The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.

SYMBOL
PIN DIAGRAM

OR GATE

The OR gate performs a logical addition commonly known as OR function. The output
is high when any one of the inputs is high. The output is low level when both the inputs are
low.

SYMBOL
 NOT GATE

The NOT gate is called an inverter. The output is high when the input is low. The output
is low when the input is high.

SYMBOL PIN DIAGRAM

TRUTH TABLE

NAND GATE

The NAND gate is a contraction of AND-NOT. The output is high when both inputs
are low and any one of the input is low .The output is low level when both inputs are high.

SYMBOL PIN DIAGRAM

TRUTH TABLE
 NOR GATE

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are
low. The output is low when one or both inputs are high.

SYMBOL PIN DIAGRAM

TRUTH TABLE

X-OR GATE

The output is high when any one of the inputs is high. The output is lowwhen both
the inputs are low and both the inputs are high.

SYMBOL PIN DIAGRAM

TRUTH TABLE
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

The logic gates are studied and its truth tables are verified
EX.No: 11 DESIGN AND IMPLEMENT COMBINATIONAL CIRCUITS USING MA

AIM:
To design and implement the magnitude comparator.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE COMPARATOR IC 7485 2
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:

The comparison of two numbers is an operator that determine one number is greater than,
less than (or) equal to the other number. A magnitude comparator is a combinational circuit
that compares two numbers A and B and determine their relative magnitude. The outcome of
the comparator is specified by three binary variables that indicate whether A>B, A=B (or)
A<B, A=B (or) A<B
The equality of the two numbers and B is displayed in a combinational circuit designated
by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs of significant
digits starting from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be expanded as

1 1
A>B = A3B +X A B + X X A B 1 +X X X A B 1
3 3 2 2 3 2 1 1 3 2 1 0 0

1 1 1 1
A<B = A3 B3 + X3A2 B2 + X3X2A1 B1 + X3X2X1A0 B0
LOGIC DIAGRAM

TRUTH TABLE

P Q P>Q P=Q P<Q

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the magnitude comparator is designed and implemented