388 Journal of Power Electronics, Vol. 16, No. 1, pp.

388-397, January 2016

http://dx.doi.org/10.6113/JPE.2016.16.1.388
JPE 16-1-39 ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Voltage Source Inverter Drive Using

Error-compensated Pulse Width Modulation
Keng-Yuan Chen†, Jwu-Sheng Hu*, and Jau-Nan Lin*
†
Dept. of Electrical Eng., Yuan-Ze University, Chung-Li, Taiwan
*
Dept. of Electrical and Control Eng., National Chiao Tung University, Hsin-Chu, Taiwan

Abstract

An error-compensated pulse width modulator (ECPWM) is proposed to improve the baseband harmonic performance and the
switching loss of voltage source inverters (VSIs). Selecting between harmonic distortion and switching loss is a design tradeoff
in the conventional space vector pulse width modulation. In this work, an accumulated difference in produced and desired phase
voltages is considered to adjust the reference signal. This mechanism can compensate for the voltage error in the previous carrier
period. With error compensation every half-carrier period, the proposed ECPWM allows one-half reduction in carrier frequency
without scarifying baseband harmonic distortion. The proposed modulator is applied to a three-phase VSI with R–L load and a
motor-speed-control system for experiments. The measured efficiency and operating temperature of switches confirm the
effectiveness of the proposed scheme.

Key words: Digital signal, Motor drive, Pulse-width modulation (PWM), Space-vector PWM, Voltage-source inverter

given a fixed switching frequency [4]–[10]. For example, the

I. INTRODUCTION
extended-state observer-based control scheme [9] is proposed
Voltage source inverters (VSIs) are widely utilized in to reduce current harmonics. The interleaved PWM is
driving variable-speed alternating current motors. suggested to reduce output current ripple [10]. The filtered
Sine-triangle pulse width modulation (PWM), space vector PWM [6] is shown to attenuate baseband harmonics,
PWM (SVPWM), and discontinuous PWM (DPWM) are especially for small modulation index reference. The novel
common real-time approaches to generate the driving signals selective harmonic elimination-based multi-module PWM [5],
for VSIs. Extensive discussions of these PWMs indicate that the multi-rate repetitive control PWM [7], the three-stage
these PWMs can be unified by shifting efficient conducting hybrid modulator [8], and the immune algorithm-based
time [1], changing modulation signals [2], or using different SVPWM [4] are applied to reduce voltage harmonic
zero-vector distributions [3]. Therefore, a simple distortion.
carrier-based implementation architecture can be used to have A different effective time placement is used in a
all the advantages of modulators, that is, simple dual-inverter-fed open-end winding induction motor [11] to
implementation, extended linear modulation index, and 33% limit switching power loss. A modified finite-step predictive
of switching number reduction. torque control is proposed in [12] to improve inverter loss by
Linear modulation range, implementation simplicity, reducing switching frequency and calculation time. In [13],
power efficiency, and harmonic distortion are important an adaptive feedback controller is developed to produce flux
factors in the control of VSIs. The tradeoff between switching reference with optimized energy consumption of the
loss and harmonic distortion remains a critical design issue. induction motor. The modified phase disposition PWM is
Several PWM techniques are discussed to reduce distortion applied to a flying capacitor inverter for voltage balancing
Manuscript received Jun. 2, 2015; accepted Jul. 15, 2015 and efficiency improving [14].
†
Recommended for publication by Associate Editor Jee-Hoon Jung. A novel inverter topology is proposed to reduce switching
Corresponding Author: bettery33@gmail.com
loss and harmonic distortion [15]. The synchronized DPWM
Tel: +886-5-4638800, Fax: +886-3-4639355, Yuan-Ze University
*
Dept. of Electrical and Control Eng., National Chiao Tung University, [16] is used in the application of a high-power, three-level
Taiwan VSI with lagging loads. Several novel DPWMs with double

© 2016 KIPE
 Voltage Source Inverter Drive Using … 389

injections are analyzed in [17] to obtain minimum current

harmonic or minimum switching loss. A feedback
quantization modulator [18] is applied to a permanent-magnet
synchronous motor (PMSM) drive system to show a 33%
reduction in switching number in contrast to SVPWM in [19].
The minimum-switching-loss PWM proposed in [20] can
reduce up to 36% of switching loss. However, the result in
[17] shows that different switching strategies must be applied
to achieve minimum distortion or minimum switching loss.
The methods in [18], [20] involve complicated calculation to Fig. 1. Three-phase VSI topology.
produce switching signals that will influence the applicability
The remainder of this paper is organized as follows:
of modulators. In this work, a simple approach based on error
Section II provides the mathematical formulation of the
compensation and asymmetric pulse width production is
proposed modulator and the mechanism of reference
suggested to achieve 50% of switching number reduction
adjustment. Section II shows the system analysis. Sections III
without sacrificing baseband harmonic distortion.
and IV present the simulations and experiments, respectively.
Several different asymmetrical switching signal production
Finally, Section V concludes this paper.
methods have been proposed recently. For example, [21]
produces random pulse-position-switching commands by
adopting varying rising/falling slopes of triangular wave to II. ECPWM
reduce the carrier harmonic and acoustic noise of a motor
A. Objectives of Modulation
drive. The asymmetrical pulse gives an additional degree of
For the three-phase VSI system depicted in Fig. 1, the
freedom when selective harmonic elimination [22] or bee
objective is to decide the on/off status of six switches to
colony optimization [23] is used. All the asymmetrical
produce desired phase voltage on the load, VaN VbN VcN  .
T
PWMs in [21]–[23] focus on declining harmonics only.
In this work, both baseband harmonic distortion and If the on (off) status of the upper switch is denoted as +1 (0),
switching loss are considered. The simplest way to reduce then the switching state of the three-phase VSI system can be
represented by a switching vector, s1 s2 s3  , which has
switching loss is to reduce switching number, that is, to T

reduce carrier frequency. However, baseband harmonic

elements that belong to the set {0, 1}. Therefore, the
distortion increases with reduced carrier frequency when the
conventional SVPWM is applied. This study proposes an instantaneous phase voltage (normalized to Vdc ) can be
error-compensated pulse width modulator (ECPWM). obtained from Equ. (1).
Different references are applied for the rising and falling VaN   2 3  1 3  1 3  s1 
edges of the carrier by voltage error compensation at a rate of V     1 3 2 3  1 3  s2 
 bN    
twice of the carrier frequency. This mechanism can greatly VcN    1 3  1 3 2 3   s3 
(1)
improve baseband harmonics and achieves a comparable
By considering the duty ratios for each phase lag, we
performance by using only half of the switching frequency in
express the normalized mean voltage produced within each
contrast to SVPWM. Therefore, the ECPWM reduces
carrier cycle as Equ. (2) according to Equ. (1).
switching loss by using a low carrier frequency without
VaN   2 3  1 3  1 3 1   1 
sacrificing baseband harmonic distortion. V    1 3 2 3  1 3    S  
In the simulation, a three-phase VSI with R–L load is built  bN    2  c  2 
in PSIM. Comparisons of the phase voltages and the phase VcN   1 3  1 3 2 3   3   3 
, (2)
currents produced by SVPWM and the proposed modulator  ,
where 1 2 3  ,   0 1 are the duty ratios for phase lags.
are shown. An experimental platform based on field-oriented
control (FOC) is built to drive a PMSM to verify the Under analog implementation, the values of  1 ,  2 ,  3 can
reliability, applicability, and effectiveness of the proposed be selected arbitrarily within the range 0 1. However, for
modulator. The switching number and harmonic distortion of the digital implementation with carrier frequency f c and
the produced phase currents are illustrated. Closed-loop
pulse bit resolution b -bit, the minimum pulse width that can
performances, such as motor speed and output torque, are
be produced is 1  f c  2  s, and a master clock frequency of
b
also measured. Under the condition that the switching
number of the proposed modulator is half that of SVPWM,  f c  2b  Hz is required. The produced duty ratios are limited
the results indicate that the system efficiency and the b
to be integer multiples of 2 , that is, they must belong to
operating temperature of power metal oxide semiconductor
the set 0,1 2 , 2 2 ,, 2  1 2 ,1. Thus, voltage deviation
b b b b
field-effect transistors (MOSFETs) are improved.
390 Journal of Power Electronics, Vol. 16, No. 1, January 2016

is unavoidable with a finite pulse width resolution. The

voltage error, although small within each carrier period, will
accumulate and induce considerable current harmonics [24].
Therefore, the objective of the switching signal generation is
to decide the duty ratios  1 ,  2 ,  3  0 1 such that the
accumulated voltage error is compensated for within every
Fig. 2. Block diagram of quantization error compensation.
carrier period, that is, minimizing the difference in the
desired and the produced voltage signals.
Given that the matrix v1 v 2 v 3  is orthonormal, Equ.
B. Error Compensation (6) can be written as
For future reference, the input three-phase voltages,  0 0 0 1 k 
denoted as r k   r1 k  r2 k  r3 k  , are normalized with v1 v 3  dk   0 1 0v1 v 3   2 k 
T T T
v2 v2
   
0 0 1  3 k 
respect to direct current (DC)-link voltage Vdc . For a given , (7)
which implies that
duty ratio, 1 k   2 k   3 k  , the produced phase voltage
T

 v1T dk   0   1 k 
is S c 1  2  3  . Therefore, the difference between the
 T   T 
 v 2 dk    v 2 ak  a k    2 k 
T

 
reference input and the produced phase voltage is in the form  v T3 dk   v T3 ak   3 k 
  , where . (8)
 1 k   v T
d k 
  To have a solution in Equ. (8), the 1 in the left-hand
r k   S c qb   2 k  
 
side of Equ. (8) must be zero. The equation v1 d k   0 is
T
  k  
 3   , (3)
proven in Appendix A. Considering the matching equation in
where qb y is the quantization that ensures y belongs to
1 k 
the set 0,1 2 , 2 2 , , 2  1 2 ,1. To compensate for the
b b b b
 k   dk 
 2 
error in Equ. (3), the duty ratio is adjusted according to  k 
Equ. (9),  3  is a solution regardless of the
minimizing the effect of accumulated error, ek  , which is   0 1
constraint i .
the accumulated difference in the desired and the produced
phase voltages, that is, 1 k  1 k 
v T2 dk   v T2  2 k  and v T3 dk   v T3  2 k 
 1 k      
   3 k   3 k 
e k   e k  1  r k   S c qb   2 k   (9)
 
  k   A modified solution, as shown in Equ. (10), can be applied
 3   .
(4)
to have feasible duty ratios. Given that v 2 v1  0 and
T

Therefore, the duty ratio is obtained by minimizing ek 

in Equ. (4). Equ. (4) implies that switching commands are vT3 v1  0 , Equ. (9) still holds when the duty ratios in Equ.

influenced by input r k  and previous error signal ek  1 . (10) are used.
The duty ratio can be obtained accordingly by solving the  1 k 
 k   d k   v
matching problem given below.  2  1

 2 3  1 3  1 3 1 k   3 k  (10)

dk     1 3 2 3  1 3  2 k   is a real number and is selected to ensure that the
  
  1 3  1 3 2 3   3 k  , 
(5a) values of duty ratios i are feasible. One selection of  is
where dk   ek  1  rk  . (5b) 3 multiplied with the minimum value among
to set it to be
the elements in d k  . The injection of  will not influence
C. Duty Ratios for Error Compensation
Eigenvalue decomposition is applied to find the duty ratios
the produced phase voltage when the y-connected load with
that satisfy Equ. (5), that is, Equ. (5a) is written as
an isolated neutral point is applied. The block diagram for
0 0 0  1 k  quantization error compensation is shown in Fig. 2. The
dk   v1 v 2 v 3 0 1 0v1 v 2 v 3   2 k 
T

output q k  is the corresponding phase duties that are

0 0 1  3 k  , (6) used to produce switching commands.
where v i , i  1, 2, 3 are the eigenvectors of Sc , and D. System Analysis
 1 3 2 6 0 
Proposition 1: Given a reference r  r1 r2 r3  satisfying
T
 
v 1 v2 v 3    1 3 1 6 1 2
 1
 3 1 6 1 2  r1  r2  r3  0
. , the duty ratios produced by Equs. (10), (5b),
 Voltage Source Inverter Drive Using … 391

and (4) for a three-phase VSI can compensate for the voltage 1  k1    1 3 1
error of each phase.    
 2  k1    d  k1     1 3   d  k1   1 1 , (15)
[Proof] Considering the duty ratios produced for the present 
 3  k1     1
input r k  and using Equs. (10) and (5b), duty ratios can be
 1 3 

written as where dk1   ek1  1  rk1  , (16)

1 k  1 k1  
 k   d k   v  e k  1  r k   v  
 2  1 1. (11) ek1   ek1  1  r k1   S c qb  2 k1   , (17)
 3 k   k  
 3 1  
and 1 is the minimum value among the elements in d k  .
By substituting Equ. (11) into Equ. (4), we can write
ek   ek  1  rk   S c qb ek  1  r k   v1 . (12)
[Proof] The error Δ b k1  is defined as the difference
We define the error Δ b k  as the difference between the between the desired and the produced duty ratios during
desired and the produced duty ratios within a carrier period, k1 -th half-carrier period, that is,
namely,
Δ b k1   e k1  1  r k1   v1 
Δ b k   ek  1  rk   v1   qb ek  1  r k   v1  . (13) . (18)
 qb e k1  1  r k1   v1 
Equ. (12) can then be rewritten as Equ. (14), applying that
By substituting Equs. (15), (16), and (18) into Equ. (17),
S c v 1  0 S c e k   e k 
, , and S c r k   r k  . we can write
ek   e k  1  r k   S c Δ b k   e k  1  r k   v1  ek1   ek1  1  r k1   S c qb ek1  1  r k1   v1
(14)
 S c Δ b k   ek1  1  r k1   S c ek1  1  r k1   Δ b k1  . (19)
The right-hand side of Equ. (14) is the error mapping by  S c Δ b k1 
the matrix S c . The voltage error appears on the Y-connected Equ. (19) states that the error signal, ek1  , is the voltage
phases. Therefore, Equ. (14) implies that with the duty ratios deviation in the Y-connected load. This error signal is
produced by Equ. (10), the error signal e k  is the voltage
compensated for by adjusting the reference of the subsequent
half-carrier period as [see Equ. (16)]
deviation on the phases. From Equ. (5b), this deviation is
dk1  1  ek1   rk1  1 . (20)
used to adjust the reference during the subsequent carrier
Therefore, the proposed three-phase VSI modulator can
period to produce duty ratios. Therefore, a single cycle is
compensate for voltage errors every half-carrier period.
sufficient for the algorithm to cancel the voltage error.
However, the voltage reference and the quantization error are
not constant, that is, at any iteration, a residual voltage error III. SIMULATION RESULTS
exists. The phase voltage deviation produced during the
To confirm the effectiveness of the proposed ECPWM, the
previous carrier period is compensated for by applying one
conventional SVPWM and the proposed ECPWM are
cycle delay tracking of the reference voltage, as shown in
implemented by visual C++, and the three-phase VSI with
Equs. (10), (5b), and (4).
R–L load is built by PSIM. The resistance (inductance) of the
E. Asymmetric Pulse Production load is 10 Ω (15 mH). The DC-link voltage is 15 V.
The rate of error compensation is selected to be twice the The 50 Hz sinusoidal wave with a normalized amplitude of
carrier frequency to improve the quality of the produced 0.5 is sampled at 8 kHz and applied to the modulators
(SVPWM and ECPWM) to produce gating signals. The
phase voltage. In this setting, given a carrier frequency f c ,
carrier frequency of SVPWM (ECPWM) is set as 8 kHz
the reference, r k1  , and the duty ratios, (4 kHz), and the pulse bit resolution of both modulators is 10.
1 k1   2 k1   3 k1 T , are updated at a rate 2 f c , that is, The gating signals for the first phase lag and the produced
the signals to be compared with triangular wave during rising phase voltages/currents for both modulators are shown in
Figs. 3 and 4. The phase voltages produced by the ECPWM
and falling edges are different. k1 corresponds to the index and the SVPWM are comparable by using half of the
of period 1 2 f c  , whereas k corresponds to the index of switching number in the ECPWM. The frequency
components of the produced phase voltage and the phase
period 1 f c .
current are shown in Figs. 5–8 to analyze baseband harmonic
Proposition 2: A three-phase VSI modulator with carrier
distortion. The baseband harmonics of the voltage/current
frequency f c can compensate for errors every half-carrier produced by the ECPWM are reduced by using only half of
period for the regular sampled reference
the switching frequency in contrast to those produced by the
r k1   r1 k1  r2 k1  r3 k1  (sampled at the frequency 2 f c )
T

SVPWM.
when the duty ratio for each reference rk1  is selected as For precise comparison, Table I (Table II) lists the voltage
392 Journal of Power Electronics, Vol. 16, No. 1, January 2016

Frequency analysis
gating signal 10
1.5
1 0
0.5
0 -10
-0.5
0.05 0.051 0.052 0.053 0.054 0.055 -20
produced phase voltage

Magnitude(dB)
Amplitude (V)

10 -30
0 -40
-10
-50
0 0.02 0.04 0.06 0.08 0.1
produced phase currents -60
Amplitude (A)

1
-70
0
-80
-1
0 0.02 0.04 0.06 0.08 0.1 1 2 3 4 5
Time(s) 10 10 10 10 10
Frequency(Hz)
Fig. 3. Simulation results for the SVPWM (upper: gating signal
Fig. 7. Frequency analysis of the phase current produced by the
for the first phase lag, middle: produced phase voltage, lower:
SVPWM.
produced phase currents). Frequency analysis
10

gating signal 0
1.5
1 -10
0.5
0 -20

Magnitude(dB)
-0.5
0.05 0.051 0.052 0.053 0.054 0.055 -30
produced phase voltage
Amplitude (V)

-40
10
0 -50
-10
-60
0 0.02 0.04 0.06 0.08 0.1
produced phase currents -70
Amplitude (A)

0
-80
1 2 3 4 5
-1 10 10 10 10 10
0 0.02 0.04 0.06 0.08 0.1 Frequency(Hz)
Time(s)
Fig. 4. Simulation results for the ECPWM (upper: gating signal Fig. 8. Frequency analysis of the phase current produced by the
for the first phase lag, middle: produced phase voltage, lower: ECPWM.
produced phase currents).
TABLE I
Frequency analysis SIMULATION RESULT: HARMONIC ANALYSIS OF THE PRODUCED
10 PHASE VOLTAGE
0
Input frequency 50 Hz
-10 Modulato Carrier Harmonics Harmonics
-20 r frequency within [0 1 k] within [0 3 k]
Magnitude(dB)

-30 (Hz) Hz (%) Hz (%)

-40 8k 0.129 0.167
SVPWM
-50 4k 0.132 0.402
-60 ECPWM 4k 0.095 0.370
-70

10
1
10
2
10
3
10
4
10
5 TABLE II
Frequency(Hz) SIMULATION RESULT: HARMONIC ANALYSIS OF THE PRODUCED
Fig. 5. Frequency analysis of the phase voltage produced by the PHASE CURRENT
SVPWM. Input frequency 50 Hz
Frequency analysis
Modulato Carrier Harmonics Harmonics
10 r frequency within [0 1 k] within [0 3 k]
0 (Hz) Hz (%) Hz (%)
-10 8k 0.047 0.047
SVPWM
-20 4k 0.054 0.057
Magnitude(dB)

-30 ECPWM 4k 0.029 0.033

-40

-50 (current) harmonic distortion under different carrier

-60 frequencies. The voltage/current harmonics increase when
-70 the carrier frequency of the SVPWM is reduced. The
10
1
10
2
10
3
10
4
10
5 ECPWM can reduce the baseband harmonic distortion under
Frequency(Hz)
a low-carrier frequency setting by applying the error
Fig. 6. Frequency analysis of the phase voltage produced by the
compensation mechanism. Among the three different
ECPWM.
 Voltage Source Inverter Drive Using … 393

modulators in Table I/Table II, the harmonic distortion of the 10

Voltage

ECPWM is the lowest within [0 1 k] Hz. The compensation

0
for the accumulated voltage error enhances the low-frequency
performance. -10

Magnitude(dB)
-20

IV. EXPERIMENTS -30

Two experimental platforms are built to confirm the -40

correctness and the feasibility of the proposed modulator. In
-50
the first part of this section, the experimental results for a
1 2 3 4 5
three-phase VSI connected with a Y-type R–L load are 10 10 10 10 10
Frequency(Hz)
shown. In the second part, a motor drive system using FOC is Fig. 9. Frequency analysis of the phase voltage produced by the
implemented. Both the SVPWM and the ECPWM are applied SVPWM.
and compared. Results indicate that the proposed modulator
Voltage
can be applied directly to the FOC-based motor controller. 10

A. Experimental Results for VSI Drive 0

In the first experimental platform, six power MOSFETs -10

Magnitude(dB)
(IRF640N) are used to build a three-phase VSI. The DC-link -20
voltage is 15 V, and the output of the VSI is connected to a
Y-type R–L load (R = 10 Ω, L = 15 mH). Both the proposed -30

ECPWM and the conventional SVPWM are implemented on -40

a field-programmable gate array (FPGA, EP2C20F484C8, -50

Cyclone II) to produce gating commands. 1 2 3 4 5
10 10 10 10 10
For the 50 Hz sinusoidal reference with a normalized Frequency(Hz)
amplitude of 0.5 and a sampling frequency of 8 kHz, Figs. Fig. 10. Frequency analysis of the phase voltage produced by the
9–12 plot the frequency-domain analysis of the measured ECPWM.
phase voltage/current. The carrier frequency of the SVPWM Current
(ECPWM) is 8 kHz (4 kHz), and the pulse bit resolution is 10. 10
5
From Figs. 9–12, the baseband harmonics are reduced by
0
using the proposed ECPWM. Tables III and IV list the -5
harmonic distortions of the phase voltage/current for different
Magnitude(dB)

-10
carrier frequencies. Similar observations to simulations are -15

obtained as follows: (a) the harmonic distortion increases -20

with the reduction in the carrier frequency by using the -25

SVPWM; (b) using the ECPWM can reduce baseband -30

-35
harmonic distortion under a low-carrier frequency setting.
-40
1 2 3 4 5
10 10 10 10 10
B. Experimental Platform for Motor-Speed Controller Frequency(Hz)

To confirm the feasibility of the proposed modulator, the Fig. 11. Frequency analysis of the phase current produced by the
SVPWM.
motor drive system using FOC is implemented in a
micro-controller (SH7137) to drive a PMSM (HVP75), which Current
10
is connected to magnetic powder brakes (ZKB010AA). A 5
torque-measuring shaft (DATAFLEXE 22/100) is inserted 0
between the PMSM and the brakes. The input references for -5
Magnitude(dB)

the SVPWM and the ECPWM are sampled at a rate of 8 kHz, -10

and the pulse bit resolution for the SVPWM (ECPWM) is 13 -15

(8). The carrier frequency of the SVPWM is 8 kHz, whereas -20

-25
that of the ECPWM is 4 kHz. An FPGA (EP2C35F484C6) is
-30
used to receive the desired duty ratio from the -35
micro-controller and generate switching commands to -40
1 2 3 4 5
produce the asymmetric switching commands of ECPWM. 10 10 10 10 10
Frequency(Hz)
The block diagram of the motor driver using the SVPWM Fig. 12. Frequency analysis of the phase current produced by the
(ECPWM) is shown in Fig. 13 (Fig. 14). The three-phase ECPWM.
394 Journal of Power Electronics, Vol. 16, No. 1, January 2016

TABLE III TABLE V

EXPERIMENTAL RESULT: HARMONIC ANALYSIS OF THE PRODUCED SPECIFICATIONS OF POWER SWITCH
PHASE VOLTAGE IRFP360
Modulator Carrier Harmonics Harmonics VDS 400 (V)
frequency within [0 1 k] within [0 3 k]
(Hz) Hz (%) Hz (%) I D (max) 23 (A)
SVPWM 8k 2.323 2.327 RDS ( on ) 0.2 (Ω)
4k 2.457 2.483
ECPWM 4k 2.251 2.283 Qg (max) 210 (nC)
Qgs 30 (nC)
TABLE IV
Qd (nC)
EXPERIMENTAL RESULT: HARMONIC ANALYSIS OF THE PRODUCED
PHASE CURRENT
Input frequency 50 Hz
Modulat Carrier Harmonics Harmonics SVPWM
or frequency within [0 1 k] within [0 3 k]
(Hz) Hz (%) Hz (%)
8k 1.888 2.029
SVPWM ECPWM
4k 2.532 2.685
ECPWM 4k 1.592 1.751

Fig. 15. Switching commands of the SVPWM and the ECPWM.

Fig. 13. Block diagram of the implementation platform using the

SVPWM.

Fig. 14. Block diagram of the implementation platform using the

ECPWM.
(a) SVPWM.
power stage is composed of six n-channel power MOSFETs
(IRFP360). The specifications are listed in Table V. The
dead-time is set to be 2 μs to prevent arm shooting through,
and the DC-link voltage is 120 V.
C. Measured Waveforms for Motor-Speed Control
Fig. 15 shows the switching commands of the upper switch
of the first phase lag under a motor speed of 300 rpm. The
switching frequency of the ECPWM is half that of the
SVPWM. Both modulators can properly produce three-phase
current, as shown in Fig. 16. The current ripple produced by (b) ECPWM.
the ECPWM is higher than that of the SVPWM because of its Fig. 16. Produced three-phase current under a motor speed of
lower carrier frequency. 300 rpm.
For precise comparison, the harmonic distortions under
different motor speeds are shown in Table VI. Using only then obtained according to   Torque  Speed  Pin  100%  .
half of the switching number, the baseband harmonic The measured motor speed and the output torque under
distortion of the ECPWM is lower than that of the SVPWM. different speed commands are listed in Table VII. The
average input/output power within a 15-min operation is
D. Efficiency of the Motor-Speed Control System
listed in Table VIII. The average input power by using the
P
The power supplied to the system (denoted as in ) and the ECPWM is smaller than that by using the SVPWM, whereas
the efficiency of the motor driving system. The efficiency is the average output power by using the ECPWM is larger than
 Voltage Source Inverter Drive Using … 395

TABLE VI TABLE IX
SWITCHING NUMBER AND CURRENT HARMONIC DISTORTION AT MEASURED MOSFET TEMPERATURE UNDER VARIOUS MOTOR
DIFFERENT MOTOR SPEEDS SPEEDS
Motor speed (rpm) 300 400 500 Motor speed (rpm) 300 400 500
Switching number SVPWM 48 k 48 k 48 k temperature SVPWM 101.1 104.1 107.4
per second ECPWM 24 k 24 k 24 k (°C) ECPWM 77.1 79.3 80.8
Current harmonic SVPWM 1.04 0.91 0.99
within [0 250] Hz ECPWM 0.93 0.70 0.80 mechanical output power of the motor are measured to obtain
(%) that by using the SVPWM under the same motor speed
Reduction rate (%) 10.6 23.1 19.2 commands. Therefore, the efficiency of the ECPWM is
higher than that of the SVPWM. In Table VIII, the efficiency
TABLE VII
PRODUCED MOTOR SPEED AND OUTPUT TORQUE improvement is calculated according to
Motor speed command (rpm) 300 400 500 efficiency improvement  ηECPWM  ηSVPWM  ηSVPWM  100%  .
measured motor speed SVPWM 302.28 402.54 503.29 An average of 7.09% efficiency improvement is obtained
(rpm) ECPWM 302.28 402.52 503.23 by using the ECPWM, and a maximum efficiency
measured output SVPWM 1.78 1.81 1.87 improvement of 8.01% is achieved at a motor speed of
torque (Nm) ECPWM 1.81 1.88 1.91
400 rpm (refer to Table VIII).
The measured result reveals that the reduction in switching
TABLE VIII
MEASURED INPUT/OUTPUT POWER OF THE MOTOR DRIVE frequency and baseband harmonics helps to improve the
SYSTEM efficiency of the motor drive.
Motor Speed Command 300 400 500
(rpm) E. MOSFET Operating Temperature
input power SVPWM 96.37 121.76 147.54 The advantage of switching frequency reduction can also
(W) ECPWM 91.24 117.21 142.39 be observed from the temperature measurement of MOSFET.
motor SVPWM 56.35 76.30 98.56 Fig. 17 shows the temperature variation in MOSFET during
mechanical ECPWM 57.29 79.33 100.65
power (W) the 15-min operation with a motor speed of 500 rpm. The
efficiency (%) SVPWM 58.45 62.66 66.80 initial temperature (air temperature in the room) is 25 °C.
ECPWM 62.80 67.68 70.69 After 7.5-min operation, the MOSFET temperature
efficiency improvement (%) 7.44 8.01 5.82 corresponds to the following conditions: the ECPWM rises to
67 °C, whereas the SVPWM is 94 °C. Therefore, for the
same operating time, the heat dissipation requirement of the
ECPWM is lower. The temperature at the end of the
operation is 107.4 (80.8) °C by using the SVPWM (ECPWM),
which shows a great reduction in operation temperature by
using the ECPWM. Similar observations are obtained with
different motor speeds. The measured temperatures after
15-min operation are listed in Table IX. A maximum
reduction of 26.6 °C is obtained. Therefore, the proposed
method outperforms the SVPWM in reducing the operating
temperature.
(a) SVPWM. A high temperature of power MOSFET leads to low
efficiency of the inverter [29]. For every 10 °C increase in the
working temperature, the lifetime reduction in MOSFET is
approximately 40% [26]. Therefore, reducing the temperature
of switches not only lessens the heat sink requirement but
also improves both the power efficiency and the lifetime of
switches.

V. CONCLUSION
An ECPWM is proposed in this work. By adjusting the
reference signal according to the accumulated error signal,
(b) ECPWM. the proposed method can compensate for the difference in the
Fig. 17. Measured temperature within [0 15]-min operating at a desired and the produced phase voltages. The switching
speed of 500 rpm.
frequency can also be reduced with an improved baseband
396 Journal of Power Electronics, Vol. 16, No. 1, January 2016

harmonic performance by selecting the compensating rate as v1T e1  v1T r1  v1T S c qb 1 1  2 1  3 1
twice the carrier frequency.
In the simulation, a three-phase VSI with R–L load is built.
 
  STc v1 qb 1 1  2 1  3 1
T

. (A4)
 S c v1  qb 1 1  2 1  3 1
T
Results imply that the baseband harmonic distortion of the
voltage/current produced by the SVPWM increases with 0
For any values of 1 1  2 1  3 1 , v 1 e1  0
T
decreased carrier frequency. By applying the error
compensation mechanism every half-carrier period, the always holds. Following the procedures of Equs. (A3) and
(A4), we can prove from Equ. (4) that v 1 e k   0, k , which
proposed ECPWM improves the baseband harmonic under a T

low-carrier frequency setting.

implies that Equ. (A1) is satisfied.
In the first experiment, a three-phase VSI with R–L load is
built. The measured phase voltages/currents produced by the
SVPWM and the ECPWM show similar observations to that ACKNOWLEDGMENT
obtained in the simulation. A motor drive platform based on
This work was supported by the Ministry of Science and
FOC is built on Renesas SH7137 to drive a PMSM (HVP75)
Technology, Taiwan under contract MOST
with magnetic powder brakes to further confirm the
103-2221-E-155-025-.
effectiveness of the proposed modulator. The measured
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