ESD Handout 12

Embedded Systems-Lab 12 1
Lab Experiment No. 12

Design Combinational Logic Circuits
(Full-Adder, Comparator & Multiplexer)
Name: _____________________________________________________ Roll No: ___________________
Score:_________________ Signature:_____________________________ Date:______________________
LAB DATA ANALYSIS ABILITY TO

SUBJECT CALCULATION OBSERVATION/
PERFORMANCE KNOWLEDGE
AND CONDUCT PRESENTATION
AND CODING RESULTS
SCORE
INTERPRETATION EXPERIMENT
INDICATOR
PERFORMANCE OBJECTIVE:
After successful completion of this lab, students will be able to:
 Design & Synthesize of Full Adder using Xilinx ISE Software.
 Simulate Full Adder using ISIM Simulator.
 Implement Full Adder with NEXYS2 Spartan 3E Board using Xilinx ISE & Adept Software.
LAB REQUIREMENTS:
 Standard PC with Xilinx ISE Design Suite 12.3 or latest, Software installed
 Digilent Adept Software.
 NEXYS2 Spartan 3E (XC3S500K or XC3S1200K) board.
DISCUSSION:
A full adder is a logical circuit that performs an addition operation on three one-bit binary numbers
often written as a, b, and cin. The full adder produces a two-bit output sum typically represented with
the signals Cout and S. Truth Table for a 1-Bit Full Adder is given below.
a
a b Cin sum Cout
0 0 0 0 0
0 0 1 1 0 Sum
0 1 0 1 0 Cin 1-Bit Full
0 1 1 0 1 Adder Cout
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1 b
1 1 1 1 1
.
Figure 1: Full Adder Truth Table, and Signal Block
A full adder can be implemented in many different ways such as with a custom transistor-level
circuit or composed of other gates. One example implementation is with
∑ ¿ A ⨁ B ⨁ C¿
C out = A . B+(C ¿¿ ¿ .( A ⨁ B)C ¿ )¿
DESIGNING PROCEDURE:
DESIGN ENTRY
1. Invoke Xilinx ISE Design Suite Software.
“Select File > New Project”

2. Enter the Project name full_adder in the Name field. Verify that HDL is selected as the Top-
Level Source Type, and click on NEXT again click on NEXT and Click on Finish.
3. Now Create a New Source file; Go to Project > New Source.
 Select VHDL Module and Enter the source file name full_adder.
 Click on Next. Enter the Input and output Ports name and click NEXT and click
Finish.
VHDL Code for the Full adder is

LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY full_adder is
Port (a, b, Cin : in STD_LOGIC;
Sum, Cout : out STD_LOGIC;
END full_adder;
ARCHITECTURE Behavioral of full_adder IS
BEGIN
sum <= (a XOR b) XOR Cin;
Cout <= (a AND b) OR (Cin AND (a XOR b));
END Behavioral;
Simulation
After Creating project and new Source File now it is ready to simulate the Design. To simulate
the Full Adder follow the following steps.
1. In the Design Panel, select the Simulation radio button.
2. Select full_adder Behavioral file and double click on Simulator Behavioral Model in the
Process window.
3. Select the Simulation from the menu bar and click on Restart.
4. Force the input signal (a, b, cin).
5. Select the Simulation from the menu bar and click on Run. It shows the following Simulation
result of Full Adder.
Figure: 2. Simulation Result for Full adder

Synthesis
1. To synthesize the design, double click on the Synthesize Design option in the Processes
window.
2. Now the schematic diagram of the Full adder can be viewed by double clicking View RTL
Schematic under Synthesize-XST menu in the Process Window, (Figure 1.3).
3. Similarly you can view the Technology Schematic Symbol by double clicking View
Technology Schematic under Synthesize-XST menu in the Process Window, (Figure 1.4).
Figure 3: Schematic diagram for Full adder Figure 4: Technology Schematic Symbol for Full
adder
Implementation
1. Before implement the design you must create the User Constraint File UCF.
2. After creating the UCF file Single Click on full_adder.ucf file from within Project
Navigator, and then select “Edit Constraints (Text)” from the Process window.
3. Assigning the pins to inputs and outputs of Full adder as following and save Ucf file.
NET "a" LOC = "G18";

NET "b" LOC = "H18";
NET "Cin" LOC = "K18";
NET "sum” LOC = "J14";

NET "Cout" LOC = "J15";
4. After assigning the Pins double click on “Implement Design” option in the Processes
window. It will go through steps like Translate, Map and Place & Route.
5. Now create a programming file (bit stream file) of the design. This is done by clicking
once on your top-level design in the Sources Pane, followed by a double click on
“Generate Programming File” in the process window.
6. Once the programming file (bit stream file) is generated, the file has to be downloaded to
the NEXYS2 Spartan3E device.
Review Question:
Repeat the same exercise for
 4-input Multiplexer
 1-Bit Magnitude Comparator
Final Assignment:
1. Write the VHDL code for 4-Bit Full Adder, perform Synthesis process; attach the RTL
Schematic diagram and Technology Schematic diagram.
2. Simulate “4-Bit Full Adder” and attach simulation Result.
3. Write the VHDL code for 4-Bit Magnitude Comparator, perform Synthesis Process and
attach the Schematic diagram and Technology Schematic Symbol.
4. Simulate “4-Bit Magnitude Comparator” and attach result(s).
5. Write the VHDL code for 1-of-4 De-multiplexer, Simulate the design and attach result(s).

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Embedded Systems-Lab 12 1

Lab Experiment No. 12

Score:___ Signature:_ Date:________

LAB DATA ANALYSIS ABILITY TO

“Select File > New Project”

VHDL Code for the Full adder is

Figure: 2. Simulation Result for Full adder

NET "a" LOC = "G18";

NET "sum” LOC = "J14";

2. Simulate “4-Bit Full Adder” and attach simulation Result.

4. Simulate “4-Bit Magnitude Comparator” and attach result(s).

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